Changeset 61 for Deliverables/D4.1

Timestamp:

Sep 10, 2010, 5:33:59 PM (10 years ago)

Author:

sacerdot

Message:

Final version.

File:

• Deliverables/D4.1/Presentation/Paris-September-2010.tex (modified) (6 diffs)

Deliverables/D4.1/Presentation/Paris-September-2010.tex

@@ -1 +1 @@
 \documentclass[serif]{beamer}
 
-\author{Claudio Sacerdoti Coen}
+\author{Dominic Mulligan \and \alert{Claudio Sacerdoti Coen}}
 \title{A brief introduction to the 8051 processor \\\vspace{\baselineskip} \small{CerCo project meeting, Paris, September 2010}}
 \date{\today}
@@ -13 +13 @@
 \begin{frame}
 \frametitle{Vital statistics I}
-The 8051 is:
+The 8051 (a.k.a. 8052, 80C51, MCS51) is:
 \begin{itemize}
 \item
@@ -22 +22 @@
 128 bytes of internal RAM, subdivided into different sections (the register banks, bit memory, stack space and general RAM)
 \item
-At most, stack space is 80 bytes, but often less (very small!)
+At most, stack space is 80 bytes, but often less (very small!)\\
+But ways of having the stack in external RAM\ldots
 \end{itemize}
 \end{frame}
@@ -33 +34 @@
 \item
 Serial (UART) port and 32 input/output lines
-\item
-Two-levels of priority for interrupts
+\item Interrupts only for I/O, could be entirely replaced by polling
+\item Two levels of priority for interrupts (cfr. four register banks)
+\item All instructions take a fixed, known-in-advance number of clock-cycles
+\end{itemize}
+\end{frame}
+
+\begin{frame}
+\frametitle{Memory model}
+Several distinct (not disjoint) memory areas and addressing mode (hence
+pointer type):
+\begin{itemize}
+ \item Code memory; ad-hoc access, read-only, may be partially on-die
+ \item Low internal RAM (128 bytes); direct + indirect address
+ \item High internal RAM (128 bytes); indirect access only
+ \item External RAM; ad-hoc access only via DPTR (16 bits SFR)
+ \item Low External RAM; ad-hoc indirect access, overlaps with External RAM
+ \item Memory-mapped I/O + Special Function Registers (SFRs); direct access only
+ \item Bit memory (256 addresses); ad-hoc access, 1/2 overlaps with
+       Low Internal RAM, 1/2 overlaps with Special Function Registers
+ \item Four register banks, 8 registers each; direct + indirect + ad-hoc
+       access, fully overlaps with Low Internal RAM
+\end{itemize}
+\end{frame}
+
+\begin{frame}
+\frametitle{Addressing modes and address spaces}
+Let's recapitulate the main addressing modes and pointer types:
+\begin{itemize}
+\item direct mode (\_\_data / \_\_near modifiers in SDCC syntax),
+      to access Low Internal RAM
+\item direct mode (fixed address in SDCC syntax), to access SFRs
+\item indirect mode (\_\_idata modifier in SDCC syntax),
+      to access (Low +) High Internal RAM
+\item external mode (\_\_xdata / \_\_far modifier in SDCC syntax)
+      to access External RAM
+\item indirect external mode a.k.a. paged data (\_\_pdata modifier in SDCC
+      syntax) to access the first 256 bytex of External RAM
+\item code mode (\_\_code modifier in SDCC syntax) to access Code Memory
+\item bit mode (\_\_bit modifier in SDCC syntax) to access Bit Memory
+\end{itemize}
+\end{frame}
+
+\begin{frame}
+\frametitle{SDCC and addressing modes}
+Memory model + ad-hoc modifiers
+\begin{itemize}
+\item the memory model (Small/Medium/Large) determines where un-modified
+      variable declarations are put (e.g. \texttt{int foo;})
+\item modified variables are put where the user wants them to be
+      (e.g. \texttt \_\_xdata int foo;)
+\item the \texttt{\_\_using} modifier is used to switch memory bank for
+      registers (see next slide), e.g. in interrupt routines
+\item pointers and pointers passing in SDCC:
+ \begin{itemize}
+  \item generic pointers (e.g. \texttt{int *foo;}); three bytes long
+        (1 selector + 16 bits at most)
+  \item labelled pointers (e.g. \texttt{int * \_\_idata foo;}); one/two bytes
+        long
+ \end{itemize}
+\end{itemize}
+\end{frame}
+
+\begin{frame}
+\frametitle{calling convention (SDCC)}
+\begin{itemize}
+\item all Rx register are caller-saved
+\item DPL/DPH, B and ACC are used for first parameter/return value passing:
+ \begin{itemize}
+  \item 1 byte: DPL
+  \item 2 bytes: DPL + DPH
+  \item 3 bytes: DPH + DPL + B (generic pointers: B=0x00 xdata, B=0xe0 idata,
+        B=0x60 pdata, B=0x80 code)
+  \item 4 bytes: DPH + DPL + B + ACC
+ \end{itemize}
+\item first bit argument is passed in a pre-defined bit address
+\item remaining arguments passed on the stack
 \end{itemize}
 \end{frame}
@@ -51 +126 @@
 \item
 If we decide to use bank 3, R4 is no longer identified with memory location 04h, but instead shifted to 1CH.
+\item Note: most operands work on the accumulator register A that is a SFR
+ and not an Rx register
 \end{itemize}
 \end{frame}
@@ -200 +277 @@
 \end{frame}
 
+\begin{frame}
+\frametitle{Executable semantics issues}
+Assembly executable semantics vs real code executable semantics
+\begin{itemize}
+\item Labels and jumps/calls: several opcodes according to the target distance.\\
+      Introduce pseudo-instructions?
+\item Labels for data: labels in different memory areas require totally
+      different opcodes
+\item What to model? (I/O? timers? interrupts?)
+\item How to model I/O, timers and interrupts?
+\end{itemize}
+Right now, only the real code executable semantics is (partially) implemented
+together with fetching and assemblying (but no pseudo-instructions and no labels).
+\end{frame}
+
 \end{document}