Changeset 61

Sep 10, 2010, 5:33:59 PM (11 years ago)

Final version.

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  • Deliverables/D4.1/Presentation/Paris-September-2010.tex

    r38 r61  
    3 \author{Claudio Sacerdoti Coen}
     3\author{Dominic Mulligan \and \alert{Claudio Sacerdoti Coen}}
    44\title{A brief introduction to the 8051 processor \\\vspace{\baselineskip} \small{CerCo project meeting, Paris, September 2010}}
    1414\frametitle{Vital statistics I}
    15 The 8051 is:
     15The 8051 (a.k.a. 8052, 80C51, MCS51) is:
    2222128 bytes of internal RAM, subdivided into different sections (the register banks, bit memory, stack space and general RAM)
    24 At most, stack space is 80 bytes, but often less (very small!)
     24At most, stack space is 80 bytes, but often less (very small!)\\
     25But ways of having the stack in external RAM\ldots
    3435Serial (UART) port and 32 input/output lines
    35 \item
    36 Two-levels of priority for interrupts
     36\item Interrupts only for I/O, could be entirely replaced by polling
     37\item Two levels of priority for interrupts (cfr. four register banks)
     38\item All instructions take a fixed, known-in-advance number of clock-cycles
     43\frametitle{Memory model}
     44Several distinct (not disjoint) memory areas and addressing mode (hence
     45pointer type):
     47 \item Code memory; ad-hoc access, read-only, may be partially on-die
     48 \item Low internal RAM (128 bytes); direct + indirect address
     49 \item High internal RAM (128 bytes); indirect access only
     50 \item External RAM; ad-hoc access only via DPTR (16 bits SFR)
     51 \item Low External RAM; ad-hoc indirect access, overlaps with External RAM
     52 \item Memory-mapped I/O + Special Function Registers (SFRs); direct access only
     53 \item Bit memory (256 addresses); ad-hoc access, 1/2 overlaps with
     54       Low Internal RAM, 1/2 overlaps with Special Function Registers
     55 \item Four register banks, 8 registers each; direct + indirect + ad-hoc
     56       access, fully overlaps with Low Internal RAM
     61\frametitle{Addressing modes and address spaces}
     62Let's recapitulate the main addressing modes and pointer types:
     64\item direct mode (\_\_data / \_\_near modifiers in SDCC syntax),
     65      to access Low Internal RAM
     66\item direct mode (fixed address in SDCC syntax), to access SFRs
     67\item indirect mode (\_\_idata modifier in SDCC syntax),
     68      to access (Low +) High Internal RAM
     69\item external mode (\_\_xdata / \_\_far modifier in SDCC syntax)
     70      to access External RAM
     71\item indirect external mode a.k.a. paged data (\_\_pdata modifier in SDCC
     72      syntax) to access the first 256 bytex of External RAM
     73\item code mode (\_\_code modifier in SDCC syntax) to access Code Memory
     74\item bit mode (\_\_bit modifier in SDCC syntax) to access Bit Memory
     79\frametitle{SDCC and addressing modes}
     80Memory model + ad-hoc modifiers
     82\item the memory model (Small/Medium/Large) determines where un-modified
     83      variable declarations are put (e.g. \texttt{int foo;})
     84\item modified variables are put where the user wants them to be
     85      (e.g. \texttt \_\_xdata int foo;)
     86\item the \texttt{\_\_using} modifier is used to switch memory bank for
     87      registers (see next slide), e.g. in interrupt routines
     88\item pointers and pointers passing in SDCC:
     89 \begin{itemize}
     90  \item generic pointers (e.g. \texttt{int *foo;}); three bytes long
     91        (1 selector + 16 bits at most)
     92  \item labelled pointers (e.g. \texttt{int * \_\_idata foo;}); one/two bytes
     93        long
     94 \end{itemize}
     99\frametitle{calling convention (SDCC)}
     101\item all Rx register are caller-saved
     102\item DPL/DPH, B and ACC are used for first parameter/return value passing:
     103 \begin{itemize}
     104  \item 1 byte: DPL
     105  \item 2 bytes: DPL + DPH
     106  \item 3 bytes: DPH + DPL + B (generic pointers: B=0x00 xdata, B=0xe0 idata,
     107        B=0x60 pdata, B=0x80 code)
     108  \item 4 bytes: DPH + DPL + B + ACC
     109 \end{itemize}
     110\item first bit argument is passed in a pre-defined bit address
     111\item remaining arguments passed on the stack
    52127If we decide to use bank 3, R4 is no longer identified with memory location 04h, but instead shifted to 1CH.
     128\item Note: most operands work on the accumulator register A that is a SFR
     129 and not an Rx register
     280\frametitle{Executable semantics issues}
     281Assembly executable semantics vs real code executable semantics
     283\item Labels and jumps/calls: several opcodes according to the target distance.\\
     284      Introduce pseudo-instructions?
     285\item Labels for data: labels in different memory areas require totally
     286      different opcodes
     287\item What to model? (I/O? timers? interrupts?)
     288\item How to model I/O, timers and interrupts?
     290Right now, only the real code executable semantics is (partially) implemented
     291together with fetching and assemblying (but no pseudo-instructions and no labels).
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