Changeset 382


Ignore:
Timestamp:
Dec 7, 2010, 11:23:06 AM (9 years ago)
Author:
mulligan
Message:

Changes from this morning.

Location:
Deliverables/D4.1/Report
Files:
4 added
1 edited

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  • Deliverables/D4.1/Report/report.tex

    r380 r382  
    77\usepackage{amssymb}
    88\usepackage[english]{babel}
     9\usepackage{graphicx}
    910\usepackage[utf8x]{inputenc}
    1011\usepackage{listings}
     
    107108\label{subsect.task}
    108109
    109 The Grant Agreement states the D4.1/D4.2 deliverables consist of:
     110The Grant Agreement states the D4.1/D4.2 deliverables consist of the following tasks:
    110111
    111112\begin{quotation}
     
    124125\label{subsect.brief.overview.target.processor}
    125126
    126 \begin{figure}
    127 \caption{High level overview of the 8051 memory layout}
    128 \label{fig.memory.layout}
    129 \end{figure}
    130 
    131127The MCS-51 is an eight bit microprocessor introduced by Intel in the late 1970s.
    132128Commonly called the 8051, in the three decades since its introduction the processor has become a highly popular target for embedded systems engineers.
     
    146142Bit memory, followed by a small amount of stack space resides in the memory space immediately after the register banks.
    147143What remains of the IRAM may be treated as general purpose memory.
     144A schematic view of IRAM layout is provided in Figure~\ref{fig.iram.layout}.
    148145
    149146External RAM (XRAM), limited to 64 kilobytes, is optional, and may be provided on or off chip, depending on the manufacturer.
    150147XRAM is accessed using a dedicated instruction.
    151 External code memory is often stored in the form of an EPROM, and limited to 64 kilobytes in size.
    152 However, depending on the particular manufacturer and processor model, a dedicated on-die read-only memory area for program code may also be supplied (the processor has a Harvard architecture, where program code and data are separated).
     148External code memory (XCODE) is often stored in the form of an EPROM, and limited to 64 kilobytes in size.
     149However, depending on the particular manufacturer and processor model, a dedicated on-die read-only memory area for program code (ICODE) may also be supplied.
    153150
    154151Memory may be addressed in numerous ways: immediate, direct, indirect, external direct and code indirect.
     
    174171The programmer is free to handle serial input and output manually, by poking serial flags in the SFRs.
    175172Similarly, `exceptional circumstances' that would otherwise trigger an interrupt on more modern processors, for example, division by zero, are also signalled by setting flags.
     173
     174\begin{figure}[t]
     175\begin{center}
     176\includegraphics[scale=0.5]{memorylayout.png}
     177\end{center}
     178\caption{High level overview of the 8051 memory layout}
     179\label{fig.memory.layout}
     180\end{figure}
     181
     182\begin{figure}[t]
     183\begin{center}
     184\includegraphics[scale=0.5]{iramlayout.png}
     185\end{center}
     186\caption{Schematic view of 8051 IRAM layout}
     187\label{fig.iram.layout}
     188\end{figure}
    176189
    177190\section{The emulator in O'Caml}
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