Changeset 36

Sep 3, 2010, 5:05:30 PM (8 years ago)

More on Claudio's presentation: upto interrupts and their handling.

1 edited


  • Deliverables/D4.1/Presentation/Paris-September-2010.tex

    r34 r36  
    8585\frametitle{Special function registers (SFRs)}
     88The special function registers (SFRs) are areas of memory dedicated to controlling specific functionality of the 8051.
     90The 8051 maintains the illusion that SFRs are a part of internal memory: writing 1 to the serial port is achieved by moving 01h to memory location 99h (an SFR controlling serial port activity).
     92However, SFRs are \emph{not} part of internal memory: any modification to memory addresses 00h--7Fh modifies internal RAM, whereas 80h--7Fh modifies the SFRs.
     94On the standard 8051, there are 21 SFRs, falling into three basic classes: those related to I/O, those related to controlling the operation of the processor, and auxiliary SFRs.
     96Derivative processors are also free to add bespoke SFRs that control additional functionality of their chips.
     101\frametitle{I/O SFRs}
     104The 32 I/O lines of the 8051 are controlled by four SFRs: P0--P4.
     106Individual I/O lines are controlled by setting bits of the requisite SFR.
     108Bit 0 of port 0 is pin P0.0, for instance.  Writing 1 to this bit will send a `high' level on the corresponding output line, whereas 0 corresponds to a `low' level.
     113\frametitle{Control SFRs (I)}
     116There are seven control SFRs: PCON, TCON, TMOD, SCON, IE, IP and PSW.
     118Setting PCON places the processor into a power saving mode.
     120TCON is a control flag for the processor's timers, and signals when they overflow.  Further, some non-timer related functionality is included, related to how external interrupts are activated.
     122TMOD sets the operating mode of the timer: an 8 bit timer that autoreloads, one 16 bit timer, a 13 bit timer, or two separate 8 bit timers.
     124IE is the `interrupt enable' flag, used to enable and disable specific interrupts.
     129\frametitle{Control SFRs (II)}
     132IP is the `interrupt priority' flag.  The 8051 has two interrupt priority modes: low and high.
     134An interrupt with a high priority can always interrupt another interrupt of lower priority.  An interrupt with high priority can never be interrupted (even by another with high priority).
     136PSW is the `program status word'.  This contains a number of important flags, for instance, Carry, Overflow, Parity, etc.  This SFR also contains the flag used to select the active register bank.
     141\frametitle{Auxiliary SFRs}
     144There are 10 auxiliary SFRs: SP, DPL, DPH, TL0, TL1, TH0, TH1, SBUF, ACC and B.
     146SP is the stack pointer.
     148DPL and DPH are the `data pointer high' and `data pointer low' SFRs.  These act together to give a 16 bit data pointer used in operations regarding external RAM and code memory.
     150Oddity: though there's an explicit instruction to increment the DPTR, there's no instruction to decrement it.
     152TL0--TH1 are the timers.
     154SBUF is the 8051's serial buffer.
     156ACC and B are two accumulator registers, with ACC being the primary accumulator.
     158Only a small number of operations involve the B register, so this can optionally be used as an additional general purpose register.
     163\frametitle{Addressing modes}
     166The 8051 has three modes for addressing memory: immediate, direct and indirect.
     168When using direct addressing, any location between addresses 00h and 7Fh is internal RAM, whereas addresses between 80h and FFh are SFRs.
     170Oddity: the 8052 provides 128 bit extra internal RAM, and this cannot be accessed through direct addressing (address clash with the SFRs), use indirect addressing instead.
     172Indirect addressing \emph{always} refers to internal RAM, never to an SFR.
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