Changeset 36

Ignore:
Timestamp:
Sep 3, 2010, 5:05:30 PM (9 years ago)
Message:

More on Claudio's presentation: upto interrupts and their handling.

File:
1 edited

Legend:

Unmodified
 r34 \begin{frame} \frametitle{Special function registers (SFRs)} \begin{itemize} \item The special function registers (SFRs) are areas of memory dedicated to controlling specific functionality of the 8051. \item The 8051 maintains the illusion that SFRs are a part of internal memory: writing 1 to the serial port is achieved by moving 01h to memory location 99h (an SFR controlling serial port activity). \item However, SFRs are \emph{not} part of internal memory: any modification to memory addresses 00h--7Fh modifies internal RAM, whereas 80h--7Fh modifies the SFRs. \item On the standard 8051, there are 21 SFRs, falling into three basic classes: those related to I/O, those related to controlling the operation of the processor, and auxiliary SFRs. \item Derivative processors are also free to add bespoke SFRs that control additional functionality of their chips. \end{itemize} \end{frame} \begin{frame} \frametitle{I/O SFRs} \begin{itemize} \item The 32 I/O lines of the 8051 are controlled by four SFRs: P0--P4. \item Individual I/O lines are controlled by setting bits of the requisite SFR. \item Bit 0 of port 0 is pin P0.0, for instance.  Writing 1 to this bit will send a high' level on the corresponding output line, whereas 0 corresponds to a low' level. \end{itemize} \end{frame} \begin{frame} \frametitle{Control SFRs (I)} \begin{itemize} \item There are seven control SFRs: PCON, TCON, TMOD, SCON, IE, IP and PSW. \item Setting PCON places the processor into a power saving mode. \item TCON is a control flag for the processor's timers, and signals when they overflow.  Further, some non-timer related functionality is included, related to how external interrupts are activated. \item TMOD sets the operating mode of the timer: an 8 bit timer that autoreloads, one 16 bit timer, a 13 bit timer, or two separate 8 bit timers. \item IE is the interrupt enable' flag, used to enable and disable specific interrupts. \end{itemize} \end{frame} \begin{frame} \frametitle{Control SFRs (II)} \begin{itemize} \item IP is the interrupt priority' flag.  The 8051 has two interrupt priority modes: low and high. \item An interrupt with a high priority can always interrupt another interrupt of lower priority.  An interrupt with high priority can never be interrupted (even by another with high priority). \item PSW is the program status word'.  This contains a number of important flags, for instance, Carry, Overflow, Parity, etc.  This SFR also contains the flag used to select the active register bank. \end{itemize} \end{frame} \begin{frame} \frametitle{Auxiliary SFRs} \begin{itemize} \item There are 10 auxiliary SFRs: SP, DPL, DPH, TL0, TL1, TH0, TH1, SBUF, ACC and B. \item SP is the stack pointer. \item DPL and DPH are the data pointer high' and `data pointer low' SFRs.  These act together to give a 16 bit data pointer used in operations regarding external RAM and code memory. \item Oddity: though there's an explicit instruction to increment the DPTR, there's no instruction to decrement it. \item TL0--TH1 are the timers. \item SBUF is the 8051's serial buffer. \item ACC and B are two accumulator registers, with ACC being the primary accumulator. \item Only a small number of operations involve the B register, so this can optionally be used as an additional general purpose register. \end{itemize} \end{frame} \begin{frame} \frametitle{Addressing modes} \begin{itemize} \item The 8051 has three modes for addressing memory: immediate, direct and indirect. \item When using direct addressing, any location between addresses 00h and 7Fh is internal RAM, whereas addresses between 80h and FFh are SFRs. \item Oddity: the 8052 provides 128 bit extra internal RAM, and this cannot be accessed through direct addressing (address clash with the SFRs), use indirect addressing instead. \item Indirect addressing \emph{always} refers to internal RAM, never to an SFR. \end{itemize} \end{frame} \begin{frame} \frametitle{Interrupts} \end{frame}