Changeset 2951 for extracted/aSM.ml
 Timestamp:
 Mar 25, 2013, 11:30:01 PM (7 years ago)
 File:

 1 edited
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extracted/aSM.ml
r2873 r2951 113 113 > 'a1) > addressing_mode > 'a1 **) 114 114 let rec addressing_mode_rect_Type4 h_DIRECT h_INDIRECT h_EXT_INDIRECT h_REGISTER h_ACC_A h_ACC_B h_DPTR h_DATA h_DATA16 h_ACC_DPTR h_ACC_PC h_EXT_INDIRECT_DPTR h_INDIRECT_DPTR h_CARRY h_BIT_ADDR h_N_BIT_ADDR h_RELATIVE h_ADDR11 h_ADDR16 = function 115  DIRECT x_ 22221 > h_DIRECT x_22221116  INDIRECT x_ 22222 > h_INDIRECT x_22222117  EXT_INDIRECT x_ 22223 > h_EXT_INDIRECT x_22223118  REGISTER x_ 22224 > h_REGISTER x_22224115  DIRECT x_33 > h_DIRECT x_33 116  INDIRECT x_34 > h_INDIRECT x_34 117  EXT_INDIRECT x_35 > h_EXT_INDIRECT x_35 118  REGISTER x_36 > h_REGISTER x_36 119 119  ACC_A > h_ACC_A 120 120  ACC_B > h_ACC_B 121 121  DPTR > h_DPTR 122  DATA x_ 22225 > h_DATA x_22225123  DATA16 x_ 22226 > h_DATA16 x_22226122  DATA x_37 > h_DATA x_37 123  DATA16 x_38 > h_DATA16 x_38 124 124  ACC_DPTR > h_ACC_DPTR 125 125  ACC_PC > h_ACC_PC … … 127 127  INDIRECT_DPTR > h_INDIRECT_DPTR 128 128  CARRY > h_CARRY 129  BIT_ADDR x_ 22227 > h_BIT_ADDR x_22227130  N_BIT_ADDR x_ 22228 > h_N_BIT_ADDR x_22228131  RELATIVE x_ 22229 > h_RELATIVE x_22229132  ADDR11 x_ 22230 > h_ADDR11 x_22230133  ADDR16 x_ 22231 > h_ADDR16 x_22231129  BIT_ADDR x_39 > h_BIT_ADDR x_39 130  N_BIT_ADDR x_40 > h_N_BIT_ADDR x_40 131  RELATIVE x_41 > h_RELATIVE x_41 132  ADDR11 x_42 > h_ADDR11 x_42 133  ADDR16 x_43 > h_ADDR16 x_43 134 134 135 135 (** val addressing_mode_rect_Type5 : … … 141 141 > 'a1) > addressing_mode > 'a1 **) 142 142 let rec addressing_mode_rect_Type5 h_DIRECT h_INDIRECT h_EXT_INDIRECT h_REGISTER h_ACC_A h_ACC_B h_DPTR h_DATA h_DATA16 h_ACC_DPTR h_ACC_PC h_EXT_INDIRECT_DPTR h_INDIRECT_DPTR h_CARRY h_BIT_ADDR h_N_BIT_ADDR h_RELATIVE h_ADDR11 h_ADDR16 = function 143  DIRECT x_ 22252 > h_DIRECT x_22252144  INDIRECT x_ 22253 > h_INDIRECT x_22253145  EXT_INDIRECT x_ 22254 > h_EXT_INDIRECT x_22254146  REGISTER x_ 22255 > h_REGISTER x_22255143  DIRECT x_64 > h_DIRECT x_64 144  INDIRECT x_65 > h_INDIRECT x_65 145  EXT_INDIRECT x_66 > h_EXT_INDIRECT x_66 146  REGISTER x_67 > h_REGISTER x_67 147 147  ACC_A > h_ACC_A 148 148  ACC_B > h_ACC_B 149 149  DPTR > h_DPTR 150  DATA x_ 22256 > h_DATA x_22256151  DATA16 x_ 22257 > h_DATA16 x_22257150  DATA x_68 > h_DATA x_68 151  DATA16 x_69 > h_DATA16 x_69 152 152  ACC_DPTR > h_ACC_DPTR 153 153  ACC_PC > h_ACC_PC … … 155 155  INDIRECT_DPTR > h_INDIRECT_DPTR 156 156  CARRY > h_CARRY 157  BIT_ADDR x_ 22258 > h_BIT_ADDR x_22258158  N_BIT_ADDR x_ 22259 > h_N_BIT_ADDR x_22259159  RELATIVE x_ 22260 > h_RELATIVE x_22260160  ADDR11 x_ 22261 > h_ADDR11 x_22261161  ADDR16 x_ 22262 > h_ADDR16 x_22262157  BIT_ADDR x_70 > h_BIT_ADDR x_70 158  N_BIT_ADDR x_71 > h_N_BIT_ADDR x_71 159  RELATIVE x_72 > h_RELATIVE x_72 160  ADDR11 x_73 > h_ADDR11 x_73 161  ADDR16 x_74 > h_ADDR16 x_74 162 162 163 163 (** val addressing_mode_rect_Type3 : … … 169 169 > 'a1) > addressing_mode > 'a1 **) 170 170 let rec addressing_mode_rect_Type3 h_DIRECT h_INDIRECT h_EXT_INDIRECT h_REGISTER h_ACC_A h_ACC_B h_DPTR h_DATA h_DATA16 h_ACC_DPTR h_ACC_PC h_EXT_INDIRECT_DPTR h_INDIRECT_DPTR h_CARRY h_BIT_ADDR h_N_BIT_ADDR h_RELATIVE h_ADDR11 h_ADDR16 = function 171  DIRECT x_ 22283 > h_DIRECT x_22283172  INDIRECT x_ 22284 > h_INDIRECT x_22284173  EXT_INDIRECT x_ 22285 > h_EXT_INDIRECT x_22285174  REGISTER x_ 22286 > h_REGISTER x_22286171  DIRECT x_95 > h_DIRECT x_95 172  INDIRECT x_96 > h_INDIRECT x_96 173  EXT_INDIRECT x_97 > h_EXT_INDIRECT x_97 174  REGISTER x_98 > h_REGISTER x_98 175 175  ACC_A > h_ACC_A 176 176  ACC_B > h_ACC_B 177 177  DPTR > h_DPTR 178  DATA x_ 22287 > h_DATA x_22287179  DATA16 x_ 22288 > h_DATA16 x_22288178  DATA x_99 > h_DATA x_99 179  DATA16 x_100 > h_DATA16 x_100 180 180  ACC_DPTR > h_ACC_DPTR 181 181  ACC_PC > h_ACC_PC … … 183 183  INDIRECT_DPTR > h_INDIRECT_DPTR 184 184  CARRY > h_CARRY 185  BIT_ADDR x_ 22289 > h_BIT_ADDR x_22289186  N_BIT_ADDR x_ 22290 > h_N_BIT_ADDR x_22290187  RELATIVE x_ 22291 > h_RELATIVE x_22291188  ADDR11 x_ 22292 > h_ADDR11 x_22292189  ADDR16 x_ 22293 > h_ADDR16 x_22293185  BIT_ADDR x_101 > h_BIT_ADDR x_101 186  N_BIT_ADDR x_102 > h_N_BIT_ADDR x_102 187  RELATIVE x_103 > h_RELATIVE x_103 188  ADDR11 x_104 > h_ADDR11 x_104 189  ADDR16 x_105 > h_ADDR16 x_105 190 190 191 191 (** val addressing_mode_rect_Type2 : … … 197 197 > 'a1) > addressing_mode > 'a1 **) 198 198 let rec addressing_mode_rect_Type2 h_DIRECT h_INDIRECT h_EXT_INDIRECT h_REGISTER h_ACC_A h_ACC_B h_DPTR h_DATA h_DATA16 h_ACC_DPTR h_ACC_PC h_EXT_INDIRECT_DPTR h_INDIRECT_DPTR h_CARRY h_BIT_ADDR h_N_BIT_ADDR h_RELATIVE h_ADDR11 h_ADDR16 = function 199  DIRECT x_ 22314 > h_DIRECT x_22314200  INDIRECT x_ 22315 > h_INDIRECT x_22315201  EXT_INDIRECT x_ 22316 > h_EXT_INDIRECT x_22316202  REGISTER x_ 22317 > h_REGISTER x_22317199  DIRECT x_126 > h_DIRECT x_126 200  INDIRECT x_127 > h_INDIRECT x_127 201  EXT_INDIRECT x_128 > h_EXT_INDIRECT x_128 202  REGISTER x_129 > h_REGISTER x_129 203 203  ACC_A > h_ACC_A 204 204  ACC_B > h_ACC_B 205 205  DPTR > h_DPTR 206  DATA x_ 22318 > h_DATA x_22318207  DATA16 x_ 22319 > h_DATA16 x_22319206  DATA x_130 > h_DATA x_130 207  DATA16 x_131 > h_DATA16 x_131 208 208  ACC_DPTR > h_ACC_DPTR 209 209  ACC_PC > h_ACC_PC … … 211 211  INDIRECT_DPTR > h_INDIRECT_DPTR 212 212  CARRY > h_CARRY 213  BIT_ADDR x_ 22320 > h_BIT_ADDR x_22320214  N_BIT_ADDR x_ 22321 > h_N_BIT_ADDR x_22321215  RELATIVE x_ 22322 > h_RELATIVE x_22322216  ADDR11 x_ 22323 > h_ADDR11 x_22323217  ADDR16 x_ 22324 > h_ADDR16 x_22324213  BIT_ADDR x_132 > h_BIT_ADDR x_132 214  N_BIT_ADDR x_133 > h_N_BIT_ADDR x_133 215  RELATIVE x_134 > h_RELATIVE x_134 216  ADDR11 x_135 > h_ADDR11 x_135 217  ADDR16 x_136 > h_ADDR16 x_136 218 218 219 219 (** val addressing_mode_rect_Type1 : … … 225 225 > 'a1) > addressing_mode > 'a1 **) 226 226 let rec addressing_mode_rect_Type1 h_DIRECT h_INDIRECT h_EXT_INDIRECT h_REGISTER h_ACC_A h_ACC_B h_DPTR h_DATA h_DATA16 h_ACC_DPTR h_ACC_PC h_EXT_INDIRECT_DPTR h_INDIRECT_DPTR h_CARRY h_BIT_ADDR h_N_BIT_ADDR h_RELATIVE h_ADDR11 h_ADDR16 = function 227  DIRECT x_ 22345 > h_DIRECT x_22345228  INDIRECT x_ 22346 > h_INDIRECT x_22346229  EXT_INDIRECT x_ 22347 > h_EXT_INDIRECT x_22347230  REGISTER x_ 22348 > h_REGISTER x_22348227  DIRECT x_157 > h_DIRECT x_157 228  INDIRECT x_158 > h_INDIRECT x_158 229  EXT_INDIRECT x_159 > h_EXT_INDIRECT x_159 230  REGISTER x_160 > h_REGISTER x_160 231 231  ACC_A > h_ACC_A 232 232  ACC_B > h_ACC_B 233 233  DPTR > h_DPTR 234  DATA x_ 22349 > h_DATA x_22349235  DATA16 x_ 22350 > h_DATA16 x_22350234  DATA x_161 > h_DATA x_161 235  DATA16 x_162 > h_DATA16 x_162 236 236  ACC_DPTR > h_ACC_DPTR 237 237  ACC_PC > h_ACC_PC … … 239 239  INDIRECT_DPTR > h_INDIRECT_DPTR 240 240  CARRY > h_CARRY 241  BIT_ADDR x_ 22351 > h_BIT_ADDR x_22351242  N_BIT_ADDR x_ 22352 > h_N_BIT_ADDR x_22352243  RELATIVE x_ 22353 > h_RELATIVE x_22353244  ADDR11 x_ 22354 > h_ADDR11 x_22354245  ADDR16 x_ 22355 > h_ADDR16 x_22355241  BIT_ADDR x_163 > h_BIT_ADDR x_163 242  N_BIT_ADDR x_164 > h_N_BIT_ADDR x_164 243  RELATIVE x_165 > h_RELATIVE x_165 244  ADDR11 x_166 > h_ADDR11 x_166 245  ADDR16 x_167 > h_ADDR16 x_167 246 246 247 247 (** val addressing_mode_rect_Type0 : … … 253 253 > 'a1) > addressing_mode > 'a1 **) 254 254 let rec addressing_mode_rect_Type0 h_DIRECT h_INDIRECT h_EXT_INDIRECT h_REGISTER h_ACC_A h_ACC_B h_DPTR h_DATA h_DATA16 h_ACC_DPTR h_ACC_PC h_EXT_INDIRECT_DPTR h_INDIRECT_DPTR h_CARRY h_BIT_ADDR h_N_BIT_ADDR h_RELATIVE h_ADDR11 h_ADDR16 = function 255  DIRECT x_ 22376 > h_DIRECT x_22376256  INDIRECT x_ 22377 > h_INDIRECT x_22377257  EXT_INDIRECT x_ 22378 > h_EXT_INDIRECT x_22378258  REGISTER x_ 22379 > h_REGISTER x_22379255  DIRECT x_188 > h_DIRECT x_188 256  INDIRECT x_189 > h_INDIRECT x_189 257  EXT_INDIRECT x_190 > h_EXT_INDIRECT x_190 258  REGISTER x_191 > h_REGISTER x_191 259 259  ACC_A > h_ACC_A 260 260  ACC_B > h_ACC_B 261 261  DPTR > h_DPTR 262  DATA x_ 22380 > h_DATA x_22380263  DATA16 x_ 22381 > h_DATA16 x_22381262  DATA x_192 > h_DATA x_192 263  DATA16 x_193 > h_DATA16 x_193 264 264  ACC_DPTR > h_ACC_DPTR 265 265  ACC_PC > h_ACC_PC … … 267 267  INDIRECT_DPTR > h_INDIRECT_DPTR 268 268  CARRY > h_CARRY 269  BIT_ADDR x_ 22382 > h_BIT_ADDR x_22382270  N_BIT_ADDR x_ 22383 > h_N_BIT_ADDR x_22383271  RELATIVE x_ 22384 > h_RELATIVE x_22384272  ADDR11 x_ 22385 > h_ADDR11 x_22385273  ADDR16 x_ 22386 > h_ADDR16 x_22386269  BIT_ADDR x_194 > h_BIT_ADDR x_194 270  N_BIT_ADDR x_195 > h_N_BIT_ADDR x_195 271  RELATIVE x_196 > h_RELATIVE x_196 272  ADDR11 x_197 > h_ADDR11 x_197 273  ADDR16 x_198 > h_ADDR16 x_198 274 274 275 275 (** val addressing_mode_inv_rect_Type4 : … … 1926 1926 Nat.nat > addressing_mode_tag Vector.vector > (addressing_mode > __ > 1927 1927 'a1) > subaddressing_mode > 'a1 **) 1928 let rec subaddressing_mode_rect_Type4 n l h_mk_subaddressing_mode x_ 22854=1929 let subaddressing_modeel = x_ 22854in1928 let rec subaddressing_mode_rect_Type4 n l h_mk_subaddressing_mode x_666 = 1929 let subaddressing_modeel = x_666 in 1930 1930 h_mk_subaddressing_mode subaddressing_modeel __ 1931 1931 … … 1933 1933 Nat.nat > addressing_mode_tag Vector.vector > (addressing_mode > __ > 1934 1934 'a1) > subaddressing_mode > 'a1 **) 1935 let rec subaddressing_mode_rect_Type5 n l h_mk_subaddressing_mode x_ 22856=1936 let subaddressing_modeel = x_ 22856in1935 let rec subaddressing_mode_rect_Type5 n l h_mk_subaddressing_mode x_668 = 1936 let subaddressing_modeel = x_668 in 1937 1937 h_mk_subaddressing_mode subaddressing_modeel __ 1938 1938 … … 1940 1940 Nat.nat > addressing_mode_tag Vector.vector > (addressing_mode > __ > 1941 1941 'a1) > subaddressing_mode > 'a1 **) 1942 let rec subaddressing_mode_rect_Type3 n l h_mk_subaddressing_mode x_ 22858=1943 let subaddressing_modeel = x_ 22858in1942 let rec subaddressing_mode_rect_Type3 n l h_mk_subaddressing_mode x_670 = 1943 let subaddressing_modeel = x_670 in 1944 1944 h_mk_subaddressing_mode subaddressing_modeel __ 1945 1945 … … 1947 1947 Nat.nat > addressing_mode_tag Vector.vector > (addressing_mode > __ > 1948 1948 'a1) > subaddressing_mode > 'a1 **) 1949 let rec subaddressing_mode_rect_Type2 n l h_mk_subaddressing_mode x_ 22860=1950 let subaddressing_modeel = x_ 22860in1949 let rec subaddressing_mode_rect_Type2 n l h_mk_subaddressing_mode x_672 = 1950 let subaddressing_modeel = x_672 in 1951 1951 h_mk_subaddressing_mode subaddressing_modeel __ 1952 1952 … … 1954 1954 Nat.nat > addressing_mode_tag Vector.vector > (addressing_mode > __ > 1955 1955 'a1) > subaddressing_mode > 'a1 **) 1956 let rec subaddressing_mode_rect_Type1 n l h_mk_subaddressing_mode x_ 22862=1957 let subaddressing_modeel = x_ 22862in1956 let rec subaddressing_mode_rect_Type1 n l h_mk_subaddressing_mode x_674 = 1957 let subaddressing_modeel = x_674 in 1958 1958 h_mk_subaddressing_mode subaddressing_modeel __ 1959 1959 … … 1961 1961 Nat.nat > addressing_mode_tag Vector.vector > (addressing_mode > __ > 1962 1962 'a1) > subaddressing_mode > 'a1 **) 1963 let rec subaddressing_mode_rect_Type0 n l h_mk_subaddressing_mode x_ 22864=1964 let subaddressing_modeel = x_ 22864in1963 let rec subaddressing_mode_rect_Type0 n l h_mk_subaddressing_mode x_676 = 1964 let subaddressing_modeel = x_676 in 1965 1965 h_mk_subaddressing_mode subaddressing_modeel __ 1966 1966 … … 2288 2288 'a2 > 'a2 > (subaddressing_mode > 'a2) > 'a1 preinstruction > 'a2 **) 2289 2289 let rec preinstruction_rect_Type4 h_ADD h_ADDC h_SUBB h_INC h_DEC h_MUL h_DIV h_DA h_JC h_JNC h_JB h_JNB h_JBC h_JZ h_JNZ h_CJNE h_DJNZ h_ANL h_ORL h_XRL h_CLR h_CPL h_RL h_RLC h_RR h_RRC h_SWAP h_MOV h_MOVX h_SETB h_PUSH h_POP h_XCH h_XCHD h_RET h_RETI h_NOP h_JMP = function 2290  ADD (x_ 22966, x_22965) > h_ADD x_22966 x_229652291  ADDC (x_ 22968, x_22967) > h_ADDC x_22968 x_229672292  SUBB (x_ 22970, x_22969) > h_SUBB x_22970 x_229692293  INC x_ 22971 > h_INC x_229712294  DEC x_ 22972 > h_DEC x_229722295  MUL (x_ 22974, x_22973) > h_MUL x_22974 x_229732296  DIV (x_ 22976, x_22975) > h_DIV x_22976 x_229752297  DA x_ 22977 > h_DA x_229772298  JC x_ 22978 > h_JC x_229782299  JNC x_ 22979 > h_JNC x_229792300  JB (x_ 22981, x_22980) > h_JB x_22981 x_229802301  JNB (x_ 22983, x_22982) > h_JNB x_22983 x_229822302  JBC (x_ 22985, x_22984) > h_JBC x_22985 x_229842303  JZ x_ 22986 > h_JZ x_229862304  JNZ x_ 22987 > h_JNZ x_229872305  CJNE (x_ 22989, x_22988) > h_CJNE x_22989 x_229882306  DJNZ (x_ 22991, x_22990) > h_DJNZ x_22991 x_229902307  ANL x_ 22992 > h_ANL x_229922308  ORL x_ 22993 > h_ORL x_229932309  XRL x_ 22994 > h_XRL x_229942310  CLR x_ 22995 > h_CLR x_229952311  CPL x_ 22996 > h_CPL x_229962312  RL x_ 22997 > h_RL x_229972313  RLC x_ 22998 > h_RLC x_229982314  RR x_ 22999 > h_RR x_229992315  RRC x_ 23000 > h_RRC x_230002316  SWAP x_ 23001 > h_SWAP x_230012317  MOV x_ 23002 > h_MOV x_230022318  MOVX x_ 23003 > h_MOVX x_230032319  SETB x_ 23004 > h_SETB x_230042320  PUSH x_ 23005 > h_PUSH x_230052321  POP x_ 23006 > h_POP x_230062322  XCH (x_ 23008, x_23007) > h_XCH x_23008 x_230072323  XCHD (x_ 23010, x_23009) > h_XCHD x_23010 x_230092290  ADD (x_778, x_777) > h_ADD x_778 x_777 2291  ADDC (x_780, x_779) > h_ADDC x_780 x_779 2292  SUBB (x_782, x_781) > h_SUBB x_782 x_781 2293  INC x_783 > h_INC x_783 2294  DEC x_784 > h_DEC x_784 2295  MUL (x_786, x_785) > h_MUL x_786 x_785 2296  DIV (x_788, x_787) > h_DIV x_788 x_787 2297  DA x_789 > h_DA x_789 2298  JC x_790 > h_JC x_790 2299  JNC x_791 > h_JNC x_791 2300  JB (x_793, x_792) > h_JB x_793 x_792 2301  JNB (x_795, x_794) > h_JNB x_795 x_794 2302  JBC (x_797, x_796) > h_JBC x_797 x_796 2303  JZ x_798 > h_JZ x_798 2304  JNZ x_799 > h_JNZ x_799 2305  CJNE (x_801, x_800) > h_CJNE x_801 x_800 2306  DJNZ (x_803, x_802) > h_DJNZ x_803 x_802 2307  ANL x_804 > h_ANL x_804 2308  ORL x_805 > h_ORL x_805 2309  XRL x_806 > h_XRL x_806 2310  CLR x_807 > h_CLR x_807 2311  CPL x_808 > h_CPL x_808 2312  RL x_809 > h_RL x_809 2313  RLC x_810 > h_RLC x_810 2314  RR x_811 > h_RR x_811 2315  RRC x_812 > h_RRC x_812 2316  SWAP x_813 > h_SWAP x_813 2317  MOV x_814 > h_MOV x_814 2318  MOVX x_815 > h_MOVX x_815 2319  SETB x_816 > h_SETB x_816 2320  PUSH x_817 > h_PUSH x_817 2321  POP x_818 > h_POP x_818 2322  XCH (x_820, x_819) > h_XCH x_820 x_819 2323  XCHD (x_822, x_821) > h_XCHD x_822 x_821 2324 2324  RET > h_RET 2325 2325  RETI > h_RETI 2326 2326  NOP > h_NOP 2327  JMP x_ 23011 > h_JMP x_230112327  JMP x_823 > h_JMP x_823 2328 2328 2329 2329 (** val preinstruction_rect_Type5 : … … 2363 2363 'a2 > 'a2 > (subaddressing_mode > 'a2) > 'a1 preinstruction > 'a2 **) 2364 2364 let rec preinstruction_rect_Type5 h_ADD h_ADDC h_SUBB h_INC h_DEC h_MUL h_DIV h_DA h_JC h_JNC h_JB h_JNB h_JBC h_JZ h_JNZ h_CJNE h_DJNZ h_ANL h_ORL h_XRL h_CLR h_CPL h_RL h_RLC h_RR h_RRC h_SWAP h_MOV h_MOVX h_SETB h_PUSH h_POP h_XCH h_XCHD h_RET h_RETI h_NOP h_JMP = function 2365  ADD (x_ 23052, x_23051) > h_ADD x_23052 x_230512366  ADDC (x_ 23054, x_23053) > h_ADDC x_23054 x_230532367  SUBB (x_ 23056, x_23055) > h_SUBB x_23056 x_230552368  INC x_ 23057 > h_INC x_230572369  DEC x_ 23058 > h_DEC x_230582370  MUL (x_ 23060, x_23059) > h_MUL x_23060 x_230592371  DIV (x_ 23062, x_23061) > h_DIV x_23062 x_230612372  DA x_ 23063 > h_DA x_230632373  JC x_ 23064 > h_JC x_230642374  JNC x_ 23065 > h_JNC x_230652375  JB (x_ 23067, x_23066) > h_JB x_23067 x_230662376  JNB (x_ 23069, x_23068) > h_JNB x_23069 x_230682377  JBC (x_ 23071, x_23070) > h_JBC x_23071 x_230702378  JZ x_ 23072 > h_JZ x_230722379  JNZ x_ 23073 > h_JNZ x_230732380  CJNE (x_ 23075, x_23074) > h_CJNE x_23075 x_230742381  DJNZ (x_ 23077, x_23076) > h_DJNZ x_23077 x_230762382  ANL x_ 23078 > h_ANL x_230782383  ORL x_ 23079 > h_ORL x_230792384  XRL x_ 23080 > h_XRL x_230802385  CLR x_ 23081 > h_CLR x_230812386  CPL x_ 23082 > h_CPL x_230822387  RL x_ 23083 > h_RL x_230832388  RLC x_ 23084 > h_RLC x_230842389  RR x_ 23085 > h_RR x_230852390  RRC x_ 23086 > h_RRC x_230862391  SWAP x_ 23087 > h_SWAP x_230872392  MOV x_ 23088 > h_MOV x_230882393  MOVX x_ 23089 > h_MOVX x_230892394  SETB x_ 23090 > h_SETB x_230902395  PUSH x_ 23091 > h_PUSH x_230912396  POP x_ 23092 > h_POP x_230922397  XCH (x_ 23094, x_23093) > h_XCH x_23094 x_230932398  XCHD (x_ 23096, x_23095) > h_XCHD x_23096 x_230952365  ADD (x_864, x_863) > h_ADD x_864 x_863 2366  ADDC (x_866, x_865) > h_ADDC x_866 x_865 2367  SUBB (x_868, x_867) > h_SUBB x_868 x_867 2368  INC x_869 > h_INC x_869 2369  DEC x_870 > h_DEC x_870 2370  MUL (x_872, x_871) > h_MUL x_872 x_871 2371  DIV (x_874, x_873) > h_DIV x_874 x_873 2372  DA x_875 > h_DA x_875 2373  JC x_876 > h_JC x_876 2374  JNC x_877 > h_JNC x_877 2375  JB (x_879, x_878) > h_JB x_879 x_878 2376  JNB (x_881, x_880) > h_JNB x_881 x_880 2377  JBC (x_883, x_882) > h_JBC x_883 x_882 2378  JZ x_884 > h_JZ x_884 2379  JNZ x_885 > h_JNZ x_885 2380  CJNE (x_887, x_886) > h_CJNE x_887 x_886 2381  DJNZ (x_889, x_888) > h_DJNZ x_889 x_888 2382  ANL x_890 > h_ANL x_890 2383  ORL x_891 > h_ORL x_891 2384  XRL x_892 > h_XRL x_892 2385  CLR x_893 > h_CLR x_893 2386  CPL x_894 > h_CPL x_894 2387  RL x_895 > h_RL x_895 2388  RLC x_896 > h_RLC x_896 2389  RR x_897 > h_RR x_897 2390  RRC x_898 > h_RRC x_898 2391  SWAP x_899 > h_SWAP x_899 2392  MOV x_900 > h_MOV x_900 2393  MOVX x_901 > h_MOVX x_901 2394  SETB x_902 > h_SETB x_902 2395  PUSH x_903 > h_PUSH x_903 2396  POP x_904 > h_POP x_904 2397  XCH (x_906, x_905) > h_XCH x_906 x_905 2398  XCHD (x_908, x_907) > h_XCHD x_908 x_907 2399 2399  RET > h_RET 2400 2400  RETI > h_RETI 2401 2401  NOP > h_NOP 2402  JMP x_ 23097 > h_JMP x_230972402  JMP x_909 > h_JMP x_909 2403 2403 2404 2404 (** val preinstruction_rect_Type3 : … … 2438 2438 'a2 > 'a2 > (subaddressing_mode > 'a2) > 'a1 preinstruction > 'a2 **) 2439 2439 let rec preinstruction_rect_Type3 h_ADD h_ADDC h_SUBB h_INC h_DEC h_MUL h_DIV h_DA h_JC h_JNC h_JB h_JNB h_JBC h_JZ h_JNZ h_CJNE h_DJNZ h_ANL h_ORL h_XRL h_CLR h_CPL h_RL h_RLC h_RR h_RRC h_SWAP h_MOV h_MOVX h_SETB h_PUSH h_POP h_XCH h_XCHD h_RET h_RETI h_NOP h_JMP = function 2440  ADD (x_ 23138, x_23137) > h_ADD x_23138 x_231372441  ADDC (x_ 23140, x_23139) > h_ADDC x_23140 x_231392442  SUBB (x_ 23142, x_23141) > h_SUBB x_23142 x_231412443  INC x_ 23143 > h_INC x_231432444  DEC x_ 23144 > h_DEC x_231442445  MUL (x_ 23146, x_23145) > h_MUL x_23146 x_231452446  DIV (x_ 23148, x_23147) > h_DIV x_23148 x_231472447  DA x_ 23149 > h_DA x_231492448  JC x_ 23150 > h_JC x_231502449  JNC x_ 23151 > h_JNC x_231512450  JB (x_ 23153, x_23152) > h_JB x_23153 x_231522451  JNB (x_ 23155, x_23154) > h_JNB x_23155 x_231542452  JBC (x_ 23157, x_23156) > h_JBC x_23157 x_231562453  JZ x_ 23158 > h_JZ x_231582454  JNZ x_ 23159 > h_JNZ x_231592455  CJNE (x_ 23161, x_23160) > h_CJNE x_23161 x_231602456  DJNZ (x_ 23163, x_23162) > h_DJNZ x_23163 x_231622457  ANL x_ 23164 > h_ANL x_231642458  ORL x_ 23165 > h_ORL x_231652459  XRL x_ 23166 > h_XRL x_231662460  CLR x_ 23167 > h_CLR x_231672461  CPL x_ 23168 > h_CPL x_231682462  RL x_ 23169 > h_RL x_231692463  RLC x_ 23170 > h_RLC x_231702464  RR x_ 23171 > h_RR x_231712465  RRC x_ 23172 > h_RRC x_231722466  SWAP x_ 23173 > h_SWAP x_231732467  MOV x_ 23174 > h_MOV x_231742468  MOVX x_ 23175 > h_MOVX x_231752469  SETB x_ 23176 > h_SETB x_231762470  PUSH x_ 23177 > h_PUSH x_231772471  POP x_ 23178 > h_POP x_231782472  XCH (x_ 23180, x_23179) > h_XCH x_23180 x_231792473  XCHD (x_ 23182, x_23181) > h_XCHD x_23182 x_231812440  ADD (x_950, x_949) > h_ADD x_950 x_949 2441  ADDC (x_952, x_951) > h_ADDC x_952 x_951 2442  SUBB (x_954, x_953) > h_SUBB x_954 x_953 2443  INC x_955 > h_INC x_955 2444  DEC x_956 > h_DEC x_956 2445  MUL (x_958, x_957) > h_MUL x_958 x_957 2446  DIV (x_960, x_959) > h_DIV x_960 x_959 2447  DA x_961 > h_DA x_961 2448  JC x_962 > h_JC x_962 2449  JNC x_963 > h_JNC x_963 2450  JB (x_965, x_964) > h_JB x_965 x_964 2451  JNB (x_967, x_966) > h_JNB x_967 x_966 2452  JBC (x_969, x_968) > h_JBC x_969 x_968 2453  JZ x_970 > h_JZ x_970 2454  JNZ x_971 > h_JNZ x_971 2455  CJNE (x_973, x_972) > h_CJNE x_973 x_972 2456  DJNZ (x_975, x_974) > h_DJNZ x_975 x_974 2457  ANL x_976 > h_ANL x_976 2458  ORL x_977 > h_ORL x_977 2459  XRL x_978 > h_XRL x_978 2460  CLR x_979 > h_CLR x_979 2461  CPL x_980 > h_CPL x_980 2462  RL x_981 > h_RL x_981 2463  RLC x_982 > h_RLC x_982 2464  RR x_983 > h_RR x_983 2465  RRC x_984 > h_RRC x_984 2466  SWAP x_985 > h_SWAP x_985 2467  MOV x_986 > h_MOV x_986 2468  MOVX x_987 > h_MOVX x_987 2469  SETB x_988 > h_SETB x_988 2470  PUSH x_989 > h_PUSH x_989 2471  POP x_990 > h_POP x_990 2472  XCH (x_992, x_991) > h_XCH x_992 x_991 2473  XCHD (x_994, x_993) > h_XCHD x_994 x_993 2474 2474  RET > h_RET 2475 2475  RETI > h_RETI 2476 2476  NOP > h_NOP 2477  JMP x_ 23183 > h_JMP x_231832477  JMP x_995 > h_JMP x_995 2478 2478 2479 2479 (** val preinstruction_rect_Type2 : … … 2513 2513 'a2 > 'a2 > (subaddressing_mode > 'a2) > 'a1 preinstruction > 'a2 **) 2514 2514 let rec preinstruction_rect_Type2 h_ADD h_ADDC h_SUBB h_INC h_DEC h_MUL h_DIV h_DA h_JC h_JNC h_JB h_JNB h_JBC h_JZ h_JNZ h_CJNE h_DJNZ h_ANL h_ORL h_XRL h_CLR h_CPL h_RL h_RLC h_RR h_RRC h_SWAP h_MOV h_MOVX h_SETB h_PUSH h_POP h_XCH h_XCHD h_RET h_RETI h_NOP h_JMP = function 2515  ADD (x_ 23224, x_23223) > h_ADD x_23224 x_232232516  ADDC (x_ 23226, x_23225) > h_ADDC x_23226 x_232252517  SUBB (x_ 23228, x_23227) > h_SUBB x_23228 x_232272518  INC x_ 23229 > h_INC x_232292519  DEC x_ 23230 > h_DEC x_232302520  MUL (x_ 23232, x_23231) > h_MUL x_23232 x_232312521  DIV (x_ 23234, x_23233) > h_DIV x_23234 x_232332522  DA x_ 23235 > h_DA x_232352523  JC x_ 23236 > h_JC x_232362524  JNC x_ 23237 > h_JNC x_232372525  JB (x_ 23239, x_23238) > h_JB x_23239 x_232382526  JNB (x_ 23241, x_23240) > h_JNB x_23241 x_232402527  JBC (x_ 23243, x_23242) > h_JBC x_23243 x_232422528  JZ x_ 23244 > h_JZ x_232442529  JNZ x_ 23245 > h_JNZ x_232452530  CJNE (x_ 23247, x_23246) > h_CJNE x_23247 x_232462531  DJNZ (x_ 23249, x_23248) > h_DJNZ x_23249 x_232482532  ANL x_ 23250 > h_ANL x_232502533  ORL x_ 23251 > h_ORL x_232512534  XRL x_ 23252 > h_XRL x_232522535  CLR x_ 23253 > h_CLR x_232532536  CPL x_ 23254 > h_CPL x_232542537  RL x_ 23255 > h_RL x_232552538  RLC x_ 23256 > h_RLC x_232562539  RR x_ 23257 > h_RR x_232572540  RRC x_ 23258 > h_RRC x_232582541  SWAP x_ 23259 > h_SWAP x_232592542  MOV x_ 23260 > h_MOV x_232602543  MOVX x_ 23261 > h_MOVX x_232612544  SETB x_ 23262 > h_SETB x_232622545  PUSH x_ 23263 > h_PUSH x_232632546  POP x_ 23264 > h_POP x_232642547  XCH (x_ 23266, x_23265) > h_XCH x_23266 x_232652548  XCHD (x_ 23268, x_23267) > h_XCHD x_23268 x_232672515  ADD (x_1036, x_1035) > h_ADD x_1036 x_1035 2516  ADDC (x_1038, x_1037) > h_ADDC x_1038 x_1037 2517  SUBB (x_1040, x_1039) > h_SUBB x_1040 x_1039 2518  INC x_1041 > h_INC x_1041 2519  DEC x_1042 > h_DEC x_1042 2520  MUL (x_1044, x_1043) > h_MUL x_1044 x_1043 2521  DIV (x_1046, x_1045) > h_DIV x_1046 x_1045 2522  DA x_1047 > h_DA x_1047 2523  JC x_1048 > h_JC x_1048 2524  JNC x_1049 > h_JNC x_1049 2525  JB (x_1051, x_1050) > h_JB x_1051 x_1050 2526  JNB (x_1053, x_1052) > h_JNB x_1053 x_1052 2527  JBC (x_1055, x_1054) > h_JBC x_1055 x_1054 2528  JZ x_1056 > h_JZ x_1056 2529  JNZ x_1057 > h_JNZ x_1057 2530  CJNE (x_1059, x_1058) > h_CJNE x_1059 x_1058 2531  DJNZ (x_1061, x_1060) > h_DJNZ x_1061 x_1060 2532  ANL x_1062 > h_ANL x_1062 2533  ORL x_1063 > h_ORL x_1063 2534  XRL x_1064 > h_XRL x_1064 2535  CLR x_1065 > h_CLR x_1065 2536  CPL x_1066 > h_CPL x_1066 2537  RL x_1067 > h_RL x_1067 2538  RLC x_1068 > h_RLC x_1068 2539  RR x_1069 > h_RR x_1069 2540  RRC x_1070 > h_RRC x_1070 2541  SWAP x_1071 > h_SWAP x_1071 2542  MOV x_1072 > h_MOV x_1072 2543  MOVX x_1073 > h_MOVX x_1073 2544  SETB x_1074 > h_SETB x_1074 2545  PUSH x_1075 > h_PUSH x_1075 2546  POP x_1076 > h_POP x_1076 2547  XCH (x_1078, x_1077) > h_XCH x_1078 x_1077 2548  XCHD (x_1080, x_1079) > h_XCHD x_1080 x_1079 2549 2549  RET > h_RET 2550 2550  RETI > h_RETI 2551 2551  NOP > h_NOP 2552  JMP x_ 23269 > h_JMP x_232692552  JMP x_1081 > h_JMP x_1081 2553 2553 2554 2554 (** val preinstruction_rect_Type1 : … … 2588 2588 'a2 > 'a2 > (subaddressing_mode > 'a2) > 'a1 preinstruction > 'a2 **) 2589 2589 let rec preinstruction_rect_Type1 h_ADD h_ADDC h_SUBB h_INC h_DEC h_MUL h_DIV h_DA h_JC h_JNC h_JB h_JNB h_JBC h_JZ h_JNZ h_CJNE h_DJNZ h_ANL h_ORL h_XRL h_CLR h_CPL h_RL h_RLC h_RR h_RRC h_SWAP h_MOV h_MOVX h_SETB h_PUSH h_POP h_XCH h_XCHD h_RET h_RETI h_NOP h_JMP = function 2590  ADD (x_ 23310, x_23309) > h_ADD x_23310 x_233092591  ADDC (x_ 23312, x_23311) > h_ADDC x_23312 x_233112592  SUBB (x_ 23314, x_23313) > h_SUBB x_23314 x_233132593  INC x_ 23315 > h_INC x_233152594  DEC x_ 23316 > h_DEC x_233162595  MUL (x_ 23318, x_23317) > h_MUL x_23318 x_233172596  DIV (x_ 23320, x_23319) > h_DIV x_23320 x_233192597  DA x_ 23321 > h_DA x_233212598  JC x_ 23322 > h_JC x_233222599  JNC x_ 23323 > h_JNC x_233232600  JB (x_ 23325, x_23324) > h_JB x_23325 x_233242601  JNB (x_ 23327, x_23326) > h_JNB x_23327 x_233262602  JBC (x_ 23329, x_23328) > h_JBC x_23329 x_233282603  JZ x_ 23330 > h_JZ x_233302604  JNZ x_ 23331 > h_JNZ x_233312605  CJNE (x_ 23333, x_23332) > h_CJNE x_23333 x_233322606  DJNZ (x_ 23335, x_23334) > h_DJNZ x_23335 x_233342607  ANL x_ 23336 > h_ANL x_233362608  ORL x_ 23337 > h_ORL x_233372609  XRL x_ 23338 > h_XRL x_233382610  CLR x_ 23339 > h_CLR x_233392611  CPL x_ 23340 > h_CPL x_233402612  RL x_ 23341 > h_RL x_233412613  RLC x_ 23342 > h_RLC x_233422614  RR x_ 23343 > h_RR x_233432615  RRC x_ 23344 > h_RRC x_233442616  SWAP x_ 23345 > h_SWAP x_233452617  MOV x_ 23346 > h_MOV x_233462618  MOVX x_ 23347 > h_MOVX x_233472619  SETB x_ 23348 > h_SETB x_233482620  PUSH x_ 23349 > h_PUSH x_233492621  POP x_ 23350 > h_POP x_233502622  XCH (x_ 23352, x_23351) > h_XCH x_23352 x_233512623  XCHD (x_ 23354, x_23353) > h_XCHD x_23354 x_233532590  ADD (x_1122, x_1121) > h_ADD x_1122 x_1121 2591  ADDC (x_1124, x_1123) > h_ADDC x_1124 x_1123 2592  SUBB (x_1126, x_1125) > h_SUBB x_1126 x_1125 2593  INC x_1127 > h_INC x_1127 2594  DEC x_1128 > h_DEC x_1128 2595  MUL (x_1130, x_1129) > h_MUL x_1130 x_1129 2596  DIV (x_1132, x_1131) > h_DIV x_1132 x_1131 2597  DA x_1133 > h_DA x_1133 2598  JC x_1134 > h_JC x_1134 2599  JNC x_1135 > h_JNC x_1135 2600  JB (x_1137, x_1136) > h_JB x_1137 x_1136 2601  JNB (x_1139, x_1138) > h_JNB x_1139 x_1138 2602  JBC (x_1141, x_1140) > h_JBC x_1141 x_1140 2603  JZ x_1142 > h_JZ x_1142 2604  JNZ x_1143 > h_JNZ x_1143 2605  CJNE (x_1145, x_1144) > h_CJNE x_1145 x_1144 2606  DJNZ (x_1147, x_1146) > h_DJNZ x_1147 x_1146 2607  ANL x_1148 > h_ANL x_1148 2608  ORL x_1149 > h_ORL x_1149 2609  XRL x_1150 > h_XRL x_1150 2610  CLR x_1151 > h_CLR x_1151 2611  CPL x_1152 > h_CPL x_1152 2612  RL x_1153 > h_RL x_1153 2613  RLC x_1154 > h_RLC x_1154 2614  RR x_1155 > h_RR x_1155 2615  RRC x_1156 > h_RRC x_1156 2616  SWAP x_1157 > h_SWAP x_1157 2617  MOV x_1158 > h_MOV x_1158 2618  MOVX x_1159 > h_MOVX x_1159 2619  SETB x_1160 > h_SETB x_1160 2620  PUSH x_1161 > h_PUSH x_1161 2621  POP x_1162 > h_POP x_1162 2622  XCH (x_1164, x_1163) > h_XCH x_1164 x_1163 2623  XCHD (x_1166, x_1165) > h_XCHD x_1166 x_1165 2624 2624  RET > h_RET 2625 2625  RETI > h_RETI 2626 2626  NOP > h_NOP 2627  JMP x_ 23355 > h_JMP x_233552627  JMP x_1167 > h_JMP x_1167 2628 2628 2629 2629 (** val preinstruction_rect_Type0 : … … 2663 2663 'a2 > 'a2 > (subaddressing_mode > 'a2) > 'a1 preinstruction > 'a2 **) 2664 2664 let rec preinstruction_rect_Type0 h_ADD h_ADDC h_SUBB h_INC h_DEC h_MUL h_DIV h_DA h_JC h_JNC h_JB h_JNB h_JBC h_JZ h_JNZ h_CJNE h_DJNZ h_ANL h_ORL h_XRL h_CLR h_CPL h_RL h_RLC h_RR h_RRC h_SWAP h_MOV h_MOVX h_SETB h_PUSH h_POP h_XCH h_XCHD h_RET h_RETI h_NOP h_JMP = function 2665  ADD (x_ 23396, x_23395) > h_ADD x_23396 x_233952666  ADDC (x_ 23398, x_23397) > h_ADDC x_23398 x_233972667  SUBB (x_ 23400, x_23399) > h_SUBB x_23400 x_233992668  INC x_ 23401 > h_INC x_234012669  DEC x_ 23402 > h_DEC x_234022670  MUL (x_ 23404, x_23403) > h_MUL x_23404 x_234032671  DIV (x_ 23406, x_23405) > h_DIV x_23406 x_234052672  DA x_ 23407 > h_DA x_234072673  JC x_ 23408 > h_JC x_234082674  JNC x_ 23409 > h_JNC x_234092675  JB (x_ 23411, x_23410) > h_JB x_23411 x_234102676  JNB (x_ 23413, x_23412) > h_JNB x_23413 x_234122677  JBC (x_ 23415, x_23414) > h_JBC x_23415 x_234142678  JZ x_ 23416 > h_JZ x_234162679  JNZ x_ 23417 > h_JNZ x_234172680  CJNE (x_ 23419, x_23418) > h_CJNE x_23419 x_234182681  DJNZ (x_ 23421, x_23420) > h_DJNZ x_23421 x_234202682  ANL x_ 23422 > h_ANL x_234222683  ORL x_ 23423 > h_ORL x_234232684  XRL x_ 23424 > h_XRL x_234242685  CLR x_ 23425 > h_CLR x_234252686  CPL x_ 23426 > h_CPL x_234262687  RL x_ 23427 > h_RL x_234272688  RLC x_ 23428 > h_RLC x_234282689  RR x_ 23429 > h_RR x_234292690  RRC x_ 23430 > h_RRC x_234302691  SWAP x_ 23431 > h_SWAP x_234312692  MOV x_ 23432 > h_MOV x_234322693  MOVX x_ 23433 > h_MOVX x_234332694  SETB x_ 23434 > h_SETB x_234342695  PUSH x_ 23435 > h_PUSH x_234352696  POP x_ 23436 > h_POP x_234362697  XCH (x_ 23438, x_23437) > h_XCH x_23438 x_234372698  XCHD (x_ 23440, x_23439) > h_XCHD x_23440 x_234392665  ADD (x_1208, x_1207) > h_ADD x_1208 x_1207 2666  ADDC (x_1210, x_1209) > h_ADDC x_1210 x_1209 2667  SUBB (x_1212, x_1211) > h_SUBB x_1212 x_1211 2668  INC x_1213 > h_INC x_1213 2669  DEC x_1214 > h_DEC x_1214 2670  MUL (x_1216, x_1215) > h_MUL x_1216 x_1215 2671  DIV (x_1218, x_1217) > h_DIV x_1218 x_1217 2672  DA x_1219 > h_DA x_1219 2673  JC x_1220 > h_JC x_1220 2674  JNC x_1221 > h_JNC x_1221 2675  JB (x_1223, x_1222) > h_JB x_1223 x_1222 2676  JNB (x_1225, x_1224) > h_JNB x_1225 x_1224 2677  JBC (x_1227, x_1226) > h_JBC x_1227 x_1226 2678  JZ x_1228 > h_JZ x_1228 2679  JNZ x_1229 > h_JNZ x_1229 2680  CJNE (x_1231, x_1230) > h_CJNE x_1231 x_1230 2681  DJNZ (x_1233, x_1232) > h_DJNZ x_1233 x_1232 2682  ANL x_1234 > h_ANL x_1234 2683  ORL x_1235 > h_ORL x_1235 2684  XRL x_1236 > h_XRL x_1236 2685  CLR x_1237 > h_CLR x_1237 2686  CPL x_1238 > h_CPL x_1238 2687  RL x_1239 > h_RL x_1239 2688  RLC x_1240 > h_RLC x_1240 2689  RR x_1241 > h_RR x_1241 2690  RRC x_1242 > h_RRC x_1242 2691  SWAP x_1243 > h_SWAP x_1243 2692  MOV x_1244 > h_MOV x_1244 2693  MOVX x_1245 > h_MOVX x_1245 2694  SETB x_1246 > h_SETB x_1246 2695  PUSH x_1247 > h_PUSH x_1247 2696  POP x_1248 > h_POP x_1248 2697  XCH (x_1250, x_1249) > h_XCH x_1250 x_1249 2698  XCHD (x_1252, x_1251) > h_XCHD x_1252 x_1251 2699 2699  RET > h_RET 2700 2700  RETI > h_RETI 2701 2701  NOP > h_NOP 2702  JMP x_ 23441 > h_JMP x_234412702  JMP x_1253 > h_JMP x_1253 2703 2703 2704 2704 (** val preinstruction_inv_rect_Type4 : … … 5104 5104 'a1 **) 5105 5105 let rec instruction_rect_Type4 h_ACALL h_LCALL h_AJMP h_LJMP h_SJMP h_MOVC h_RealInstruction = function 5106  ACALL x_ 24013 > h_ACALL x_240135107  LCALL x_ 24014 > h_LCALL x_240145108  AJMP x_ 24015 > h_AJMP x_240155109  LJMP x_ 24016 > h_LJMP x_240165110  SJMP x_ 24017 > h_SJMP x_240175111  MOVC (x_ 24019, x_24018) > h_MOVC x_24019 x_240185112  RealInstruction x_ 24020 > h_RealInstruction x_240205106  ACALL x_1825 > h_ACALL x_1825 5107  LCALL x_1826 > h_LCALL x_1826 5108  AJMP x_1827 > h_AJMP x_1827 5109  LJMP x_1828 > h_LJMP x_1828 5110  SJMP x_1829 > h_SJMP x_1829 5111  MOVC (x_1831, x_1830) > h_MOVC x_1831 x_1830 5112  RealInstruction x_1832 > h_RealInstruction x_1832 5113 5113 5114 5114 (** val instruction_rect_Type5 : … … 5119 5119 'a1 **) 5120 5120 let rec instruction_rect_Type5 h_ACALL h_LCALL h_AJMP h_LJMP h_SJMP h_MOVC h_RealInstruction = function 5121  ACALL x_ 24029 > h_ACALL x_240295122  LCALL x_ 24030 > h_LCALL x_240305123  AJMP x_ 24031 > h_AJMP x_240315124  LJMP x_ 24032 > h_LJMP x_240325125  SJMP x_ 24033 > h_SJMP x_240335126  MOVC (x_ 24035, x_24034) > h_MOVC x_24035 x_240345127  RealInstruction x_ 24036 > h_RealInstruction x_240365121  ACALL x_1841 > h_ACALL x_1841 5122  LCALL x_1842 > h_LCALL x_1842 5123  AJMP x_1843 > h_AJMP x_1843 5124  LJMP x_1844 > h_LJMP x_1844 5125  SJMP x_1845 > h_SJMP x_1845 5126  MOVC (x_1847, x_1846) > h_MOVC x_1847 x_1846 5127  RealInstruction x_1848 > h_RealInstruction x_1848 5128 5128 5129 5129 (** val instruction_rect_Type3 : … … 5134 5134 'a1 **) 5135 5135 let rec instruction_rect_Type3 h_ACALL h_LCALL h_AJMP h_LJMP h_SJMP h_MOVC h_RealInstruction = function 5136  ACALL x_ 24045 > h_ACALL x_240455137  LCALL x_ 24046 > h_LCALL x_240465138  AJMP x_ 24047 > h_AJMP x_240475139  LJMP x_ 24048 > h_LJMP x_240485140  SJMP x_ 24049 > h_SJMP x_240495141  MOVC (x_ 24051, x_24050) > h_MOVC x_24051 x_240505142  RealInstruction x_ 24052 > h_RealInstruction x_240525136  ACALL x_1857 > h_ACALL x_1857 5137  LCALL x_1858 > h_LCALL x_1858 5138  AJMP x_1859 > h_AJMP x_1859 5139  LJMP x_1860 > h_LJMP x_1860 5140  SJMP x_1861 > h_SJMP x_1861 5141  MOVC (x_1863, x_1862) > h_MOVC x_1863 x_1862 5142  RealInstruction x_1864 > h_RealInstruction x_1864 5143 5143 5144 5144 (** val instruction_rect_Type2 : … … 5149 5149 'a1 **) 5150 5150 let rec instruction_rect_Type2 h_ACALL h_LCALL h_AJMP h_LJMP h_SJMP h_MOVC h_RealInstruction = function 5151  ACALL x_ 24061 > h_ACALL x_240615152  LCALL x_ 24062 > h_LCALL x_240625153  AJMP x_ 24063 > h_AJMP x_240635154  LJMP x_ 24064 > h_LJMP x_240645155  SJMP x_ 24065 > h_SJMP x_240655156  MOVC (x_ 24067, x_24066) > h_MOVC x_24067 x_240665157  RealInstruction x_ 24068 > h_RealInstruction x_240685151  ACALL x_1873 > h_ACALL x_1873 5152  LCALL x_1874 > h_LCALL x_1874 5153  AJMP x_1875 > h_AJMP x_1875 5154  LJMP x_1876 > h_LJMP x_1876 5155  SJMP x_1877 > h_SJMP x_1877 5156  MOVC (x_1879, x_1878) > h_MOVC x_1879 x_1878 5157  RealInstruction x_1880 > h_RealInstruction x_1880 5158 5158 5159 5159 (** val instruction_rect_Type1 : … … 5164 5164 'a1 **) 5165 5165 let rec instruction_rect_Type1 h_ACALL h_LCALL h_AJMP h_LJMP h_SJMP h_MOVC h_RealInstruction = function 5166  ACALL x_ 24077 > h_ACALL x_240775167  LCALL x_ 24078 > h_LCALL x_240785168  AJMP x_ 24079 > h_AJMP x_240795169  LJMP x_ 24080 > h_LJMP x_240805170  SJMP x_ 24081 > h_SJMP x_240815171  MOVC (x_ 24083, x_24082) > h_MOVC x_24083 x_240825172  RealInstruction x_ 24084 > h_RealInstruction x_240845166  ACALL x_1889 > h_ACALL x_1889 5167  LCALL x_1890 > h_LCALL x_1890 5168  AJMP x_1891 > h_AJMP x_1891 5169  LJMP x_1892 > h_LJMP x_1892 5170  SJMP x_1893 > h_SJMP x_1893 5171  MOVC (x_1895, x_1894) > h_MOVC x_1895 x_1894 5172  RealInstruction x_1896 > h_RealInstruction x_1896 5173 5173 5174 5174 (** val instruction_rect_Type0 : … … 5179 5179 'a1 **) 5180 5180 let rec instruction_rect_Type0 h_ACALL h_LCALL h_AJMP h_LJMP h_SJMP h_MOVC h_RealInstruction = function 5181  ACALL x_ 24093 > h_ACALL x_240935182  LCALL x_ 24094 > h_LCALL x_240945183  AJMP x_ 24095 > h_AJMP x_240955184  LJMP x_ 24096 > h_LJMP x_240965185  SJMP x_ 24097 > h_SJMP x_240975186  MOVC (x_ 24099, x_24098) > h_MOVC x_24099 x_240985187  RealInstruction x_ 24100 > h_RealInstruction x_241005181  ACALL x_1905 > h_ACALL x_1905 5182  LCALL x_1906 > h_LCALL x_1906 5183  AJMP x_1907 > h_AJMP x_1907 5184  LJMP x_1908 > h_LJMP x_1908 5185  SJMP x_1909 > h_SJMP x_1909 5186  MOVC (x_1911, x_1910) > h_MOVC x_1911 x_1910 5187  RealInstruction x_1912 > h_RealInstruction x_1912 5188 5188 5189 5189 (** val instruction_inv_rect_Type4 : … … 5476 5476 > 'a1 **) 5477 5477 let rec pseudo_instruction_rect_Type4 h_Instruction h_Comment h_Cost h_Jmp h_Jnz h_MovSuccessor h_Call h_Mov = function 5478  Instruction x_2 4266 > h_Instruction x_242665479  Comment x_2 4267 > h_Comment x_242675480  Cost x_2 4268 > h_Cost x_242685481  Jmp x_2 4269 > h_Jmp x_242695482  Jnz (x_2 4272, x_24271, x_24270) > h_Jnz x_24272 x_24271 x_242705483  MovSuccessor (x_2 4275, x_24274, x_24273) >5484 h_MovSuccessor x_2 4275 x_24274 x_242735485  Call x_2 4276 > h_Call x_242765486  Mov (x_2 4278, x_24277) > h_Mov x_24278 x_242775478  Instruction x_2078 > h_Instruction x_2078 5479  Comment x_2079 > h_Comment x_2079 5480  Cost x_2080 > h_Cost x_2080 5481  Jmp x_2081 > h_Jmp x_2081 5482  Jnz (x_2084, x_2083, x_2082) > h_Jnz x_2084 x_2083 x_2082 5483  MovSuccessor (x_2087, x_2086, x_2085) > 5484 h_MovSuccessor x_2087 x_2086 x_2085 5485  Call x_2088 > h_Call x_2088 5486  Mov (x_2090, x_2089) > h_Mov x_2090 x_2089 5487 5487 5488 5488 (** val pseudo_instruction_rect_Type5 : … … 5494 5494 > 'a1 **) 5495 5495 let rec pseudo_instruction_rect_Type5 h_Instruction h_Comment h_Cost h_Jmp h_Jnz h_MovSuccessor h_Call h_Mov = function 5496  Instruction x_2 4288 > h_Instruction x_242885497  Comment x_2 4289 > h_Comment x_242895498  Cost x_2 4290 > h_Cost x_242905499  Jmp x_2 4291 > h_Jmp x_242915500  Jnz (x_2 4294, x_24293, x_24292) > h_Jnz x_24294 x_24293 x_242925501  MovSuccessor (x_2 4297, x_24296, x_24295) >5502 h_MovSuccessor x_2 4297 x_24296 x_242955503  Call x_2 4298 > h_Call x_242985504  Mov (x_2 4300, x_24299) > h_Mov x_24300 x_242995496  Instruction x_2100 > h_Instruction x_2100 5497  Comment x_2101 > h_Comment x_2101 5498  Cost x_2102 > h_Cost x_2102 5499  Jmp x_2103 > h_Jmp x_2103 5500  Jnz (x_2106, x_2105, x_2104) > h_Jnz x_2106 x_2105 x_2104 5501  MovSuccessor (x_2109, x_2108, x_2107) > 5502 h_MovSuccessor x_2109 x_2108 x_2107 5503  Call x_2110 > h_Call x_2110 5504  Mov (x_2112, x_2111) > h_Mov x_2112 x_2111 5505 5505 5506 5506 (** val pseudo_instruction_rect_Type3 : … … 5512 5512 > 'a1 **) 5513 5513 let rec pseudo_instruction_rect_Type3 h_Instruction h_Comment h_Cost h_Jmp h_Jnz h_MovSuccessor h_Call h_Mov = function 5514  Instruction x_2 4310 > h_Instruction x_243105515  Comment x_2 4311 > h_Comment x_243115516  Cost x_2 4312 > h_Cost x_243125517  Jmp x_2 4313 > h_Jmp x_243135518  Jnz (x_2 4316, x_24315, x_24314) > h_Jnz x_24316 x_24315 x_243145519  MovSuccessor (x_2 4319, x_24318, x_24317) >5520 h_MovSuccessor x_2 4319 x_24318 x_243175521  Call x_2 4320 > h_Call x_243205522  Mov (x_2 4322, x_24321) > h_Mov x_24322 x_243215514  Instruction x_2122 > h_Instruction x_2122 5515  Comment x_2123 > h_Comment x_2123 5516  Cost x_2124 > h_Cost x_2124 5517  Jmp x_2125 > h_Jmp x_2125 5518  Jnz (x_2128, x_2127, x_2126) > h_Jnz x_2128 x_2127 x_2126 5519  MovSuccessor (x_2131, x_2130, x_2129) > 5520 h_MovSuccessor x_2131 x_2130 x_2129 5521  Call x_2132 > h_Call x_2132 5522  Mov (x_2134, x_2133) > h_Mov x_2134 x_2133 5523 5523 5524 5524 (** val pseudo_instruction_rect_Type2 : … … 5530 5530 > 'a1 **) 5531 5531 let rec pseudo_instruction_rect_Type2 h_Instruction h_Comment h_Cost h_Jmp h_Jnz h_MovSuccessor h_Call h_Mov = function 5532  Instruction x_2 4332 > h_Instruction x_243325533  Comment x_2 4333 > h_Comment x_243335534  Cost x_2 4334 > h_Cost x_243345535  Jmp x_2 4335 > h_Jmp x_243355536  Jnz (x_2 4338, x_24337, x_24336) > h_Jnz x_24338 x_24337 x_243365537  MovSuccessor (x_2 4341, x_24340, x_24339) >5538 h_MovSuccessor x_2 4341 x_24340 x_243395539  Call x_2 4342 > h_Call x_243425540  Mov (x_2 4344, x_24343) > h_Mov x_24344 x_243435532  Instruction x_2144 > h_Instruction x_2144 5533  Comment x_2145 > h_Comment x_2145 5534  Cost x_2146 > h_Cost x_2146 5535  Jmp x_2147 > h_Jmp x_2147 5536  Jnz (x_2150, x_2149, x_2148) > h_Jnz x_2150 x_2149 x_2148 5537  MovSuccessor (x_2153, x_2152, x_2151) > 5538 h_MovSuccessor x_2153 x_2152 x_2151 5539  Call x_2154 > h_Call x_2154 5540  Mov (x_2156, x_2155) > h_Mov x_2156 x_2155 5541 5541 5542 5542 (** val pseudo_instruction_rect_Type1 : … … 5548 5548 > 'a1 **) 5549 5549 let rec pseudo_instruction_rect_Type1 h_Instruction h_Comment h_Cost h_Jmp h_Jnz h_MovSuccessor h_Call h_Mov = function 5550  Instruction x_2 4354 > h_Instruction x_243545551  Comment x_2 4355 > h_Comment x_243555552  Cost x_2 4356 > h_Cost x_243565553  Jmp x_2 4357 > h_Jmp x_243575554  Jnz (x_2 4360, x_24359, x_24358) > h_Jnz x_24360 x_24359 x_243585555  MovSuccessor (x_2 4363, x_24362, x_24361) >5556 h_MovSuccessor x_2 4363 x_24362 x_243615557  Call x_2 4364 > h_Call x_243645558  Mov (x_2 4366, x_24365) > h_Mov x_24366 x_243655550  Instruction x_2166 > h_Instruction x_2166 5551  Comment x_2167 > h_Comment x_2167 5552  Cost x_2168 > h_Cost x_2168 5553  Jmp x_2169 > h_Jmp x_2169 5554  Jnz (x_2172, x_2171, x_2170) > h_Jnz x_2172 x_2171 x_2170 5555  MovSuccessor (x_2175, x_2174, x_2173) > 5556 h_MovSuccessor x_2175 x_2174 x_2173 5557  Call x_2176 > h_Call x_2176 5558  Mov (x_2178, x_2177) > h_Mov x_2178 x_2177 5559 5559 5560 5560 (** val pseudo_instruction_rect_Type0 : … … 5566 5566 > 'a1 **) 5567 5567 let rec pseudo_instruction_rect_Type0 h_Instruction h_Comment h_Cost h_Jmp h_Jnz h_MovSuccessor h_Call h_Mov = function 5568  Instruction x_2 4376 > h_Instruction x_243765569  Comment x_2 4377 > h_Comment x_243775570  Cost x_2 4378 > h_Cost x_243785571  Jmp x_2 4379 > h_Jmp x_243795572  Jnz (x_2 4382, x_24381, x_24380) > h_Jnz x_24382 x_24381 x_243805573  MovSuccessor (x_2 4385, x_24384, x_24383) >5574 h_MovSuccessor x_2 4385 x_24384 x_243835575  Call x_2 4386 > h_Call x_243865576  Mov (x_2 4388, x_24387) > h_Mov x_24388 x_243875568  Instruction x_2188 > h_Instruction x_2188 5569  Comment x_2189 > h_Comment x_2189 5570  Cost x_2190 > h_Cost x_2190 5571  Jmp x_2191 > h_Jmp x_2191 5572  Jnz (x_2194, x_2193, x_2192) > h_Jnz x_2194 x_2193 x_2192 5573  MovSuccessor (x_2197, x_2196, x_2195) > 5574 h_MovSuccessor x_2197 x_2196 x_2195 5575  Call x_2198 > h_Call x_2198 5576  Mov (x_2200, x_2199) > h_Mov x_2200 x_2199 5577 5577 5578 5578 (** val pseudo_instruction_inv_rect_Type4 : … … 5796 5796 Types.prod List.list > identifier > __ > __ > 'a1) > 5797 5797 pseudo_assembly_program > 'a1 **) 5798 let rec pseudo_assembly_program_rect_Type4 h_mk_pseudo_assembly_program x_2 4531=5798 let rec pseudo_assembly_program_rect_Type4 h_mk_pseudo_assembly_program x_2343 = 5799 5799 let { preamble = preamble0; code = code0; renamed_symbols = 5800 renamed_symbols0; final_label = final_label0 } = x_2 45315800 renamed_symbols0; final_label = final_label0 } = x_2343 5801 5801 in 5802 5802 h_mk_pseudo_assembly_program preamble0 code0 __ renamed_symbols0 … … 5808 5808 Types.prod List.list > identifier > __ > __ > 'a1) > 5809 5809 pseudo_assembly_program > 'a1 **) 5810 let rec pseudo_assembly_program_rect_Type5 h_mk_pseudo_assembly_program x_2 4533=5810 let rec pseudo_assembly_program_rect_Type5 h_mk_pseudo_assembly_program x_2345 = 5811 5811 let { preamble = preamble0; code = code0; renamed_symbols = 5812 renamed_symbols0; final_label = final_label0 } = x_2 45335812 renamed_symbols0; final_label = final_label0 } = x_2345 5813 5813 in 5814 5814 h_mk_pseudo_assembly_program preamble0 code0 __ renamed_symbols0 … … 5820 5820 Types.prod List.list > identifier > __ > __ > 'a1) > 5821 5821 pseudo_assembly_program > 'a1 **) 5822 let rec pseudo_assembly_program_rect_Type3 h_mk_pseudo_assembly_program x_2 4535=5822 let rec pseudo_assembly_program_rect_Type3 h_mk_pseudo_assembly_program x_2347 = 5823 5823 let { preamble = preamble0; code = code0; renamed_symbols = 5824 renamed_symbols0; final_label = final_label0 } = x_2 45355824 renamed_symbols0; final_label = final_label0 } = x_2347 5825 5825 in 5826 5826 h_mk_pseudo_assembly_program preamble0 code0 __ renamed_symbols0 … … 5832 5832 Types.prod List.list > identifier > __ > __ > 'a1) > 5833 5833 pseudo_assembly_program > 'a1 **) 5834 let rec pseudo_assembly_program_rect_Type2 h_mk_pseudo_assembly_program x_2 4537=5834 let rec pseudo_assembly_program_rect_Type2 h_mk_pseudo_assembly_program x_2349 = 5835 5835 let { preamble = preamble0; code = code0; renamed_symbols = 5836 renamed_symbols0; final_label = final_label0 } = x_2 45375836 renamed_symbols0; final_label = final_label0 } = x_2349 5837 5837 in 5838 5838 h_mk_pseudo_assembly_program preamble0 code0 __ renamed_symbols0 … … 5844 5844 Types.prod List.list > identifier > __ > __ > 'a1) > 5845 5845 pseudo_assembly_program > 'a1 **) 5846 let rec pseudo_assembly_program_rect_Type1 h_mk_pseudo_assembly_program x_2 4539=5846 let rec pseudo_assembly_program_rect_Type1 h_mk_pseudo_assembly_program x_2351 = 5847 5847 let { preamble = preamble0; code = code0; renamed_symbols = 5848 renamed_symbols0; final_label = final_label0 } = x_2 45395848 renamed_symbols0; final_label = final_label0 } = x_2351 5849 5849 in 5850 5850 h_mk_pseudo_assembly_program preamble0 code0 __ renamed_symbols0 … … 5856 5856 Types.prod List.list > identifier > __ > __ > 'a1) > 5857 5857 pseudo_assembly_program > 'a1 **) 5858 let rec pseudo_assembly_program_rect_Type0 h_mk_pseudo_assembly_program x_2 4541=5858 let rec pseudo_assembly_program_rect_Type0 h_mk_pseudo_assembly_program x_2353 = 5859 5859 let { preamble = preamble0; code = code0; renamed_symbols = 5860 renamed_symbols0; final_label = final_label0 } = x_2 45415860 renamed_symbols0; final_label = final_label0 } = x_2353 5861 5861 in 5862 5862 h_mk_pseudo_assembly_program preamble0 code0 __ renamed_symbols0 … … 5944 5944 (object_code > costlabel_map > symboltable_type > BitVector.word > __ 5945 5945 > 'a1) > labelled_object_code > 'a1 **) 5946 let rec labelled_object_code_rect_Type4 h_mk_labelled_object_code x_2 4557=5946 let rec labelled_object_code_rect_Type4 h_mk_labelled_object_code x_2369 = 5947 5947 let { oc = oc0; costlabels = costlabels0; symboltable = symboltable0; 5948 final_pc = final_pc0 } = x_2 45575948 final_pc = final_pc0 } = x_2369 5949 5949 in 5950 5950 h_mk_labelled_object_code oc0 costlabels0 symboltable0 final_pc0 __ … … 5953 5953 (object_code > costlabel_map > symboltable_type > BitVector.word > __ 5954 5954 > 'a1) > labelled_object_code > 'a1 **) 5955 let rec labelled_object_code_rect_Type5 h_mk_labelled_object_code x_2 4559=5955 let rec labelled_object_code_rect_Type5 h_mk_labelled_object_code x_2371 = 5956 5956 let { oc = oc0; costlabels = costlabels0; symboltable = symboltable0; 5957 final_pc = final_pc0 } = x_2 45595957 final_pc = final_pc0 } = x_2371 5958 5958 in 5959 5959 h_mk_labelled_object_code oc0 costlabels0 symboltable0 final_pc0 __ … … 5962 5962 (object_code > costlabel_map > symboltable_type > BitVector.word > __ 5963 5963 > 'a1) > labelled_object_code > 'a1 **) 5964 let rec labelled_object_code_rect_Type3 h_mk_labelled_object_code x_2 4561=5964 let rec labelled_object_code_rect_Type3 h_mk_labelled_object_code x_2373 = 5965 5965 let { oc = oc0; costlabels = costlabels0; symboltable = symboltable0; 5966 final_pc = final_pc0 } = x_2 45615966 final_pc = final_pc0 } = x_2373 5967 5967 in 5968 5968 h_mk_labelled_object_code oc0 costlabels0 symboltable0 final_pc0 __ … … 5971 5971 (object_code > costlabel_map > symboltable_type > BitVector.word > __ 5972 5972 > 'a1) > labelled_object_code > 'a1 **) 5973 let rec labelled_object_code_rect_Type2 h_mk_labelled_object_code x_2 4563=5973 let rec labelled_object_code_rect_Type2 h_mk_labelled_object_code x_2375 = 5974 5974 let { oc = oc0; costlabels = costlabels0; symboltable = symboltable0; 5975 final_pc = final_pc0 } = x_2 45635975 final_pc = final_pc0 } = x_2375 5976 5976 in 5977 5977 h_mk_labelled_object_code oc0 costlabels0 symboltable0 final_pc0 __ … … 5980 5980 (object_code > costlabel_map > symboltable_type > BitVector.word > __ 5981 5981 > 'a1) > labelled_object_code > 'a1 **) 5982 let rec labelled_object_code_rect_Type1 h_mk_labelled_object_code x_2 4565=5982 let rec labelled_object_code_rect_Type1 h_mk_labelled_object_code x_2377 = 5983 5983 let { oc = oc0; costlabels = costlabels0; symboltable = symboltable0; 5984 final_pc = final_pc0 } = x_2 45655984 final_pc = final_pc0 } = x_2377 5985 5985 in 5986 5986 h_mk_labelled_object_code oc0 costlabels0 symboltable0 final_pc0 __ … … 5989 5989 (object_code > costlabel_map > symboltable_type > BitVector.word > __ 5990 5990 > 'a1) > labelled_object_code > 'a1 **) 5991 let rec labelled_object_code_rect_Type0 h_mk_labelled_object_code x_2 4567=5991 let rec labelled_object_code_rect_Type0 h_mk_labelled_object_code x_2379 = 5992 5992 let { oc = oc0; costlabels = costlabels0; symboltable = symboltable0; 5993 final_pc = final_pc0 } = x_2 45675993 final_pc = final_pc0 } = x_2379 5994 5994 in 5995 5995 h_mk_labelled_object_code oc0 costlabels0 symboltable0 final_pc0 __
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