Changeset 2867 for extracted/rTL.ml


Ignore:
Timestamp:
Mar 13, 2013, 11:12:29 PM (7 years ago)
Author:
sacerdot
Message:

New extraction after indianess bug fixes by Paolo.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • extracted/rTL.ml

    r2854 r2867  
    111111    (Registers.register -> Registers.register -> 'a1) -> rtl_seq -> 'a1 **)
    112112let rec rtl_seq_rect_Type4 h_rtl_stack_address = function
    113 | Rtl_stack_address (x_2091, x_2090) -> h_rtl_stack_address x_2091 x_2090
     113| Rtl_stack_address (x_20906, x_20905) -> h_rtl_stack_address x_20906 x_20905
    114114
    115115(** val rtl_seq_rect_Type5 :
    116116    (Registers.register -> Registers.register -> 'a1) -> rtl_seq -> 'a1 **)
    117117let rec rtl_seq_rect_Type5 h_rtl_stack_address = function
    118 | Rtl_stack_address (x_2095, x_2094) -> h_rtl_stack_address x_2095 x_2094
     118| Rtl_stack_address (x_20910, x_20909) -> h_rtl_stack_address x_20910 x_20909
    119119
    120120(** val rtl_seq_rect_Type3 :
    121121    (Registers.register -> Registers.register -> 'a1) -> rtl_seq -> 'a1 **)
    122122let rec rtl_seq_rect_Type3 h_rtl_stack_address = function
    123 | Rtl_stack_address (x_2099, x_2098) -> h_rtl_stack_address x_2099 x_2098
     123| Rtl_stack_address (x_20914, x_20913) -> h_rtl_stack_address x_20914 x_20913
    124124
    125125(** val rtl_seq_rect_Type2 :
    126126    (Registers.register -> Registers.register -> 'a1) -> rtl_seq -> 'a1 **)
    127127let rec rtl_seq_rect_Type2 h_rtl_stack_address = function
    128 | Rtl_stack_address (x_2103, x_2102) -> h_rtl_stack_address x_2103 x_2102
     128| Rtl_stack_address (x_20918, x_20917) -> h_rtl_stack_address x_20918 x_20917
    129129
    130130(** val rtl_seq_rect_Type1 :
    131131    (Registers.register -> Registers.register -> 'a1) -> rtl_seq -> 'a1 **)
    132132let rec rtl_seq_rect_Type1 h_rtl_stack_address = function
    133 | Rtl_stack_address (x_2107, x_2106) -> h_rtl_stack_address x_2107 x_2106
     133| Rtl_stack_address (x_20922, x_20921) -> h_rtl_stack_address x_20922 x_20921
    134134
    135135(** val rtl_seq_rect_Type0 :
    136136    (Registers.register -> Registers.register -> 'a1) -> rtl_seq -> 'a1 **)
    137137let rec rtl_seq_rect_Type0 h_rtl_stack_address = function
    138 | Rtl_stack_address (x_2111, x_2110) -> h_rtl_stack_address x_2111 x_2110
     138| Rtl_stack_address (x_20926, x_20925) -> h_rtl_stack_address x_20926 x_20925
    139139
    140140(** val rtl_seq_inv_rect_Type4 :
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