Changeset 162 for Deliverables
 Timestamp:
 Oct 7, 2010, 2:49:53 PM (10 years ago)
 Location:
 Deliverables/D4.1
 Files:

 3 edited
Legend:
 Unmodified
 Added
 Removed

Deliverables/D4.1/ASMInterpret.ml
r161 r162 865 865 let addr = (int_of_vect (mk_byte7 r1 r2 r3 n2)) in 866 866 let addr' = vect_of_int ((addr / 8) + 32) `Seven in 867 let bit = get_bit (Byte7Map.find addr' status.low_internal_ram) (addr mod 8) in 868 (match bit with 869 None > assert false 870  Some bit' > bit') 867 get_bit (Byte7Map.find addr' status.low_internal_ram) (addr mod 8) 871 868  (true,r1,r2,r3) > 872 869 let addr = int_of_vect $ mk_byte7 r1 r2 r3 n2 in 873 870 let div = addr / 8 in 874 871 let rem = addr mod 8 in 875 match get_bit (get_sfr status (vect_of_int ((div * 8) + 128) `Eight)) rem with 876 Some x > x 877  None > assert false) 872 get_bit (get_sfr status (vect_of_int ((div * 8) + 128) `Eight)) rem) 878 873 in (match x with `BIT _ > res  _ > not res) 879 874  `C > get_cy_flag status … … 888 883 let addr' = vect_of_int ((addr / 8) + 32) `Seven in 889 884 let n_bit = set_bit (Byte7Map.find addr' status.low_internal_ram) (addr mod 8) v in 890 (match n_bit with 891 None > assert false 892  Some n_bit' > 893 { status with low_internal_ram = Byte7Map.add addr' n_bit' status.low_internal_ram }) 885 { status with low_internal_ram = Byte7Map.add addr' n_bit status.low_internal_ram } 894 886  (true,r1,r2,r3) > 895 887 let addr = int_of_vect $ mk_byte7 r1 r2 r3 n2 in … … 899 891 let sfr = get_sfr status addr' in 900 892 let sfr' = set_bit sfr rem v in 901 (match sfr' with 902 Some x > set_sfr status addr' x 903  None > assert false)) 893 set_sfr status addr' sfr') 904 894  `C > 905 895 let (n1,n2) = from_byte status.psw in … … 1281 1271  (_,_,b1,b2),(_,_,b3,b4) > 1282 1272 let b = get_bit status.tcon 4 in 1283 (match b with 1284 None > assert false 1285  Some b' > 1286 if b' then 1287 (* Timer0 first *) 1288 (match b1,b2 with 1289 true,true > assert false 1290  false,false > assert false 1291  false,true > 1292 (* TYPE ERROR! *) 1293 let res,ac,ov,cy = add16_with_c (mk_word status.th0 status.tl0) (vect_of_int 1 `Sixteen) false in 1273 let status = 1274 (* Timer0 first *) 1275 (match b1,b2 with 1276 true,true > 1277 (* 13 bit mode *) 1278 if b then 1279 let res,_,_,_ = add8_with_c status.tl0 (vect_of_int ticks `Eight) false in 1280 let res = int_of_vect res in 1281 if res > 31 then 1282 let res = res mod 32 in 1283 let res',cy',ov',ac' = add8_with_c status.th0 (vect_of_int 1 `Eight) false in 1284 if ov' then 1285 let b = set_bit status.tcon 7 true in 1286 { status with tcon = b; th0 = res'; tl0 = vect_of_int res `Eight } 1287 else 1288 { status with th0 = res'; tl0 = vect_of_int res `Eight } 1289 else 1290 { status with tl0 = vect_of_int res `Eight } 1291 else 1292 status 1293  false,false > 1294 (* split timer mode *) 1295 let status = 1296 (if b then 1297 let res,cy,ov,ac = add8_with_c status.tl0 (vect_of_int ticks `Eight) false in 1294 1298 if ov then 1295 1299 let b = set_bit status.tcon 5 true in 1296 (match b with 1297 None > assert false 1298  Some sts > assert false (* DPM: implement! *)) 1300 { status with tcon = b; tl0 = res } 1299 1301 else 1300 assert false (* DPM: implement *) 1301  true,false > assert false) 1302 { status with tl0 = res } 1303 else 1304 status) 1305 in 1306 if get_bit status.tcon 6 then 1307 let res,cy,ov,ac = add8_with_c status.th0 (vect_of_int ticks `Eight) false in 1308 if ov then 1309 let b = set_bit status.tcon 7 true in 1310 { status with tcon = b; th0 = res } 1311 else 1312 { status with th0 = res } 1313 else 1314 status 1315  false,true > 1316 (* 16 bit timer mode *) 1317 if b then 1318 let res,_,ov,_ = add16_with_c (mk_word status.th0 status.tl0) (vect_of_int ticks `Sixteen) false in 1319 if ov then 1320 let b = set_bit status.tcon 5 true in 1321 let new_th0,new_tl0 = from_word res in 1322 { status with tcon = b; th0 = new_th0; tl0 = new_tl0 } 1323 else 1324 let new_th0,new_tl0 = from_word res in 1325 { status with th0 = new_th0; tl0 = new_tl0 } 1326 else 1327 status 1328  true,false > 1329 (* 8 bit timer mode *) 1330 if b then 1331 let res,_,ov,_ = add8_with_c status.tl0 (vect_of_int ticks `Eight) false in 1332 if ov then 1333 let b = set_bit status.tcon 5 true in 1334 { status with tcon = b; tl0 = status.th0; } 1335 else 1336 { status with tl0 = res } 1337 else 1338 status) in 1339 (* timer 1 now *) 1340 (match b3,b4 with 1341 true,true > 1342 (* 13 bit mode *) 1343 if b then 1344 let res,_,_,_ = add8_with_c status.tl1 (vect_of_int ticks `Eight) false in 1345 let res = int_of_vect res in 1346 if res > 31 then 1347 let res = res mod 32 in 1348 let res',cy',ov',ac' = add8_with_c status.th1 (vect_of_int 1 `Eight) false in 1349 if ov' then 1350 let b = set_bit status.tcon 7 true in 1351 { status with tcon = b; th1 = res'; tl1 = vect_of_int res `Eight } 1352 else 1353 { status with th1 = res'; tl0 = vect_of_int res `Eight } 1354 else 1355 { status with tl1 = vect_of_int res `Eight } 1356 else 1357 status 1358  false,false > 1359 (* split timer mode *) 1360 let status = 1361 (if b then 1362 let res,cy,ov,ac = add8_with_c status.tl1 (vect_of_int ticks `Eight) false in 1363 if ov then 1364 let b = set_bit status.tcon 5 true in 1365 { status with tcon = b; tl1 = res } 1366 else 1367 { status with tl1 = res } 1368 else 1369 status) 1370 in 1371 if get_bit status.tcon 6 then 1372 let res,cy,ov,ac = add8_with_c status.th1 (vect_of_int ticks `Eight) false in 1373 if ov then 1374 let b = set_bit status.tcon 7 true in 1375 { status with tcon = b; th1 = res } 1376 else 1377 { status with th1 = res } 1378 else 1379 status 1380  false,true > 1381 (* 16 bit timer mode *) 1382 if b then 1383 let res,_,ov,_ = add16_with_c (mk_word status.th0 status.tl1) (vect_of_int ticks `Sixteen) false in 1384 if ov then 1385 let b = set_bit status.tcon 5 true in 1386 let new_th1,new_tl1 = from_word res in 1387 { status with tcon = b; th1 = new_th1; tl1 = new_tl1 } 1388 else 1389 let new_th1,new_tl1 = from_word res in 1390 { status with th1 = new_th1; tl1 = new_tl1 } 1391 else 1392 status 1393  true,false > 1394 (* 8 bit timer mode *) 1395 if b then 1396 let res,_,ov,_ = add8_with_c status.tl1 (vect_of_int ticks `Eight) false in 1397 if ov then 1398 let b = set_bit status.tcon 5 true in 1399 { status with tcon = b; tl1 = status.th1; } 1400 else 1401 { status with tl1 = res } 1302 1402 else 1303 1403 status) 1304 1305 1404 ;; 1306 1405 
Deliverables/D4.1/BitVectors.ml
r147 r162 39 39 let get_bit index l = 40 40 try 41 Some (List.nth index l)42 with (Failure _  Invalid_argument _) > None41 List.nth index l 42 with (Failure _  Invalid_argument _) > assert false 43 43 44 44 let set_bit l index new_val = … … 49 49  0,_::tl > new_val::tl 50 50  n,hd::tl > hd::(aux (n1) tl) in 51 Some (List.rev (aux index (List.rev l)))52 with Invalid_argument "" > None51 List.rev (aux index (List.rev l)) 52 with Invalid_argument "" > assert false 53 53 54 54 let (&) l1 l2 = List.map2 (fun b1 b2 > b1 & b2) l1 l2 
Deliverables/D4.1/BitVectors.mli
r147 r162 24 24 val from_word11: word11 > bit * bit * bit * byte 25 25 26 val get_bit: 'a vect > int > bit option27 val set_bit: 'a vect > int > bit > 'a vect option26 val get_bit: 'a vect > int > bit 27 val set_bit: 'a vect > int > bit > 'a vect 28 28 29 29 val int_of_vect: 'a vect > int
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