Changeset 158


Ignore:
Timestamp:
Oct 6, 2010, 4:36:08 PM (9 years ago)
Author:
mulligan
Message:

Lots of bugs fixed. SFR access implemented.

Location:
Deliverables/D4.1
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • Deliverables/D4.1/ASM.mli

    r120 r158  
    1616type acc_dptr = [ `A_DPTR ]
    1717type acc_pc = [ `A_PC ]
     18type ext_indirect_dptr = [ `EXT_IND_DPTR ]
    1819type indirect_dptr = [ `IND_DPTR ]
    19 type ext_indirect_dptr = [ `EXT_IND_DPTR ]
    2020type carry = [ `C ]
    2121type bit = [ `BIT of byte ]
  • Deliverables/D4.1/ASMInterpret.ml

    r151 r158  
    6868 match int_of_vect addr with
    6969  (* I/O and timer ports *)
    70     0x80 -> Some status.p0
    71   | 0x90 -> Some status.p1
    72   | 0xA0 -> Some status.p2
    73   | 0xB0 -> Some status.p3
    74   | 0x99 -> Some status.sbuf
    75   | 0x90 -> Some status.tl0
    76   | 0x91 -> Some status.tl1
    77   | 0x92 -> Some status.th0
    78   | 0x93 -> Some status.th1
    79   | 0xC8 -> Some status.t2con
    80   | 0xCA -> Some status.rcap2l
    81   | 0xCB -> Some status.rcap2h
    82   | 0xCD -> Some status.tl2
    83   | 0xCE -> Some status.th2
     70    0x80 -> status.p0
     71  | 0x90 -> status.p1
     72  | 0xA0 -> status.p2
     73  | 0xB0 -> status.p3
     74  | 0x99 -> status.sbuf
     75  | 0x8A -> status.tl0
     76  | 0x8B -> status.tl1
     77  | 0x8C -> status.th0
     78  | 0x8D -> status.th1
     79  | 0xC8 -> status.t2con
     80  | 0xCA -> status.rcap2l
     81  | 0xCB -> status.rcap2h
     82  | 0xCC -> status.tl2
     83  | 0xCD -> status.th2
    8484
    8585  (* control ports *)
    86   | 0x87 -> Some status.pcon
    87   | 0x88 -> Some status.tcon
    88   | 0x89 -> Some status.tmod
    89   | 0x98 -> Some status.scon
    90   | 0xA8 -> Some status.ie
    91   | 0xB8 -> Some status.ip
     86  | 0x87 -> status.pcon
     87  | 0x88 -> status.tcon
     88  | 0x89 -> status.tmod
     89  | 0x98 -> status.scon
     90  | 0xA8 -> status.ie
     91  | 0xB8 -> status.ip
    9292
    9393  (* registers *)
    94   | 0x81 -> Some status.sp
    95   | 0x82 -> Some status.dpl
    96   | 0x83 -> Some status.dph
    97   | 0xD0 -> Some status.psw
    98   | 0xE0 -> Some status.acc
    99   | 0xF0 -> Some status.b
    100   | _ -> None
     94  | 0x81 -> status.sp
     95  | 0x82 -> status.dpl
     96  | 0x83 -> status.dph
     97  | 0xD0 -> status.psw
     98  | 0xE0 -> status.acc
     99  | 0xF0 -> status.b
     100  | _ -> assert false
    101101;;
    102102
     
    105105 match int_of_vect addr with
    106106  (* I/O and timer ports *)
    107     0x80 -> Some { status with p0 = v }
    108   | 0x90 -> Some { status with p1 = v }
    109   | 0xA0 -> Some { status with p2 = v }
    110   | 0xB0 -> Some { status with p3 = v }
    111   | 0x99 -> Some { status with sbuf = v }
    112   | 0x90 -> Some { status with tl0 = v }
    113   | 0x91 -> Some { status with tl1 = v }
    114   | 0x92 -> Some { status with th0 = v }
    115   | 0x93 -> Some { status with th1 = v }
    116   | 0xC8 -> Some { status with t2con = v }
    117   | 0xCA -> Some { status with rcap2l = v }
    118   | 0xCB -> Some { status with rcap2h = v }
    119   | 0xCD -> Some { status with tl2 = v }
    120   | 0xCE -> Some { status with th2 = v }
     107    0x80 -> { status with p0 = v }
     108  | 0x90 -> { status with p1 = v }
     109  | 0xA0 -> { status with p2 = v }
     110  | 0xB0 -> { status with p3 = v }
     111  | 0x99 -> { status with sbuf = v }
     112  | 0x8A -> { status with tl0 = v }
     113  | 0x8B -> { status with tl1 = v }
     114  | 0x8C -> { status with th0 = v }
     115  | 0x8D -> { status with th1 = v }
     116  | 0xC8 -> { status with t2con = v }
     117  | 0xCA -> { status with rcap2l = v }
     118  | 0xCB -> { status with rcap2h = v }
     119  | 0xCD -> { status with tl2 = v }
     120  | 0xCE -> { status with th2 = v }
    121121
    122122  (* control ports *)
    123   | 0x87 -> Some { status with pcon = v }
    124   | 0x88 -> Some { status with tcon = v }
    125   | 0x89 -> Some { status with tmod = v }
    126   | 0x98 -> Some { status with scon = v }
    127   | 0xA8 -> Some { status with ie = v }
    128   | 0xB8 -> Some { status with ip = v }
     123  | 0x87 -> { status with pcon = v }
     124  | 0x88 -> { status with tcon = v }
     125  | 0x89 -> { status with tmod = v }
     126  | 0x98 -> { status with scon = v }
     127  | 0xA8 -> { status with ie = v }
     128  | 0xB8 -> { status with ip = v }
    129129
    130130  (* registers *)
    131   | 0x81 -> Some { status with sp = v }
    132   | 0x82 -> Some { status with dpl = v }
    133   | 0x83 -> Some { status with dph = v }
    134   | 0xD0 -> Some { status with psw = v }
    135   | 0xE0 -> Some { status with acc = v }
    136   | 0xF0 -> Some { status with b = v }
    137   | _ -> None
     131  | 0x81 -> { status with sp = v }
     132  | 0x82 -> { status with dpl = v }
     133  | 0x83 -> { status with dph = v }
     134  | 0xD0 -> { status with psw = v }
     135  | 0xE0 -> { status with acc = v }
     136  | 0xF0 -> { status with b = v }
     137  | _ -> assert false
    138138;;
    139139
     
    822822          (false,r1,r2,r3) ->
    823823            Byte7Map.find (mk_byte7 r1 r2 r3 n1) status.low_internal_ram
    824         | _ ->
    825             (match get_sfr status addr with
    826                Some x -> x
    827              | None -> assert false))
     824        | _ -> get_sfr status addr)
    828825  | `INDIRECT b ->
    829826       let (b1, b2) = from_byte (get_register status (false,false,b)) in
     
    848845       let cry,addr = half_add status.pc (mk_word (vect_of_int 0 `Eight) status.acc) in
    849846         WordMap.find addr status.external_ram
    850   | `IND_DPTR ->
     847  | `EXT_INDIRECT b ->
     848         let addr = get_register status (false,false,b) in
     849           WordMap.find (mk_word (zero `Eight) addr) status.external_ram
     850  | `EXT_IND_DPTR ->
    851851       let dpr = mk_word status.dph status.dpl in
    852852         WordMap.find dpr status.external_ram
     
    870870             | Some bit' -> bit')
    871871        | (true,r1,r2,r3) ->
    872             let addr' = mk_byte7 r1 r2 r3 n2 in
    873               (match get_sfr status addr' with
     872            let addr = int_of_vect $ mk_byte7 r1 r2 r3 n2 in
     873            let div = addr / 8 in
     874            let rem = addr mod 8 in
     875              match get_bit (get_sfr status (vect_of_int ((div * 8) + 128) `Eight)) rem with
    874876                Some x -> x
    875               | None -> assert false))
     877              | None -> assert false)
    876878    in (match x with `BIT _ -> res | _ -> not res)
    877879  | `C -> get_cy_flag status
     
    891893                  { status with low_internal_ram = Byte7Map.add addr' n_bit' status.low_internal_ram })
    892894      | (true,r1,r2,r3) ->
    893            (* assert false for now. Try to understand what DEC really does *)
    894            let addr = mk_byte7 r1 r2 r3 n2 in
    895              match set_sfr status addr v with
    896                Some status -> status
    897              | None -> assert false)
     895            let addr = int_of_vect $ mk_byte7 r1 r2 r3 n2 in
     896            let div = addr / 8 in
     897            let rem = addr mod 8 in
     898            let addr' = vect_of_int ((div * 8) + 128) `Eight in
     899            let sfr = get_sfr status addr' in
     900            let sfr' = set_bit sfr rem v in
     901              (match sfr' with
     902                Some x -> set_sfr status addr' x
     903              | None -> assert false))
    898904    | `C ->
    899905       let (n1,n2) = from_byte status.psw in
     
    923929  | `A -> { status with acc = v }
    924930  | `B -> { status with b = v }
    925   | `IND_DPTR ->
    926      let dpr = mk_word status.dph status.dpl in
    927       { status with external_ram =
    928         WordMap.add dpr v status.external_ram }
     931  | `EXT_IND_DPTR ->
     932      let dpr = mk_word status.dph status.dpl in
     933        { status with external_ram =
     934          WordMap.add dpr v status.external_ram }
     935  | `EXT_INDIRECT b ->
     936     let addr = get_register status (false,false,b) in
     937       { status with external_ram =
     938           WordMap.add (mk_word (zero `Eight) addr) v status.external_ram }
    929939;;
    930940
     
    11071117     let lookup = WordMap.find addr status.code_memory in
    11081118       { status with acc = lookup }
    1109  (* data transfer *)
    1110 (*
    1111  | MOVX of (acc * [ indirect | indirect_dptr ],
    1112             [ indirect | indirect_dptr ] * acc) union2
    1113 *)
     1119  (* data transfer *)
     1120  (* DPM: MOVX currently only implements the *copying* of data! *)
     1121  | `MOVX (`U1 (a1, a2)) -> set_arg_8 status (get_arg_8 status a2) a1
     1122  | `MOVX (`U2 (a1, a2)) -> set_arg_8 status (get_arg_8 status a2) a1
    11141123  | `SETB b -> set_arg_1 status true b
    11151124  | `PUSH (`DIRECT b) ->
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