Changeset 151 for Deliverables/D4.1
- Timestamp:
- Oct 6, 2010, 11:29:14 AM (10 years ago)
- File:
-
- 1 edited
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Deliverables/D4.1/ASMInterpret.ml
r150 r151 68 68 match int_of_vect addr with 69 69 (* I/O and timer ports *) 70 0x80 -> status.p071 | 0x90 -> status.p172 | 0xA0 -> status.p273 | 0xB0 -> status.p374 | 0x99 -> status.sbuf75 | 0x90 -> status.tl076 | 0x91 -> status.tl177 | 0x92 -> status.th078 | 0x93 -> status.th179 | 0xC8 -> status.t2con80 | 0xCA -> status.rcap2l81 | 0xCB -> status.rcap2h82 | 0xCD -> status.tl283 | 0xCE -> status.th270 0x80 -> Some status.p0 71 | 0x90 -> Some status.p1 72 | 0xA0 -> Some status.p2 73 | 0xB0 -> Some status.p3 74 | 0x99 -> Some status.sbuf 75 | 0x90 -> Some status.tl0 76 | 0x91 -> Some status.tl1 77 | 0x92 -> Some status.th0 78 | 0x93 -> Some status.th1 79 | 0xC8 -> Some status.t2con 80 | 0xCA -> Some status.rcap2l 81 | 0xCB -> Some status.rcap2h 82 | 0xCD -> Some status.tl2 83 | 0xCE -> Some status.th2 84 84 85 85 (* control ports *) 86 | 0x87 -> status.pcon87 | 0x88 -> status.tcon88 | 0x89 -> status.tmod89 | 0x98 -> status.scon90 | 0xA8 -> status.ie91 | 0xB8 -> status.ip86 | 0x87 -> Some status.pcon 87 | 0x88 -> Some status.tcon 88 | 0x89 -> Some status.tmod 89 | 0x98 -> Some status.scon 90 | 0xA8 -> Some status.ie 91 | 0xB8 -> Some status.ip 92 92 93 93 (* registers *) 94 | 0x81 -> status.sp95 | 0x82 -> status.dpl96 | 0x83 -> status.dph97 | 0xD0 -> status.psw98 | 0xE0 -> status.acc99 | 0xF0 -> status.b100 | _ -> assert false94 | 0x81 -> Some status.sp 95 | 0x82 -> Some status.dpl 96 | 0x83 -> Some status.dph 97 | 0xD0 -> Some status.psw 98 | 0xE0 -> Some status.acc 99 | 0xF0 -> Some status.b 100 | _ -> None 101 101 ;; 102 102 … … 105 105 match int_of_vect addr with 106 106 (* I/O and timer ports *) 107 0x80 -> { status with p0 = v }108 | 0x90 -> { status with p1 = v }109 | 0xA0 -> { status with p2 = v }110 | 0xB0 -> { status with p3 = v }111 | 0x99 -> { status with sbuf = v }112 | 0x90 -> { status with tl0 = v }113 | 0x91 -> { status with tl1 = v }114 | 0x92 -> { status with th0 = v }115 | 0x93 -> { status with th1 = v }116 | 0xC8 -> { status with t2con = v }117 | 0xCA -> { status with rcap2l = v }118 | 0xCB -> { status with rcap2h = v }119 | 0xCD -> { status with tl2 = v }120 | 0xCE -> { status with th2 = v }107 0x80 -> Some { status with p0 = v } 108 | 0x90 -> Some { status with p1 = v } 109 | 0xA0 -> Some { status with p2 = v } 110 | 0xB0 -> Some { status with p3 = v } 111 | 0x99 -> Some { status with sbuf = v } 112 | 0x90 -> Some { status with tl0 = v } 113 | 0x91 -> Some { status with tl1 = v } 114 | 0x92 -> Some { status with th0 = v } 115 | 0x93 -> Some { status with th1 = v } 116 | 0xC8 -> Some { status with t2con = v } 117 | 0xCA -> Some { status with rcap2l = v } 118 | 0xCB -> Some { status with rcap2h = v } 119 | 0xCD -> Some { status with tl2 = v } 120 | 0xCE -> Some { status with th2 = v } 121 121 122 122 (* control ports *) 123 | 0x87 -> { status with pcon = v }124 | 0x88 -> { status with tcon = v }125 | 0x89 -> { status with tmod = v }126 | 0x98 -> { status with scon = v }127 | 0xA8 -> { status with ie = v }128 | 0xB8 -> { status with ip = v }123 | 0x87 -> Some { status with pcon = v } 124 | 0x88 -> Some { status with tcon = v } 125 | 0x89 -> Some { status with tmod = v } 126 | 0x98 -> Some { status with scon = v } 127 | 0xA8 -> Some { status with ie = v } 128 | 0xB8 -> Some { status with ip = v } 129 129 130 130 (* registers *) 131 | 0x81 -> { status with sp = v }132 | 0x82 -> { status with dpl = v }133 | 0x83 -> { status with dph = v }134 | 0xD0 -> { status with psw = v }135 | 0xE0 -> { status with acc = v }136 | 0xF0 -> { status with b = v }137 | _ -> assert false131 | 0x81 -> Some { status with sp = v } 132 | 0x82 -> Some { status with dpl = v } 133 | 0x83 -> Some { status with dph = v } 134 | 0xD0 -> Some { status with psw = v } 135 | 0xE0 -> Some { status with acc = v } 136 | 0xF0 -> Some { status with b = v } 137 | _ -> None 138 138 ;; 139 139 … … 822 822 (false,r1,r2,r3) -> 823 823 Byte7Map.find (mk_byte7 r1 r2 r3 n1) status.low_internal_ram 824 | _ -> get_sfr status addr) 824 | _ -> 825 (match get_sfr status addr with 826 Some x -> x 827 | None -> assert false)) 825 828 | `INDIRECT b -> 826 829 let (b1, b2) = from_byte (get_register status (false,false,b)) in … … 867 870 | Some bit' -> bit') 868 871 | (true,r1,r2,r3) -> 869 (*CSC: SFR access, TO BE IMPLEMENTED *) 870 assert false) 872 let addr' = mk_byte7 r1 r2 r3 n2 in 873 (match get_sfr status addr' with 874 Some x -> x 875 | None -> assert false)) 871 876 in (match x with `BIT _ -> res | _ -> not res) 872 877 | `C -> get_cy_flag status … … 886 891 { status with low_internal_ram = Byte7Map.add addr' n_bit' status.low_internal_ram }) 887 892 | (true,r1,r2,r3) -> 888 (*CSC: SFR access, TO BE IMPLEMENTED *)889 893 (* assert false for now. Try to understand what DEC really does *) 890 assert false) 894 let addr = mk_byte7 r1 r2 r3 n2 in 895 match set_sfr status addr v with 896 Some status -> status 897 | None -> assert false) 891 898 | `C -> 892 899 let (n1,n2) = from_byte status.psw in
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