Ignore:
Timestamp:
Sep 29, 2010, 1:27:40 PM (10 years ago)
Author:
sacerdot
Message:

Rough implementation of direct (i.e. no BIT) SFR access.
Note: I/O is not handled properly. Thus the current implementation only
makes sense for real registers like SP, PSW, etc.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • Deliverables/D4.1/test.ml

    r140 r142  
    44let observe status =
    55 let pc = status.ASMInterpret.pc in
    6  let opcode = Physical.WordMap.find pc status.ASMInterpret.code_memory in
    76 let instr,_,_ = ASMInterpret.fetch status.ASMInterpret.code_memory pc in
    8   prerr_string ("pc = " ^ BitVectors.hex_string_of_vect pc) ;
    9   prerr_string (" : " ^ BitVectors.hex_string_of_vect opcode);
    10   prerr_endline (" = " ^ Pretty.pp_instruction instr)
     7  prerr_string (BitVectors.hex_string_of_vect pc) ;
     8  prerr_endline (": " ^ Pretty.pp_instruction instr)
    119in
    1210 ASMInterpret.execute observe status
Note: See TracChangeset for help on using the changeset viewer.