1 | include "arithmetics/nat.ma". |
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2 | include "basics/jmeq.ma". |
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3 | |
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4 | include "ASM/String.ma". |
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5 | include "ASM/ASM.ma". |
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6 | include "ASM/Arithmetic.ma". |
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7 | include "joint/BEValues.ma". |
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8 | include "ASM/BitVectorTrie.ma". |
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9 | |
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10 | definition int_size ≝ bitvector_of_nat 8 1. |
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11 | definition ptr_size ≝ bitvector_of_nat 8 2. |
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12 | definition alignment ≝ None. |
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13 | |
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14 | (* dpm: Can these two inductive definitions be merged? In LIN, yes, but perhaps |
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15 | not further back in the translation chain. *) |
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16 | inductive OpAccs: Type[0] ≝ |
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17 | Mul: OpAccs |
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18 | | DivuModu: OpAccs. |
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19 | |
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20 | inductive Op1: Type[0] ≝ |
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21 | Cmpl: Op1 |
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22 | | Inc: Op1. |
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23 | |
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24 | inductive Op2: Type[0] ≝ |
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25 | Add: Op2 |
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26 | | Addc: Op2 |
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27 | | Sub: Op2 |
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28 | | And: Op2 |
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29 | | Or: Op2 |
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30 | | Xor: Op2. |
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31 | |
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32 | (* dpm: maybe useless? *) |
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33 | inductive Register: Type[0] ≝ |
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34 | Register00: Register |
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35 | | Register01: Register |
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36 | | Register02: Register |
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37 | | Register03: Register |
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38 | | Register04: Register |
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39 | | Register05: Register |
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40 | | Register06: Register |
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41 | | Register07: Register |
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42 | | Register10: Register |
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43 | | Register11: Register |
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44 | | Register12: Register |
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45 | | Register13: Register |
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46 | | Register14: Register |
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47 | | Register15: Register |
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48 | | Register16: Register |
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49 | | Register17: Register |
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50 | | Register20: Register |
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51 | | Register21: Register |
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52 | | Register22: Register |
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53 | | Register23: Register |
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54 | | Register24: Register |
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55 | | Register25: Register |
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56 | | Register26: Register |
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57 | | Register27: Register |
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58 | | Register30: Register |
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59 | | Register31: Register |
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60 | | Register32: Register |
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61 | | Register33: Register |
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62 | | Register34: Register |
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63 | | Register35: Register |
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64 | | Register36: Register |
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65 | | Register37: Register |
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66 | | RegisterA: Register |
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67 | | RegisterB: Register |
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68 | | RegisterDPL: Register |
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69 | | RegisterDPH: Register |
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70 | | RegisterCarry: Register. |
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71 | |
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72 | definition nat_of_register: Register → nat ≝ |
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73 | λr: Register. |
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74 | match r with |
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75 | [ Register00 ⇒ 0 |
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76 | | Register01 ⇒ 1 |
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77 | | Register02 ⇒ 2 |
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78 | | Register03 ⇒ 3 |
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79 | | Register04 ⇒ 4 |
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80 | | Register05 ⇒ 5 |
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81 | | Register06 ⇒ 6 |
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82 | | Register07 ⇒ 7 |
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83 | | Register10 ⇒ 8 |
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84 | | Register11 ⇒ 9 |
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85 | | Register12 ⇒ 10 |
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86 | | Register13 ⇒ 11 |
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87 | | Register14 ⇒ 12 |
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88 | | Register15 ⇒ 13 |
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89 | | Register16 ⇒ 14 |
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90 | | Register17 ⇒ 15 |
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91 | | Register20 ⇒ 16 |
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92 | | Register21 ⇒ 17 |
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93 | | Register22 ⇒ 18 |
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94 | | Register23 ⇒ 19 |
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95 | | Register24 ⇒ 20 |
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96 | | Register25 ⇒ 21 |
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97 | | Register26 ⇒ 22 |
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98 | | Register27 ⇒ 23 |
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99 | | Register30 ⇒ 24 |
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100 | | Register31 ⇒ 25 |
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101 | | Register32 ⇒ 26 |
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102 | | Register33 ⇒ 27 |
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103 | | Register34 ⇒ 28 |
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104 | | Register35 ⇒ 29 |
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105 | | Register36 ⇒ 30 |
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106 | | Register37 ⇒ 31 |
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107 | | RegisterA ⇒ 32 |
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108 | | RegisterB ⇒ 33 |
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109 | | RegisterDPL ⇒ 34 |
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110 | | RegisterDPH ⇒ 35 |
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111 | | RegisterCarry ⇒ 36 (* was -1, increment as needed *) |
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112 | ]. |
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113 | |
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114 | definition physical_register_count ≝ 36. |
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115 | |
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116 | definition bitvector_of_register: Register → BitVector 6 ≝ |
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117 | λregister. |
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118 | bitvector_of_nat ? (nat_of_register register). |
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119 | |
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120 | definition eq_Register: Register → Register → bool ≝ |
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121 | λr, s: Register. |
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122 | let r_as_nat ≝ nat_of_register r in |
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123 | let s_as_nat ≝ nat_of_register s in |
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124 | eqb r_as_nat s_as_nat. |
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125 | |
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126 | axiom print_register: Register → String. |
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127 | |
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128 | (* dpm: registers for stack manipulation *) |
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129 | definition RegisterSST ≝ Register10. |
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130 | definition RegisterST0 ≝ Register02. |
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131 | definition RegisterST1 ≝ Register03. |
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132 | definition RegisterST2 ≝ Register04. |
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133 | definition RegisterST3 ≝ Register05. |
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134 | definition RegisterSTS ≝ [RegisterST0; RegisterST1; RegisterST2; RegisterST3]. |
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135 | definition RegisterSPL ≝ Register06. |
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136 | definition RegisterSPH ≝ Register07. |
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137 | definition RegisterParams: list Register ≝ |
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138 | [ Register30; Register31; Register32; Register33; |
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139 | Register34; Register35; Register36; Register37 ]. |
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140 | definition Registers ≝ |
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141 | [Register00; Register01; Register02; Register03; Register04; |
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142 | Register05; Register06; Register07; Register10; Register11; |
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143 | Register12; Register13; Register14; Register15; Register16; |
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144 | Register17; Register20; Register21; Register22; Register23; |
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145 | Register24; Register25; Register26; Register27; Register30; |
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146 | Register31; Register32; Register33; Register34; Register35; |
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147 | Register36; Register37; RegisterA; RegisterB; RegisterDPL; |
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148 | RegisterDPH; RegisterSPL; RegisterSPH; RegisterST0; RegisterST1; |
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149 | RegisterSST]. |
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150 | definition RegisterRets ≝ [RegisterDPL; RegisterDPH; Register00; Register01]. |
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151 | definition RegisterCallerSaved ≝ |
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152 | [Register00; Register01; Register02; Register03; Register04; |
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153 | Register05; Register06; Register07; Register10; Register11; |
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154 | Register12; Register13; Register14; Register15; Register16; |
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155 | Register17; Register30; Register31; Register32; Register33; |
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156 | Register34; Register35; Register36; Register37]. |
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157 | definition RegisterCalleeSaved ≝ |
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158 | [Register20; Register21; Register22; Register23; Register24; |
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159 | Register25; Register26; Register27]. |
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160 | definition RegistersForbidden ≝ |
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161 | [RegisterA; RegisterB; RegisterDPL; RegisterDPH; |
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162 | RegisterSPL; RegisterSPH; RegisterST0; RegisterST1; |
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163 | RegisterST2; RegisterST3; RegisterSST]. |
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164 | (* registers minus forbidden *) |
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165 | definition RegistersAllocatable ≝ |
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166 | [Register00; Register01; Register02; Register03; Register04; |
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167 | Register05; Register06; Register07; Register10; Register11; |
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168 | Register12; Register13; Register14; Register15; Register16; |
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169 | Register17; Register20; Register21; Register22; Register23; |
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170 | Register24; Register25; Register26; Register27; Register30; |
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171 | Register31; Register32; Register33; Register34; Register35; |
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172 | Register36; Register37]. |
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173 | |
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174 | definition register_address: Register → [[ acc_a; direct; registr ]] ≝ |
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175 | λr: Register. |
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176 | match r with |
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177 | [ Register00 ⇒ REGISTER [[ false; false; false ]] |
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178 | | Register01 ⇒ REGISTER [[ false; false; true ]] |
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179 | | Register02 ⇒ REGISTER [[ false; true; false ]] |
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180 | | Register03 ⇒ REGISTER [[ false; true; true ]] |
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181 | | Register04 ⇒ REGISTER [[ true; false; false ]] |
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182 | | Register05 ⇒ REGISTER [[ true; false; true ]] |
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183 | | Register06 ⇒ REGISTER [[ true; true; false ]] |
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184 | | Register07 ⇒ REGISTER [[ true; true; true ]] |
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185 | | RegisterA ⇒ ACC_A |
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186 | | RegisterB ⇒ DIRECT (bitvector_of_nat 8 240) |
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187 | | RegisterDPL ⇒ DIRECT (bitvector_of_nat 8 82) |
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188 | | RegisterDPH ⇒ DIRECT (bitvector_of_nat 8 83) |
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189 | | _ ⇒ DIRECT (bitvector_of_nat 8 (nat_of_register r)) |
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190 | ]. |
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191 | [*: normalize |
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192 | @ I |
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193 | ] |
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194 | qed. |
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195 | |
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196 | definition hw_register_env ≝ BitVectorTrie beval 6. |
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197 | definition empty_hw_register_env: hw_register_env ≝ Stub …. |
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198 | definition hwreg_retrieve: hw_register_env → Register → beval ≝ |
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199 | λenv,r. lookup … (bitvector_of_register r) env BVundef. |
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200 | definition hwreg_store: Register → beval → hw_register_env → hw_register_env ≝ |
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201 | λr,v,env. insert … (bitvector_of_register r) v env. |
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202 | |
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203 | record Eval: Type[0] ≝ |
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204 | { |
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205 | opaccs: OpAccs → Byte → Byte → Byte × Byte; |
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206 | op1: Op1 → Byte → Byte; |
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207 | op2: Bit → Op2 → Byte → Byte → (Byte × Bit) |
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208 | }. |
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209 | |
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210 | axiom opaccs_implementation: OpAccs → Byte → Byte → Byte × Byte. |
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211 | axiom op1_implementation: Op1 → Byte → Byte. |
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212 | axiom op2_implementation: Bit → Op2 → Byte → Byte → (Byte × Bit). |
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213 | |
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214 | definition eval: Eval ≝ |
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215 | mk_Eval opaccs_implementation |
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216 | op1_implementation |
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217 | op2_implementation. |
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