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37 | \title{On the correctness of an optimising assembler for the Intel MCS-51 microprocessor\thanks{The project CerCo acknowledges the financial support of the Future and Emerging Technologies (FET) programme within the Seventh Framework Programme for Research of the European Commission, under FET-Open grant number: 243881.}} |
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38 | \author{Dominic P. Mulligan \and Claudio Sacerdoti Coen} |
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39 | \institute{Dipartimento di Scienze dell'Informazione,\\ Universit\'a degli Studi di Bologna} |
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40 | |
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41 | \bibliographystyle{splncs03} |
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42 | |
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43 | \begin{document} |
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44 | |
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45 | \maketitle |
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46 | |
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47 | \begin{abstract} |
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48 | We present a proof of correctness, in Matita, for an optimising assembler for the MCS-51 microcontroller. |
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49 | This assembler constitutes a major component of the EU's CerCo project. |
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50 | |
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51 | The efficient expansion of pseudoinstructions---particularly jumps---into MCS-51 machine instructions is complex. |
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52 | We isolate the decision making over how jumps should be expanded from the expansion process itself as much as possible using `policies'. |
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53 | This makes the proof of correctness for the assembler significantly more straightforward. |
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54 | |
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55 | We observe that it is impossible for an optimising assembler to preserve the semantics of every assembly program. |
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56 | Assembly language programs can manipulate concrete addresses in arbitrary ways. |
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57 | Our proof strategy contains a tracking facility for `good addresses' and only programs that use good addresses have their semantics preserved under assembly. |
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58 | Our strategy offers increased flexibility over the traditional approach to proving the correctness of assemblers, wherein addresses in assembly are kept opaque and immutable. |
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59 | In particular, we may experiment with allowing the benign manipulation of addresses. |
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60 | \keywords{Verified software, CerCo (Certified Complexity), MCS-51 microcontroller, Matita proof assistant} |
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61 | \end{abstract} |
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62 | |
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63 | % ---------------------------------------------------------------------------- % |
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64 | % SECTION % |
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65 | % ---------------------------------------------------------------------------- % |
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66 | \section{Introduction} |
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67 | \label{sect.introduction} |
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68 | |
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69 | We consider the formalisation of an assembler for the Intel MCS-51 8-bit microprocessor in the Matita proof assistant~\cite{asperti:user:2007}. |
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70 | This formalisation forms a major component of the EU-funded CerCo (`Certified Complexity') project~\cite{cerco:2011}, concerning the construction and formalisation of a concrete complexity preserving compiler for a large subset of the C programming language. |
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71 | |
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72 | The MCS-51 dates from the early 1980s and is commonly called the 8051/8052. |
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73 | Despite the microprocessor's age, derivatives are still widely manufactured by a number of semiconductor foundries, with the processor being used especially in embedded systems development, where well-tested, cheap, predictable microprocessors find their niche. |
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74 | |
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75 | The MCS-51 has a relative paucity of features compared to its more modern brethren, with the lack of any caching or pipelining features meaning that timing of execution is predictable, making the MCS-51 very attractive for CerCo's ends. |
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76 | Yet---as with many things---what one hand giveth, the other taketh away, and the MCS-51's paucity of features---though an advantage in many respects---also quickly becomes a hindrance. |
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77 | In particular, the MCS-51 features a relatively minuscule series of memory spaces by modern standards. |
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78 | As a result our C compiler, to have any sort of hope of successfully compiling realistic programs for embedded devices, ought to produce `tight' machine code. |
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79 | |
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80 | In order to do this, we must solve the `branch displacement' problem---deciding how best to expand pseudojumps to labels in assembly language to machine code jumps. |
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81 | Clearly a correct but efficient strategy would be to expand all unconditional pseudojumps to the MCS-51's \texttt{LJMP} instruction, and all conditional pseudojumps to a set configuration of jumps using \texttt{LJMP} instructions; this is inefficient and a waste of valuable code memory space. |
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82 | Finding an efficient solution with this expansion process is not trivial, and is a well-known problem for those writing assemblers targetting CISC architectures (for instance, see~\cite{hyde:branch:2006}). |
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83 | |
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84 | To free the CerCo C compiler from having to consider complications relating to branch displacement, we have chosen to implement an optimising assembler, whose input language the compiler will target. |
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85 | Labels, conditional jumps to labels, a program preamble containing global data and a \texttt{MOV} instruction for moving this global data into the MCS-51's one 16-bit register all feature in our assembly language. |
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86 | We simplify the proof by assuming that all our assembly programs are pre-linked (i.e. we do not formalise a linker---this is left for future work). |
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87 | |
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88 | Further, we must make sure that the assembly process does not change the timing characteristics of an assembly program for two reasons. |
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89 | |
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90 | First, the semantics of some functions of the MCS-51, notably I/O, depend on the microprocessor's clock. |
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91 | Changing how long a particular program takes to execute can affect the semantics of a program. |
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92 | This is undesirable. |
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93 | |
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94 | Second, CerCo imposes a cost model on C programs or, more specifically, on simple blocks of instructions. |
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95 | This cost model is induced by the compilation process itself, and its non-compositional nature allows us to assign different costs to identical blocks of instructions depending on how they are compiled. |
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96 | In short, we aim to obtain a very precise costing for a program by embracing the compilation process, not ignoring it. |
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97 | This, however, complicates the proof of correctness for the compiler proper, and we must prove that both the meaning and concrete complexity characteristics of the program are preserved for every translation pass in the compiler, including the assembler. |
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98 | |
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99 | How we went about resolving this problem affected the shape of our proof of correctness for the whole assembler in a rather profound way. |
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100 | We first attempted to synthesise a solution bottom up: starting with no solution, we gradually refine a solution using the same functions that implement the jump expansion process. |
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101 | Using this technique, solutions can fail to exist, and the proof of correctness for the assembler quickly descends into a diabolical quagmire. |
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102 | |
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103 | Abandoning this attempt, we instead split the `policy'---the decision over how any particular jump should be expanded---from the implementation that actually expands assembly programs into machine code. |
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104 | Assuming the existence of a correct policy, we proved the implementation of the assembler correct. |
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105 | Further, we proved that the assembler fails to assemble an assembly program if and only if a correct policy does not exist. |
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106 | This is achieved by means of dependent types: the assembly function is total over a program, a policy and the proof that the policy is correct for that program. |
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107 | |
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108 | Policies do not exist in only a limited number of circumstances: namely, if a pseudoinstruction attempts to jump to a label that does not exist, or the program is too large to fit in code memory, even after shrinking jumps according to the policy. |
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109 | The first circumstance is an example of a serious compiler error, as an ill-formed assembly program was generated, and does not (and should not) count as a mark against the completeness of the assembler. |
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110 | |
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111 | The rest of this paper is a detailed description of our proof that is, in part, still a work in progress. |
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112 | |
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113 | % ---------------------------------------------------------------------------- % |
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114 | % SECTION % |
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115 | % ---------------------------------------------------------------------------- % |
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116 | \subsection{Overview of the paper} |
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117 | \label{subsect.overview.of.the.paper} |
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118 | In Section~\ref{sect.matita} we provide a brief overview of the Matita proof assistant for the unfamiliar reader. |
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119 | In Section~\ref{sect.the.proof} we discuss the design and implementation of the proof proper. |
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120 | In Section~\ref{sect.conclusions} we conclude. |
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121 | |
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122 | % ---------------------------------------------------------------------------- % |
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123 | % SECTION % |
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124 | % ---------------------------------------------------------------------------- % |
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125 | \section{Matita} |
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126 | \label{sect.matita} |
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127 | |
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128 | Matita is a proof assistant based on a variant of the Calculus of (Co)inductive Constructions~\cite{asperti:user:2007}. |
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129 | In particular, it features dependent types that we heavily exploit in the formalisation. |
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130 | The syntax of the statements and definitions in the paper should be self-explanatory, at least to those exposed to dependent type theory. |
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131 | We only remark the use of of `$\mathtt{?}$' or `$\mathtt{\ldots}$' for omitting single terms or sequences of terms to be inferred automatically by the system, respectively. |
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132 | Those that are not inferred are left to the user as proof obligations. |
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133 | Pairs are denoted with angular brackets, $\langle-, -\rangle$. |
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134 | |
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135 | Matita features a liberal system of coercions. |
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136 | It is possible to define a uniform coercion $\lambda x.\langle x,?\rangle$ from every type $T$ to the dependent product $\Sigma x:T.P~x$. |
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137 | The coercion opens a proof obligation that asks the user to prove that $P$ holds for $x$. |
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138 | When a coercion must be applied to a complex term (a $\lambda$-abstraction, a local definition, or a case analysis), the system automatically propagates the coercion to the sub-terms |
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139 | For instance, to apply a coercion to force $\lambda x.M : A \to B$ to have type $\forall x:A.\Sigma y:B.P~x~y$, the system looks for a coercion from $M: B$ to $\Sigma y:B.P~x~y$ in a context augmented with $x:A$. |
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140 | This is significant when the coercion opens a proof obligation, as the user will be presented with multiple, but simpler proof obligations in the correct context. |
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141 | In this way, Matita supports the ``Russell'' proof methodology developed by Sozeau in~\cite{sozeau:subset:2006}, with an implementation that is lighter and more tightly integrated with the system than that of Coq. |
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142 | |
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143 | % ---------------------------------------------------------------------------- % |
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144 | % SECTION % |
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145 | % ---------------------------------------------------------------------------- % |
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146 | \section{The proof} |
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147 | \label{sect.the.proof} |
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148 | |
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149 | % ---------------------------------------------------------------------------- % |
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150 | % SECTION % |
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151 | % ---------------------------------------------------------------------------- % |
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152 | |
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153 | \subsection{Machine code semantics} |
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154 | \label{subsect.machine.code.semantics} |
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155 | |
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156 | Our emulator centres around a \texttt{Status} record, describing the microprocessor's state. |
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157 | This record contains fields corresponding to the microprocessor's program counter, registers, and so on. |
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158 | At the machine code level, code memory is implemented as a compact trie of bytes addressed by the program counter. |
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159 | We parameterise \texttt{Status} records by this representation as a few technical tasks manipulating statuses are made simpler using this approach, as well as permitting a modicum of abstraction. |
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160 | |
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161 | We may execute a single step of a machine code program using the \texttt{execute\_1} function, which returns an updated \texttt{Status}: |
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162 | \begin{lstlisting} |
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163 | definition execute_1: $\forall$cm. Status cm $\rightarrow$ Status cm := $\ldots$ |
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164 | \end{lstlisting} |
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165 | %The function \texttt{execute} allows one to execute an arbitrary, but fixed (due to Matita's normalisation requirement) number of steps of a program. |
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166 | The function \texttt{execute\_1} closely matches the operation of the MCS-51 hardware, as described by a Siemen's manufacturer's data sheet (specifically, this one~\cite{siemens:2011}). |
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167 | We first fetch, using the program counter, from code memory the first byte of the instruction to be executed, decoding the resulting opcode, fetching more bytes as is necessary. |
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168 | Decoded instructions are represented as an inductive type, where $\llbracket - \rrbracket$ denotes a fixed-length vector: |
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169 | \begin{lstlisting} |
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170 | inductive preinstruction (A: Type[0]): Type[0] := |
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171 | | ADD: $\llbracket$acc_a$\rrbracket$ → $\llbracket$registr; direct; indirect; data$\rrbracket$ $\rightarrow$ preinstruction A |
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172 | | INC: $\llbracket$ acc_a; registr; direct; indirect; dptr$\rrbracket$ $\rightarrow$ preinstruction A |
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173 | | JB: $\llbracket$bit_addr$\rrbracket$ $\rightarrow$ A $\rightarrow$ preinstruction A |
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174 | | ... |
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175 | |
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176 | inductive instruction: Type[0] := |
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177 | | LCALL: $\llbracket$addr16$\rrbracket$ $\rightarrow$ instruction |
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178 | | AJMP: $\llbracket$addr11$\rrbracket$ $\rightarrow$ instruction |
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179 | | RealInstruction: preinstruction $\llbracket$relative$\rrbracket$ $\rightarrow$ instruction. |
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180 | | ... |
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181 | \end{lstlisting} |
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182 | Here, we use dependent types to provide a precise typing for instructions, specifying in their type the permitted addressing modes that their arguments can belong to. |
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183 | The parameterised type $A$ of \texttt{preinstruction} represents the addressing mode for conditional jumps; in \texttt{instruction} we fix this type to be a relative offset in the constructor \texttt{RealInstruction}. |
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184 | |
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185 | Once decoded, execution proceeds by a case analysis on the decoded instruction, following the operation of the hardware. |
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186 | For example, the \texttt{DEC} instruction (`decrement') is implemented as follows: |
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187 | |
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188 | \begin{lstlisting} |
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189 | | DEC addr $\Rightarrow$ |
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190 | let s := add_ticks1 s in |
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191 | let $\langle$result, flags$\rangle$ := sub_8_with_carry (get_arg_8 $\ldots$ s true addr) |
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192 | (bitvector_of_nat 8 1) false in |
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193 | set_arg_8 $\ldots$ s addr result |
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194 | \end{lstlisting} |
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195 | |
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196 | Here, \texttt{add\_ticks1} models the incrementing of the internal clock of the microprocessor. |
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197 | |
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198 | % ---------------------------------------------------------------------------- % |
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199 | % SECTION % |
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200 | % ---------------------------------------------------------------------------- % |
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201 | |
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202 | \subsection{Assembly code semantics} |
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203 | \label{subsect.assembly.code.semantics} |
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204 | |
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205 | An assembly program is a list of potentially labelled pseudoinstructions, bundled with a preamble consisting of a list of symbolic names for locations in data memory (i.e. global variables). |
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206 | Pseudoinstructions are implemented as an inductive type: |
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207 | \begin{lstlisting} |
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208 | inductive pseudo_instruction: Type[0] := |
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209 | | Instruction: preinstruction Identifier $\rightarrow$ pseudo_instruction |
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210 | ... |
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211 | | Jmp: Identifier $\rightarrow$ pseudo_instruction |
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212 | | Call: Identifier $\rightarrow$ pseudo_instruction |
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213 | | Mov: $\llbracket$dptr$\rrbracket$ $\rightarrow$ Identifier $\rightarrow$ pseudo_instruction. |
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214 | \end{lstlisting} |
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215 | The pseudoinstructions \texttt{Jmp}, \texttt{Call} and \texttt{Mov} are generalisations of machine code unconditional jumps, calls and move instructions respectively, all of whom act on labels, as opposed to concrete memory addresses. |
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216 | Similarly, conditional jumps can now only jump to labels, as is implied by the first constructor of the type above. |
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217 | All other object code instructions are available at the assembly level, with the exception of those that appeared in the \texttt{instruction} type, such as \texttt{ACALL} and \texttt{LJMP}. |
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218 | These are jumps and calls to absolute addresses, which we do not wish to allow at the assembly level. |
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219 | |
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220 | Execution of pseudoinstructions is a function from \texttt{PseudoStatus} to \texttt{PseudoStatus}. |
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221 | Both \texttt{Status} and \texttt{PseudoStatus} are instances of a more general type parameterised over the representation of code memory. |
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222 | The more general type is crucial for sharing the majority of the semantics of the two languages. |
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223 | |
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224 | Emulation for pseudoinstructions is handled by \texttt{execute\_1\_pseudo\_instruction}: |
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225 | \begin{lstlisting} |
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226 | definition execute_1_pseudo_instruction: |
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227 | (Word $\rightarrow$ nat $\times$ nat) $\rightarrow$ $\forall$cm. PseudoStatus cm $\rightarrow$ PseudoStatus cm := $\ldots$ |
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228 | \end{lstlisting} |
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229 | Notice, here, that the emulation function for assembly programs takes an additional argument over \texttt{execute\_1}. |
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230 | This is a function that maps program counters (at the assembly level) to pairs of natural numbers representing the number of clock ticks that the pseudoinstruction needs to execute, post expansion. |
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231 | We call this function a \emph{costing}, and note that the costing is induced by the particular strategy we use to expand pseudoinstructions. |
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232 | If we change how we expand conditional jumps to labels, for instance, then the costing needs to change, hence \texttt{execute\_1\_pseudo\_instruction}'s parametricity in the costing. |
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233 | |
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234 | The costing returns \emph{pairs} of natural numbers because, in the case of expanding conditional jumps to labels, the expansion of the `true branch' and `false branch' may differ in execution time. |
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235 | The \texttt{add\_ticks1} function, which we have already seen used to increment the machine clock above, is determined for the assembly language from the costing function. |
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236 | |
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237 | Execution proceeds by first fetching from pseudo-code memory using the program counter---treated as an index into the pseudoinstruction list. |
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238 | No decoding is required. |
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239 | We then proceed by case analysis over the pseudoinstruction, reusing the code for object code for all instructions present in the MCS-51's instruction set. |
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240 | For all newly introduced pseudoinstructions, we simply translate labels to concrete addresses before behaving as a `real' instruction. |
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241 | |
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242 | In contrast to other approaches, we do not perform any kind of symbolic execution, wherein data is the disjoint union of bytes and addresses, with addresses kept opaque and immutable. |
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243 | Labels are immediately translated to concrete addresses, and registers and memory locations only ever contain bytes, never labels. |
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244 | As a consequence, we allow the programmer to mangle, change and generally adjust addresses as they want, under the proviso that the translation process may not be able to preserve the semantics of programs that do this. |
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245 | This will be further discussed in Subsection~\ref{subsect.total.correctness.for.well.behaved.assembly.programs}. |
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246 | |
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247 | % ---------------------------------------------------------------------------- % |
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248 | % SECTION % |
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249 | % ---------------------------------------------------------------------------- % |
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250 | |
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251 | \subsection{The assembler} |
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252 | \label{subsect.the.assembler} |
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253 | |
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254 | Conceptually the assembler works in two passes. |
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255 | The first pass expands pseudoinstructions into a list of machine code instructions using the function \texttt{expand\_pseudo\_instruction}. |
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256 | The second pass encodes as a list of bytes the expanded instruction list by mapping the function \texttt{assembly1} across the list, and then flattening. |
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257 | \begin{displaymath} |
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258 | [\mathtt{P_1}, \ldots \mathtt{P_n}] \xrightarrow{\left(\mathtt{P_i} \xrightarrow{\mbox{\fontsize{7}{9}\selectfont$\mathtt{expand\_pseudo\_instruction}$}} \mathtt{[I^1_i, \ldots I^q_i]} \xrightarrow{\mbox{\fontsize{7}{9}\selectfont$\mathtt{~~~~~~~~assembly1^{*}~~~~~~~~}$}} \mathtt{[0110]}\right)^{*}} \mathtt{[010101]} |
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259 | \end{displaymath} |
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260 | The most complex of the two passes is the first, which expands pseudoinstructions and must perform the task of branch displacement~\cite{hyde:branch:2006}. |
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261 | The function \texttt{assembly\_1\_pseudo\_instruction} used in the body of the paper is essentially the composition of the two passes. |
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262 | |
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263 | The branch displacement problems consists of the problem of expanding pseudojumps into their concrete counterparts, preferably as efficiently as possible. |
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264 | For instance, the MCS-51 features three unconditional jump instructions: \texttt{LJMP} and \texttt{SJMP}---`long jump' and `short jump' respectively---and an 11-bit oddity of the MCS-51, \texttt{AJMP}. |
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265 | Each of these three instructions expects arguments in different sizes and behaves in markedly different ways: \texttt{SJMP} may only perform a `local jump'; \texttt{LJMP} may jump to any address in the MCS-51's memory space and \texttt{AJMP} may jump to any address in the current memory page. |
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266 | Consequently, the size of each opcode is different, and to squeeze as much code as possible into the MCS-51's limited code memory, the smallest possible opcode that will suffice should be selected. |
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267 | |
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268 | Similarly, a conditional pseudojump must be translated potentially into a configuration of machine code instructions, depending on the distance to the jump's target. |
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269 | For example, to translate a jump to a label, a single conditional jump pseudoinstruction may be translated into a block of three real instructions as follows (here, \texttt{JZ} is `jump if accumulator is zero'): |
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270 | {\small{ |
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271 | \begin{displaymath} |
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272 | \begin{array}{r@{\quad}l@{\;\;}l@{\qquad}c@{\qquad}l@{\;\;}l} |
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273 | & \mathtt{JZ} & \mathtt{label} & & \mathtt{JZ} & \text{size of \texttt{SJMP} instruction} \\ |
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274 | & \ldots & & \text{translates to} & \mathtt{SJMP} & \text{size of \texttt{LJMP} instruction} \\ |
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275 | \mathtt{label:} & \mathtt{MOV} & \mathtt{A}\;\;\mathtt{B} & \Longrightarrow & \mathtt{LJMP} & \text{address of \textit{label}} \\ |
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276 | & & & & \ldots & \\ |
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277 | & & & & \mathtt{MOV} & \mathtt{A}\;\;\mathtt{B} |
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278 | \end{array} |
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279 | \end{displaymath}}} |
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280 | Here, if \texttt{JZ} fails, we fall through to the \texttt{SJMP} which jumps over the \texttt{LJMP}. |
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281 | Naturally, if \texttt{label} is `close enough', a conditional jump pseudoinstruction is mapped directly to a conditional jump machine instruction; the above translation only applies if \texttt{label} is not sufficiently local. |
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282 | |
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283 | In order to implement branch displacement it is impossible to really make the \texttt{expand\_pseudo\_instruction} function completely independent of the encoding function. |
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284 | This is due to branch displacement requiring the distance in bytes of the target of the jump. |
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285 | Moreover the standard solutions for solving the branch displacement problem find their solutions iteratively, by either starting from a solution where all jumps are long, and shrinking them when possible, or starting from a state where all jumps are short and increasing their length as needed. |
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286 | Proving the correctness of such algorithms is already quite involved and the correctness of the assembler as a whole does not depend on the `quality' of the solution found to a branch displacement problem. |
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287 | For this reason, we try to isolate the computation of a branch displacement problem from the proof of correctness for the assembler by parameterising our \texttt{expand\_pseudo\_instruction} by a `policy'. |
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288 | |
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289 | \begin{lstlisting} |
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290 | definition expand_pseudo_instruction: |
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291 | $\forall$lookup_labels: Identifier $\rightarrow$ Word. |
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292 | $\forall$sigma: Word $\rightarrow$ Word. |
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293 | $\forall$policy: Word $\rightarrow$ bool. |
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294 | $\forall$ppc: Word. |
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295 | $\forall$lookup_datalabels: Identifier $\rightarrow$ Word. |
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296 | $\forall$pi: pseudo_instruction. |
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297 | list instruction := ... |
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298 | \end{lstlisting} |
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299 | Here, the functions \texttt{lookup\_labels} and \texttt{lookup\_datalabels} are the functions that map labels and datalabels to program counters respectively, both of them used in the semantics of assembly. |
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300 | The input \texttt{pi} is the pseudoinstruction to be expanded and is found at address \texttt{ppc} in the assembly program. |
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301 | The policy is defined using the two functions \texttt{sigma} and \texttt{policy}, of which \texttt{sigma} is the most interesting. |
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302 | The function \texttt{sigma} maps pseudo program counters to program counters: the encoding of the expansion of the pseudoinstruction found at address \texttt{a} in the assembly code should be placed into code memory at address \texttt{sigma(a)}. |
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303 | Of course this is possible only if the policy is correct, which means that the encoding of consecutive assembly instructions must be consecutive in code memory. |
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304 | \begin{displaymath} |
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305 | \texttt{sigma}(\texttt{ppc} + 1) = \texttt{pc} + \texttt{current\_instruction\_size} |
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306 | \end{displaymath} |
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307 | Here, \texttt{current\_instruction\_size} is the size in bytes of the encoding of the expanded pseudoinstruction found at \texttt{ppc}. |
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308 | Note that the entanglement we hinted at is only partially solved in this way: the assembler code can ignore the implementation details of the algorithm that finds a policy; |
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309 | however, the algorithm that finds a policy must know the exact behaviour of the assembly program because it needs to predict the way the assembly will expand and encode pseudoinstructions, once fed with a policy. |
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310 | A companion submission to this one~\cite{boender:correctness:2012} certifies an algorithm that finds branch displacement policies for the assembler described in this paper. |
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311 | |
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312 | The \texttt{expand\_pseudo\_instruction} function uses the \texttt{sigma} map to determine the size of jump required when expanding pseudojumps, computing the jump size by examining the size of the differences between program counters. |
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313 | For instance, if at address \texttt{ppc} in the assembly program we found \texttt{Jmp l} such that \texttt{lookup\_labels l = a}, if the offset \texttt{d = sigma(a) - sigma(ppc + 1)} is such that \texttt{d} $< 128$ then \texttt{Jmp l} is normally translated to the best local solution, the short jump \texttt{SJMP d}. |
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314 | A global best solution to the branch displacement problem, however, is not always made of locally best solutions. |
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315 | Therefore, in some circumstances, it is necessary to force the assembler to expand jumps into larger ones. |
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316 | This is achieved by the \texttt{policy} function: if \texttt{policy ppc = true} then a \texttt{Jmp l} at address \texttt{ppc} is always translated to a long jump. |
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317 | An essentially identical mechanism exists for call instructions. |
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318 | |
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319 | % ---------------------------------------------------------------------------- % |
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320 | % SECTION % |
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321 | % ---------------------------------------------------------------------------- % |
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322 | \subsection{Correctness of the assembler with respect to fetching} |
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323 | \label{subsect.total.correctness.of.the.assembler} |
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324 | Using our policies, we now work toward proving the total correctness of the assembler. |
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325 | By `total correctness', we mean that the assembly process never fails when provided with a correct policy and that the process does not change the semantics of a certain class of well behaved assembly programs. |
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326 | |
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327 | The aim of this section is to prove the following informal statement: when we fetch an assembly pseudoinstruction \texttt{I} at address \texttt{ppc}, then we can fetch the expanded pseudoinstruction(s) \texttt{[J1, \ldots, Jn] = fetch\_pseudo\_instruction \ldots\ I\ ppc} from \texttt{sigma(ppc)} in the code memory obtained by loading the assembled object code. |
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328 | This constitutes the first major step in the proof of correctness of the assembler, the next one being the simulation of \texttt{I} by \texttt{[J1, \ldots, Jn]} (see Subsection~\ref{subsect.total.correctness.for.well.behaved.assembly.programs}). |
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329 | |
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330 | The \texttt{assembly} function is given a Russell type (slightly simplified here): |
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331 | \begin{lstlisting} |
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332 | definition assembly: |
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333 | $\forall$p: pseudo_assembly_program. |
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334 | $\forall$sigma: Word $\rightarrow$ Word. |
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335 | $\forall$policy: Word $\rightarrow$ bool. |
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336 | $\Sigma$res:list Byte $\times$ (BitVectorTrie costlabel 16). |
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337 | sigma_meets_specification p sigma policy $\rightarrow$ |
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338 | let $\langle$preamble, instr_list$\rangle$ := p in |
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339 | |instr_list| < 2^16 $\rightarrow$ |
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340 | let $\langle$assembled,costs$\rangle$ := res in |
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341 | $\forall$ppc. $\forall$ppc_ok:nat_of_bitvector $\ldots$ ppc < |instr_list|. |
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342 | let $\langle$pi,newppc$\rangle$ := fetch_pseudo_instruction instr_list ppc ppc_ok in |
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343 | let $\langle$l,a$\rangle$ := assembly_1_pseudoinstruction $\ldots$ sigma policy ppc $\ldots$ pi in |
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344 | $\forall$j:nat. j < |a| |
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345 | nth j a = nth (add $\ldots$ (sigma ppc) (bitvector_of_nat ? j))) assembled |
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346 | \end{lstlisting} |
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347 | In plain words, the type of assembly states the following. |
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348 | Suppose we are given a policy that is correct for the program we are assembling, and suppose the program to be assembled is fully addressable by a 16-bit word. |
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349 | Then if we fetch from the pseudo program counter \texttt{ppc} we get a pseudoinstruction \texttt{pi} and a new pseudo program counter \texttt{ppc}. |
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350 | Further, assembling the pseudoinstruction \texttt{pi} results in a list of bytes, \texttt{a}. |
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351 | Then, indexing into this list with any natural number \texttt{j} less than the length of \texttt{a} gives the same result as indexing into \texttt{assembled} with \texttt{sigma(ppc)} (the program counter pointing to the start of the expansion in \texttt{assembled}) plus \texttt{j}. |
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352 | |
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353 | Essentially the lemma above states that the \texttt{assembly} function correctly expands pseudoinstructions, and that the expanded instruction reside consecutively in memory. |
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354 | This result is lifted from lists of bytes into a result on tries of bytes (i.e. code memories), using an additional lemma: \texttt{assembly\_ok}. |
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355 | |
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356 | Lemma \texttt{fetch\_assembly} establishes that the \texttt{fetch} and \texttt{assembly1} functions interact correctly. |
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357 | The \texttt{fetch} function, as its name implies, fetches the instruction indexed by the program counter in the code memory, while \texttt{assembly1} maps a single instruction to its byte encoding: |
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358 | \begin{lstlisting} |
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359 | lemma fetch_assembly: |
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360 | $\forall$pc: Word. |
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361 | $\forall$i: instruction. |
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362 | $\forall$code_memory: BitVectorTrie Byte 16. |
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363 | $\forall$assembled: list Byte. |
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364 | assembled = assembly1 i $\rightarrow$ |
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365 | let len := length $\ldots$ assembled in |
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366 | let pc_plus_len := add $\ldots$ pc (bitvector_of_nat $\ldots$ len) in |
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367 | encoding_check code_memory pc pc_plus_len assembled $\rightarrow$ |
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368 | let $\langle$instr, pc', ticks$\rangle$ := fetch code_memory pc in |
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369 | instr = i $\wedge$ ticks = (ticks_of_instruction instr) $\wedge$ pc' = pc_plus_len. |
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370 | \end{lstlisting} |
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371 | In particular, we read \texttt{fetch\_assembly} as follows. |
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372 | Given an instruction, \texttt{i}, we first assemble the instruction to obtain \texttt{assembled}, checking that the assembled instruction was stored in code memory correctly. |
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373 | Fetching from code memory, we obtain a tuple consisting of the instruction, new program counter, and the number of ticks this instruction will take to execute. |
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374 | We finally check that the fetched instruction is the same instruction that we began with, and the number of ticks this instruction will take to execute is the same as the result returned by a lookup function, \texttt{ticks\_of\_instruction}, devoted to tracking this information. |
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375 | Or, in plainer words, assembling and then immediately fetching again gets you back to where you started. |
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376 | |
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377 | Lemma \texttt{fetch\_assembly\_pseudo} (slightly simplified, here) is obtained by composition of \texttt{expand\_pseudo\_instruction} and \texttt{assembly\_1\_pseudoinstruction}: |
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378 | \begin{lstlisting} |
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379 | lemma fetch_assembly_pseudo: |
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380 | $\forall$program: pseudo_assembly_program. |
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381 | $\forall$sigma: Word $\rightarrow$ Word. |
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382 | $\forall$policy: Word $\rightarrow$ bool. |
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383 | $\forall$ppc. |
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384 | $\forall$code_memory. |
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385 | let $\langle$preamble, instr_list$\rangle$ := program in |
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386 | let pi := $\pi_1$ (fetch_pseudo_instruction instr_list ppc) in |
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387 | let pc := sigma ppc in |
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388 | let instrs := expand_pseudo_instruction $\ldots$ sigma policy ppc $\ldots$ pi in |
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389 | let $\langle$l, a$\rangle$ := assembly_1_pseudoinstruction $\ldots$ sigma policy ppc $\ldots$ pi in |
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390 | let pc_plus_len := add $\ldots$ pc (bitvector_of_nat $\ldots$ l) in |
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391 | encoding_check code_memory pc pc_plus_len a $\rightarrow$ |
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392 | fetch_many code_memory pc_plus_len pc instructions. |
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393 | \end{lstlisting} |
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394 | Here, \texttt{l} is the number of machine code instructions the pseudoinstruction at hand has been expanded into. |
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395 | We assemble a single pseudoinstruction with \texttt{assembly\_1\_pseudoinstruction}, which internally calls \texttt{expand\_pseudo\_instruction}. |
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396 | The function \texttt{fetch\_many} fetches multiple machine code instructions from code memory and performs some routine checks. |
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397 | |
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398 | Intuitively, Lemma \texttt{fetch\_assembly\_pseudo} can be read as follows. |
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399 | Suppose we expand the pseudoinstruction at \texttt{ppc} with the policy decision \texttt{sigma}, obtaining the list of machine code instructions \texttt{instrs}. |
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400 | Suppose we also assemble the pseudoinstruction at \texttt{ppc} to obtain \texttt{a}, a list of bytes. |
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401 | Then, we check with \texttt{fetch\_many} that the number of machine instructions that were fetched matches the number of instruction that \texttt{expand\_pseudo\_instruction} expanded. |
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402 | |
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403 | The final lemma in this series is \texttt{fetch\_assembly\_pseudo2} that combines the Lemma \texttt{fetch\_assembly\_pseudo} with the correctness of the functions that load object code into the processor's memory. |
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404 | Again, we slightly simplify: |
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405 | \begin{lstlisting} |
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406 | lemma fetch_assembly_pseudo2: |
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407 | $\forall$program. |
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408 | $\forall$sigma. |
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409 | $\forall$policy. |
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410 | $\forall$sigma_meets_specification. |
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411 | $\forall$ppc. |
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412 | let $\langle$preamble, instr_list$\rangle$ := program in |
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413 | let $\langle$labels, costs$\rangle$ := create_label_cost_map instr_list in |
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414 | let $\langle$assembled, costs'$\rangle$ := $\pi_1$ $\ldots$ (assembly program sigma policy) in |
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415 | let cmem := load_code_memory assembled in |
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416 | let $\langle$pi, newppc$\rangle$ := fetch_pseudo_instruction instr_list ppc in |
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417 | let instructions := expand_pseudo_instruction $\ldots$ sigma ppc $\ldots$ pi in |
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418 | fetch_many cmem (sigma newppc) (sigma ppc) instructions. |
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419 | \end{lstlisting} |
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420 | |
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421 | Here we use $\pi_1 \ldots$ to eject out the existential witness from the Russell-typed function \texttt{assembly}. |
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422 | |
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423 | We read \texttt{fetch\_assembly\_pseudo2} as follows. |
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424 | Suppose we are able to successfully assemble an assembly program using \texttt{assembly} and produce a code memory, \texttt{cmem}. |
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425 | Then, fetching a pseudoinstruction from the pseudo-code memory at address \texttt{ppc} corresponds to fetching a sequence of instructions from the real code memory using \texttt{sigma} to expand pseudoinstructions. |
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426 | The fetched sequence corresponds to the expansion, according to \texttt{sigma}, of the pseudoinstruction. |
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427 | |
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428 | At first, the lemmas appears to immediately imply the correctness of the assembler. |
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429 | However, this property is \emph{not} strong enough to establish that the semantics of an assembly program has been preserved by the assembly process since it does not establish the correspondence between the semantics of a pseudoinstruction and that of its expansion. |
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430 | In particular, the two semantics differ on instructions that \emph{could} directly manipulate program addresses. |
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431 | |
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432 | % ---------------------------------------------------------------------------- % |
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433 | % SECTION % |
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434 | % ---------------------------------------------------------------------------- % |
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435 | \subsection{Total correctness for `well behaved' assembly programs} |
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436 | \label{subsect.total.correctness.for.well.behaved.assembly.programs} |
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437 | |
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438 | The traditional approach to verifying the correctness of an assembler is to treat memory addresses as opaque structures that cannot be modified. |
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439 | Memory is represented as a map from opaque addresses to the disjoint union of data and opaque addresses---addresses are kept opaque to prevent their possible `semantics breaking' manipulation by assembly programs: |
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440 | \begin{displaymath} |
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441 | \mathtt{Mem} : \mathtt{Addr} \rightarrow \mathtt{Bytes} + \mathtt{Addr} \qquad \llbracket - \rrbracket : \mathtt{Instr} \rightarrow \mathtt{Mem} \rightarrow \mathtt{option\ Mem} |
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442 | \end{displaymath} |
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443 | The semantics of a pseudoinstruction, $\llbracket - \rrbracket$, is given as a possibly failing function from pseudoinstructions and memory spaces to new memory spaces. |
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444 | The semantic function proceeds by case analysis over the operands of a given instruction, failing if either operand is an opaque address, or otherwise succeeding, updating memory. |
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445 | \begin{gather*} |
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446 | \llbracket \mathtt{ADD\ @A1\ @A2} \rrbracket^\mathtt{M} = \begin{cases} |
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447 | \mathtt{Byte\ b1},\ \mathtt{Byte\ b2} & \rightarrow \mathtt{Some}(\mathtt{M}\ \text{with}\ \mathtt{b1} + \mathtt{b2}) \\ |
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448 | -,\ \mathtt{Addr\ a} & \rightarrow \mathtt{None} \\ |
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449 | \mathtt{Addr\ a},\ - & \rightarrow \mathtt{None} |
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450 | \end{cases} |
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451 | \end{gather*} |
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452 | In contrast, in this paper we take a different approach. |
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453 | We trace memory locations (and, potentially, registers) that contain memory addresses. |
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454 | We then prove that only those assembly programs that use addresses in `safe' ways have their semantics preserved by the assembly process---a sort of dynamic type system sitting atop memory. |
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455 | |
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456 | We believe that this approach is more flexible when compared to the traditional approach, as in principle it allows us to introduce some permitted \emph{benign} manipulations of addresses that the traditional approach, using opaque addresses, cannot handle, therefore expanding the set of input programs that can be assembled correctly. |
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457 | This approach, of using real addresses coupled with a weak, dynamic typing system sitting atop of memory, is similar to one taken by Huth \emph{et al}~\cite{tuch:types:2007}, for reasoning about low-level C code. |
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458 | |
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459 | Our analogue of the semantic function above is then merely a wrapper around the function that implements the semantics of machine code, paired with a function that keeps track of addresses. |
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460 | This permits a large amount of code reuse, as the semantics of pseudo- and machine code are essentially shared. |
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461 | The only thing that changes at the assembly level is the presence of the new tracking function. |
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462 | |
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463 | However, with this approach we must detect (at run time) programs that manipulate addresses in well behaved ways, according to some approximation of well-behavedness. |
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464 | We use an \texttt{internal\_pseudo\_address\_map} to trace addresses of code memory addresses in internal RAM: |
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465 | \begin{lstlisting} |
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466 | definition internal_pseudo_address_map := |
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467 | list ((BitVector 8) $\times$ (bool $\times$ Word)) $\times$ (option (bool $\times$ Word)). |
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468 | \end{lstlisting} |
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469 | The implementation of \texttt{internal\_pseudo\_address\_map} is complicated by some peculiarities of the MCS-51's instruction set. |
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470 | Note here that all addresses are 16 bit words, but are stored (and manipulated) as 8 bit bytes. |
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471 | All \texttt{MOV} instructions in the MCS-51 must use the accumulator \texttt{A} as an intermediary, moving a byte at a time. |
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472 | The second component of \texttt{internal\_pseudo\_address\_map} therefore states whether the accumulator currently holds a piece of an address, and if so, whether it is the upper or lower byte of the address (using the boolean flag) complete with the corresponding, source address in full. |
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473 | The first component, on the other hand, performs a similar task for the rest of external RAM. |
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474 | Again, we use a boolean flag to describe whether a byte is the upper or lower component of a 16-bit address. |
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475 | |
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476 | The \texttt{low\_internal\_ram\_of\_pseudo\_low\_internal\_ram} function converts the lower internal RAM of a \texttt{PseudoStatus} into the lower internal RAM of a \texttt{Status}. |
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477 | A similar function exists for high internal RAM. |
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478 | Note that both RAM segments are indexed using addresses 7-bits long. |
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479 | The function is currently axiomatised, and an associated set of axioms prescribe the behaviour of the function: |
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480 | \begin{lstlisting} |
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481 | axiom low_internal_ram_of_pseudo_low_internal_ram: |
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482 | internal_pseudo_address_map$\rightarrow$BitVectorTrie Byte 7$\rightarrow$BitVectorTrie Byte 7. |
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483 | \end{lstlisting} |
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484 | |
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485 | Next, we are able to translate \texttt{PseudoStatus} records into \texttt{Status} records using \texttt{status\_of\_pseudo\_status}. |
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486 | Translating a \texttt{PseudoStatus}'s code memory requires we expand pseudoinstructions and then assemble to obtain a trie of bytes. |
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487 | This never fails, provided that our policy is correct: |
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488 | \begin{lstlisting} |
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489 | definition status_of_pseudo_status: |
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490 | internal_pseudo_address_map $\rightarrow$ $\forall$pap. $\forall$ps: PseudoStatus pap. |
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491 | $\forall$sigma: Word $\rightarrow$ Word. $\forall$policy: Word $\rightarrow$ bool. |
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492 | Status (code_memory_of_pseudo_assembly_program pap sigma policy) |
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493 | \end{lstlisting} |
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494 | |
---|
495 | The \texttt{next\_internal\_pseudo\_address\_map} function is responsible for run time monitoring of the behaviour of assembly programs, in order to detect well behaved ones. |
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496 | It returns a map that traces memory addresses in internal RAM after execution of the next pseudoinstruction, failing when the instruction tampers with memory addresses in unanticipated (but potentially correct) ways. |
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497 | It thus decides the membership of a strict subset of the set of well behaved programs. |
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498 | \begin{lstlisting} |
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499 | definition next_internal_pseudo_address_map: internal_pseudo_address_map |
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500 | $\rightarrow$ PseudoStatus $\rightarrow$ option internal_pseudo_address_map |
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501 | \end{lstlisting} |
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502 | Note, if we wished to allow `benign manipulations' of addresses, it would be this function that needs to be changed. |
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503 | |
---|
504 | The function \texttt{ticks\_of0} computes how long---in clock cycles---a pseudoinstruction will take to execute when expanded in accordance with a given policy. |
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505 | The function returns a pair of natural numbers, needed for recording the execution times of each branch of a conditional jump. |
---|
506 | \begin{lstlisting} |
---|
507 | definition ticks_of0: |
---|
508 | pseudo_assembly_program $\rightarrow$ (Word $\rightarrow$ Word) $\rightarrow$ (Word $\rightarrow$ bool) $\rightarrow$ Word $\rightarrow$ |
---|
509 | pseudo_instruction $\rightarrow$ nat $\times$ nat := $\ldots$ |
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510 | \end{lstlisting} |
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511 | An additional function, \texttt{ticks\_of}, is merely a wrapper around this function. |
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512 | |
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513 | Finally, we are able to state and prove our main theorem. |
---|
514 | This relates the execution of a single assembly instruction and the execution of (possibly) many machine code instructions, as long as we are able to track memory addresses properly: |
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515 | \begin{lstlisting} |
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516 | theorem main_thm: |
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517 | $\forall$M, M': internal_pseudo_address_map. |
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518 | $\forall$program: pseudo_assembly_program. |
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519 | let $\langle$preamble, instr_list$\rangle$ := program in |
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520 | $\forall$is_well_labelled: is_well_labelled_p instr_list. |
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521 | $\forall$sigma: Word $\rightarrow$ Word. |
---|
522 | $\forall$policy: Word $\rightarrow$ bool. |
---|
523 | $\forall$sigma_meets_specification. |
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524 | $\forall$ps: PseudoStatus program. |
---|
525 | $\forall$program_counter_in_bounds. |
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526 | next_internal_pseudo_address_map M program ps = Some $\ldots$ M' $\rightarrow$ |
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527 | $\exists$n. execute n $\ldots$ (status_of_pseudo_status M $\ldots$ ps sigma policy) = |
---|
528 | status_of_pseudo_status M' $\ldots$ (execute_1_pseudo_instruction |
---|
529 | (ticks_of program sigma policy) program ps) sigma policy. |
---|
530 | \end{lstlisting} |
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531 | The statement is standard for forward simulation, but restricted to \texttt{PseudoStatuses} \texttt{ps} whose next instruction to be executed is well-behaved with respect to the \texttt{internal\_pseudo\_address\_map} \texttt{M}. |
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532 | Further, we explicitly require proof that our policy is correct and the pseudo program counter lies within the bounds of the program. |
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533 | Theorem \texttt{main\_thm} establishes the total correctness of the assembly process and can simply be lifted to the forward simulation of an arbitrary number of well behaved steps on the assembly program. |
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534 | |
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535 | % ---------------------------------------------------------------------------- % |
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536 | % SECTION % |
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537 | % ---------------------------------------------------------------------------- % |
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538 | \section{Conclusions} |
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539 | \label{sect.conclusions} |
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540 | |
---|
541 | We are proving the total correctness of an assembler for MCS-51 assembly language. |
---|
542 | In particular, our assembly language features labels, arbitrary conditional and unconditional jumps to labels, global data and instructions for moving this data into the MCS-51's single 16-bit register. |
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543 | Expanding these pseudoinstructions into machine code instructions is not trivial, and the proof that the assembly process is `correct', in that the semantics of a subset of assembly programs are not changed is complex. |
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544 | |
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545 | The formalisation is a key component of the CerCo project, which aims to produce a verified concrete complexity preserving compiler for a large subset of the C programming language. |
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546 | The verified assembler, complete with the underlying formalisation of the semantics of MCS-51 machine code, will form the bedrock layer upon which the rest of the CerCo project will build its verified compiler platform. |
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547 | |
---|
548 | It is interesting to compare our work to an `industrial grade' assembler for the MCS-51: SDCC~\cite{sdcc:2011}. |
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549 | SDCC is the only open source C compiler that targets the MCS-51 instruction set. |
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550 | It appears that all pseudojumps in SDCC assembly are expanded to \texttt{LJMP} instructions, the worst possible jump expansion policy from an efficiency point of view. |
---|
551 | Note that this policy is the only possible policy \emph{in theory} that can preserve the semantics of an assembly program during the assembly process. |
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552 | However, this comes at the expense of assembler completeness: the generated program may be too large to fit into code memory. |
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553 | In this respect, there is a trade-off between the completeness of the assembler and the efficiency of the assembled program. |
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554 | The definition and proof of a terminating, correct jump expansion policy is described in a companion publication to this one~\cite{boender:correctness:2012}. |
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555 | |
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556 | Aside from their application in verified compiler projects such as CerCo, CompCert~\cite{leroy:formally:2009} and CompCertTSO~\cite{sevcik:relaxed-memory:2011}, verified assemblers such as ours could also be applied to the verification of operating system kernels. |
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557 | Of particular note is the verified seL4 kernel~\cite{klein:sel4:2009,klein:sel4:2010}. |
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558 | This verification explicitly assumes the existence of, amongst other things, a trustworthy assembler and compiler. |
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559 | |
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560 | Note that both CompCert, CompCertTSO and the seL4 formalisation assume the existence of `trustworthy' assemblers. |
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561 | For instance, the CompCert C compiler's backend stops at the PowerPC assembly language, in the default backend. |
---|
562 | The observation that an optimising assembler cannot preserve the semantics of every assembly program may have important consequences for these projects (though in the case of CompCertTSO, targetting a multiprocessor, what exactly constitutes the subset of `good programs' may not be entirely clear). |
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563 | If CompCert chooses to assume the existence of an optimising assembler, then care should be made to ensure that any assembly program produced by the CompCert compiler falls into the subset of programs that have a hope of having their semantics preserved by an optimising assembler. |
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564 | |
---|
565 | Our formalisation exploits dependent types in different ways and for multiple purposes. |
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566 | The first purpose is to reduce potential errors in the formalisation of the microprocessor. |
---|
567 | In particular, dependent types are used to constraint the size of bitvectors and tries that represent memory quantities and memory areas respectively. |
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568 | They are also used to simulate polymorphic variants in Matita, in order to provide precise typings to various functions expecting only a subset of all possible addressing modes than the MCS-51 offers. |
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569 | Polymorphic variants nicely capture the absolutely unorthogonal instruction set of the MCS-51 where every opcode must accept its own subset of the 11 addressing mode of the processor. |
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570 | |
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571 | The second purpose is to single out the sources of incompleteness. |
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572 | By abstracting our functions over the dependent type of correct policies, we were able to manifest the fact that the compiler never refuses to compile a program where a correct policy exists. |
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573 | This also allowed to simplify the initial proof by dropping lemmas establishing that one function fails if and only if some previous function does so. |
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574 | |
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575 | Finally, dependent types, together with Matita's liberal system of coercions, allow us to simulate almost entirely---in user space---the proof methodology ``Russell'' of Sozeau~\cite{sozeau:subset:2006}. |
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576 | However, not every proof has been carried out in this way: we only used this style to prove that a function satisfies a specification that only involves that function in a significant way. |
---|
577 | For example, it would be unnatural to see the proof that fetch and assembly commute as the specification of one of the two functions. |
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578 | |
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579 | \subsection{Related work} |
---|
580 | \label{subsect.related.work} |
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581 | |
---|
582 | % piton |
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583 | We are not the first to consider the total correctness of an assembler for a non-trivial assembly language. |
---|
584 | Perhaps the most impressive piece of work in this domain is the Piton stack~\cite{moore:piton:1996,moore:grand:2005}. |
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585 | This was a stack of verified components, written and verified in ACL2, ranging from a proprietary FM9001 microprocessor verified at the gate level, to assemblers and compilers for two high-level languages---a dialect of Lisp and $\mu$Gypsy~\cite{moore:grand:2005}. |
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586 | |
---|
587 | % jinja |
---|
588 | Klein and Nipkow consider a Java-like programming language, Jinja~\cite{klein:machine:2006,klein:machine:2010}. |
---|
589 | They provide a compiler, virtual machine and operational semantics for the programming language and virtual machine, and prove that their compiler is semantics and type preserving. |
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590 | |
---|
591 | We believe some other verified assemblers exist in the literature. |
---|
592 | However, what sets our work apart from that above is our attempt to optimise the machine code generated by our assembler. |
---|
593 | This complicates any formalisation effort, as an attempt at the best possible selection of machine instructions must be made, especially important on a device such as the MCS-51 with a minuscule code memory. |
---|
594 | Further, care must be taken to ensure that the time properties of an assembly program are not modified by the assembly process lest we affect the semantics of any program employing the MCS-51's I/O facilities. |
---|
595 | This is only possible by inducing a cost model on the source code from the optimisation strategy and input program. |
---|
596 | This will be a \emph{leit motif} of CerCo. |
---|
597 | |
---|
598 | \subsection{Resources} |
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599 | \label{subsect.resources} |
---|
600 | |
---|
601 | All files relating to our formalisation effort can be found online at~\url{http://cerco.cs.unibo.it}. |
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602 | In particular, we have assumed several properties of ``library functions'' related in particular to modular arithmetic and datastructure manipulation. |
---|
603 | Moreover, we have axiomatised various ancillary functions needed to complete the main theorems, as well as some `routine' proof obligations of the theorems themselves, preferring instead to focus on the main meat of the theorems. |
---|
604 | We thus believe that the proof strategy is sound and that we will be able to close soon all axioms, up to possible minor bugs that should have local fixes that do not affect the global proof strategy. |
---|
605 | |
---|
606 | The development, including the definition of the executable semantics of the MCS-51, is spread across 29 files, totalling around 18,500 lines of Matita source. |
---|
607 | The bulk of the proof described herein is contained in a series of files, \texttt{AssemblyProof.ma}, \texttt{AssemblyProofSplit.ma} and \texttt{AssemblyProofSplitSplit.ma} consisting at the moment of approximately 4200 lines of Matita source. |
---|
608 | Numerous other lines of proofs are spread all over the development because of dependent types and the Russell proof style, which does not allow one to separate the code from the proofs. |
---|
609 | The low ratio between the number of lines of code and the number of lines of proof is unusual. |
---|
610 | It is justified by the fact that the pseudo-assembly and the assembly language share most constructs and that large parts of the semantics are also shared. |
---|
611 | Therefore many lines of code are required to describe the complex semantics of the processor, but, for the shared cases, the proof of preservation of the semantics is essentially trivial. |
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612 | |
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613 | \bibliography{cpp-2012-asm.bib} |
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614 | |
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615 | \end{document}\renewcommand{\verb}{\lstinline} |
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616 | \def\lstlanguagefiles{lst-grafite.tex} |
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617 | \lstset{language=Grafite} |
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