source: src/ASM/CPP2012-asm/cpp-2012-asm.tex @ 2088

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37\title{On the correctness of an optimising assembler for the Intel MCS-51 microprocessor\thanks{The project CerCo acknowledges the financial support of the Future and Emerging Technologies (FET) programme within the Seventh Framework Programme for Research of the European Commission, under FET-Open grant number: 243881.}}
38\author{Dominic P. Mulligan \and Claudio Sacerdoti Coen}
39\institute{Dipartimento di Scienze dell'Informazione,\\ Universit\'a di Bologna}
40
41\bibliographystyle{splncs03}
42
43\begin{document}
44
45\maketitle
46
47\begin{abstract}
48We present a proof of correctness, in Matita, for an optimising assembler for the MCS-51 microcontroller.
49This assembler constitutes a major component of the EU's CerCo project.
50
51The efficient expansion of pseudoinstructions---particularly jumps---into MCS-51 machine instructions is complex.
52We isolate the decision making over how jumps should be expanded from the expansion process itself as much as possible using `policies'.
53This makes the proof of correctness for the assembler significantly more straightforward.
54
55We observe that it is impossible for an optimising assembler to preserve the semantics of every assembly program.
56Assembly language programs can manipulate concrete addresses in arbitrary ways.
57Our proof strategy contains a tracking facility for `good addresses' and only programs that use good addresses have their semantics preserved under assembly.
58Our strategy offers increased flexibility over the traditional approach to proving the correctness of assemblers, wherein addresses in assembly are kept opaque and immutable.
59In particular, we may experiment with allowing the benign manipulation of addresses.
60\keywords{Verified software, CerCo (Certified Complexity), MCS-51 microcontroller, Matita proof assistant}
61\end{abstract}
62
63% ---------------------------------------------------------------------------- %
64% SECTION                                                                      %
65% ---------------------------------------------------------------------------- %
66\section{Introduction}
67\label{sect.introduction}
68
69We consider the formalisation of an assembler for the Intel MCS-51 8-bit microprocessor in the Matita proof assistant~\cite{asperti:user:2007}.
70This formalisation forms a major component of the EU-funded CerCo (`Certified Complexity') project~\cite{cerco:2011}, concerning the construction and formalisation of a concrete complexity preserving compiler for a large subset of the C programming language.
71
72The MCS-51 dates from the early 1980s and is commonly called the 8051/8052.
73Despite the microprocessor's age, derivatives are still widely manufactured by a number of semiconductor foundries, with the processor being used especially in embedded systems development, where well-tested, cheap, predictable microprocessors find their niche.
74
75The MCS-51 has a relative paucity of features compared to its more modern brethren, with the lack of any caching or pipelining features meaning that timing of execution is predictable, making the MCS-51 very attractive for CerCo's ends.
76Yet---as with many things---what one hand giveth, the other taketh away, and the MCS-51's paucity of features---though an advantage in many respects---also quickly becomes a hindrance.
77In particular, the MCS-51 features a relatively minuscule series of memory spaces by modern standards.
78As a result our C compiler, to have any sort of hope of successfully compiling realistic programs for embedded devices, ought to produce `tight' machine code.
79
80In order to do this, we must solve the `branch displacement' problem---deciding how best to expand pseudojumps to labels in assembly language to machine code jumps.
81Clearly a correct but efficient strategy would be to expand all unconditional pseudojumps to the MCS-51's \texttt{LJMP} instruction, and all conditional pseudojumps to a set configuration of jumps using \texttt{LJMP} instructions; this is inefficient and a waste of valuable code memory space.
82Finding an efficient solution with this expansion process is not trivial, and is a well-known problem for those writing assemblers targetting RISC architectures (for instance, see~\cite{holmes:branch:2006}).
83
84To free the CerCo C compiler from having to consider complications relating to branch displacement, we have chosen to implement an optimising assembler, whose input language the compiler will target.
85Labels, conditional jumps to labels, a program preamble containing global data and a \texttt{MOV} instruction for moving this global data into the MCS-51's one 16-bit register all feature in our assembly language.
86We simplify the proof by assuming that all our assembly programs are pre-linked (i.e. we do not formalise a linker---this is left for future work).
87
88Further, we must make sure that the assembly process does not change the timing characteristics of an assembly program for two reasons.
89
90First, the semantics of some functions of the MCS-51, notably I/O, depend on the microprocessor's clock.
91Changing how long a particular program takes to execute can affect the semantics of a program.
92This is undesirable.
93
94Second, CerCo imposes a cost model on C programs or, more specifically, on simple blocks of instructions.
95This cost model is induced by the compilation process itself, and its non-compositional nature allows us to assign different costs to identical blocks of instructions depending on how they are compiled.
96In short, we aim to obtain a very precise costing for a program by embracing the compilation process, not ignoring it.
97This, however, complicates the proof of correctness for the compiler proper, and we must prove that both the meaning and concrete complexity characteristics of the program are preserved for every translation pass in the compiler, including the assembler.
98
99How we went about resolving this problem affected the shape of our proof of correctness for the whole assembler in a rather profound way.
100We first attempted to synthesise a solution bottom up: starting with no solution, we gradually refine a solution using the same functions that implement the jump expansion process.
101Using this technique, solutions can fail to exist, and the proof of correctness for the assembler quickly descends into a diabolical quagmire.
102
103Abandoning this attempt, we instead split the `policy'---the decision over how any particular jump should be expanded---from the implementation that actually expands assembly programs into machine code.
104Assuming the existence of a correct policy, we proved the implementation of the assembler correct.
105Further, we proved that the assembler fails to assemble an assembly program if and only if a correct policy does not exist.
106This is achieved by means of dependent types: the assembly function is total over a program, a policy and the proof that the policy is correct for that program.
107
108Policies do not exist in only a limited number of circumstances: namely, if a pseudoinstruction attempts to jump to a label that does not exist, or the program is too large to fit in code memory, even after shrinking jumps according to the policy.
109The first circumstance is an example of a serious compiler error, as an ill-formed assembly program was generated, and does not (and should not) count as a mark against the completeness of the assembler.
110
111The rest of this paper is a detailed description of our proof that is, in part, still a work in progress.
112
113% ---------------------------------------------------------------------------- %
114% SECTION                                                                      %
115% ---------------------------------------------------------------------------- %
116\subsection{Overview of the paper}
117\label{subsect.overview.of.the.paper}
118In Section~\ref{sect.matita} we provide a brief overview of the Matita proof assistant for the unfamiliar reader.
119In Section~\ref{sect.the.proof} we discuss the design and implementation of the proof proper.
120In Section~\ref{sect.conclusions} we conclude.
121
122% ---------------------------------------------------------------------------- %
123% SECTION                                                                      %
124% ---------------------------------------------------------------------------- %
125\section{Matita}
126\label{sect.matita}
127
128Matita is a proof assistant based on a variant of the Calculus of (Co)inductive Constructions~\cite{asperti:user:2007}.
129In particular, it features dependent types that we heavily exploit in the formalisation.
130The syntax of the statements and definitions in the paper should be self-explanatory, at least to those exposed to dependent type theory.
131We only remark the use of of `$\mathtt{?}$' or `$\mathtt{\ldots}$' for omitting single terms or sequences of terms to be inferred automatically by the system, respectively.
132Those that are not inferred are left to the user as proof obligations.
133Pairs are denoted with angular brackets, $\langle-, -\rangle$.
134
135Matita features a liberal system of coercions.
136It is possible to define a uniform coercion $\lambda x.\langle x,?\rangle$ from every type $T$ to the dependent product $\Sigma x:T.P~x$.
137The coercion opens a proof obligation that asks the user to prove that $P$ holds for $x$.
138When a coercion must be applied to a complex term (a $\lambda$-abstraction, a local definition, or a case analysis), the system automatically propagates the coercion to the sub-terms
139 For instance, to apply a coercion to force $\lambda x.M : A \to B$ to have type $\forall x:A.\Sigma y:B.P~x~y$, the system looks for a coercion from $M: B$ to $\Sigma y:B.P~x~y$ in a context augmented with $x:A$.
140This is significant when the coercion opens a proof obligation, as the user will be presented with multiple, but simpler proof obligations in the correct context.
141In this way, Matita supports the ``Russell'' proof methodology developed by Sozeau in~\cite{sozeau:subset:2006}, with an implementation that is lighter and more tightly integrated with the system than that of Coq.
142
143% ---------------------------------------------------------------------------- %
144% SECTION                                                                      %
145% ---------------------------------------------------------------------------- %
146\section{The proof}
147\label{sect.the.proof}
148
149% ---------------------------------------------------------------------------- %
150% SECTION                                                                      %
151% ---------------------------------------------------------------------------- %
152
153\subsection{Machine code semantics}
154\label{subsect.machine.code.semantics}
155
156Our emulator centres around a \texttt{Status} record, describing the microprocessor's state.
157This record contains fields corresponding to the microprocessor's program counter, registers, and so on.
158At the machine code level, code memory is implemented as a compact trie of bytes addressed by the program counter.
159We parameterise \texttt{Status} records by this representation as a few technical tasks manipulating statuses are made simpler using this approach, as well as permitting a modicum of abstraction.
160
161We may execute a single step of a machine code program using the \texttt{execute\_1} function, which returns an updated \texttt{Status}:
162\begin{lstlisting}
163definition execute_1: $\forall$cm. Status cm $\rightarrow$ Status cm := $\ldots$
164\end{lstlisting}
165%The function \texttt{execute} allows one to execute an arbitrary, but fixed (due to Matita's normalisation requirement) number of steps of a program.
166The function \texttt{execute\_1} closely matches the operation of the MCS-51 hardware, as described by a Siemen's manufacturer's data sheet (specifically, this one~\cite{siemens:2011}).
167We first fetch, using the program counter, from code memory the first byte of the instruction to be executed, decoding the resulting opcode, fetching more bytes as is necessary.
168Decoded instructions are represented as an inductive type, where $\llbracket - \rrbracket$ denotes a fixed-length vector:
169\begin{lstlisting}
170inductive preinstruction (A: Type[0]): Type[0] :=
171 | ADD: $\llbracket$acc_a$\rrbracket$ → $\llbracket$registr; direct; indirect; data$\rrbracket$ $\rightarrow$ preinstruction A
172 | INC: $\llbracket$ acc_a; registr; direct; indirect; dptr$\rrbracket$ $\rightarrow$ preinstruction A
173 | JB: $\llbracket$bit_addr$\rrbracket$ $\rightarrow$ A $\rightarrow$ preinstruction A
174 | ...
175
176inductive instruction: Type[0] :=
177 | LCALL: $\llbracket$addr16$\rrbracket$ $\rightarrow$ instruction
178 | AJMP: $\llbracket$addr11$\rrbracket$ $\rightarrow$ instruction
179 | RealInstruction: preinstruction $\llbracket$relative$\rrbracket$ $\rightarrow$ instruction.
180 | ...
181\end{lstlisting}
182Here, we use dependent types to provide a precise typing for instructions, specifying in their type the permitted addressing modes that their arguments can belong to.
183The parameterised type $A$ of \texttt{preinstruction} represents the addressing mode for conditional jumps; in \texttt{instruction} we fix this type to be a relative offset in the constructor \texttt{RealInstruction}.
184
185Once decoded, execution proceeds by a case analysis on the decoded instruction, following the operation of the hardware.
186For example, the \texttt{DEC} instruction (`decrement') is implemented as follows:
187
188\begin{lstlisting}
189 | DEC addr $\Rightarrow$
190  let s := add_ticks1 s in
191  let $\langle$result, flags$\rangle$ := sub_8_with_carry (get_arg_8 $\ldots$ s true addr)
192   (bitvector_of_nat 8 1) false in
193     set_arg_8 $\ldots$ s addr result
194\end{lstlisting}
195
196Here, \texttt{add\_ticks1} models the incrementing of the internal clock of the microprocessor.
197
198% ---------------------------------------------------------------------------- %
199% SECTION                                                                      %
200% ---------------------------------------------------------------------------- %
201
202\subsection{Assembly code semantics}
203\label{subsect.assembly.code.semantics}
204
205An assembly program is a list of potentially labelled pseudoinstructions, bundled with a preamble consisting of a list of symbolic names for locations in data memory (i.e. global variables).
206Pseudoinstructions are implemented as an inductive type:
207\begin{lstlisting}
208inductive pseudo_instruction: Type[0] :=
209  | Instruction: preinstruction Identifier $\rightarrow$ pseudo_instruction
210    ...
211  | Jmp: Identifier $\rightarrow$ pseudo_instruction
212  | Call: Identifier $\rightarrow$ pseudo_instruction
213  | Mov: $\llbracket$dptr$\rrbracket$ $\rightarrow$ Identifier $\rightarrow$ pseudo_instruction.
214\end{lstlisting}
215The pseudoinstructions \texttt{Jmp}, \texttt{Call} and \texttt{Mov} are generalisations of machine code unconditional jumps, calls and move instructions respectively, all of whom act on labels, as opposed to concrete memory addresses.
216Similarly, conditional jumps can now only jump to labels, as is implied by the first constructor of the type above.
217All other object code instructions are available at the assembly level, with the exception of those that appeared in the \texttt{instruction} type, such as \texttt{ACALL} and \texttt{LJMP}.
218These are jumps and calls to absolute addresses, which we do not wish to allow at the assembly level.
219
220Execution of pseudoinstructions is a function from \texttt{PseudoStatus} to \texttt{PseudoStatus}.
221Both \texttt{Status} and \texttt{PseudoStatus} are instances of a more general type parameterised over the representation of code memory.
222The more general type is crucial for sharing the majority of the semantics of the two languages.
223
224Emulation for pseudoinstructions is handled by \texttt{execute\_1\_pseudo\_instruction}:
225\begin{lstlisting}
226definition execute_1_pseudo_instruction:
227 (Word $\rightarrow$ nat $\times$ nat) $\rightarrow$ $\forall$cm. PseudoStatus cm $\rightarrow$ PseudoStatus cm := $\ldots$
228\end{lstlisting}
229Notice, here, that the emulation function for assembly programs takes an additional argument over \texttt{execute\_1}.
230This is a function that maps program counters (at the assembly level) to pairs of natural numbers representing the number of clock ticks that the pseudoinstruction needs to execute, post expansion.
231We call this function a \emph{costing}, and note that the costing is induced by the particular strategy we use to expand pseudoinstructions.
232If we change how we expand conditional jumps to labels, for instance, then the costing needs to change, hence \texttt{execute\_1\_pseudo\_instruction}'s parametricity in the costing.
233
234The costing returns \emph{pairs} of natural numbers because, in the case of expanding conditional jumps to labels, the expansion of the `true branch' and `false branch' may differ in execution time.
235The \texttt{add\_ticks1} function, which we have already seen used to increment the machine clock above, is determined for the assembly language from the costing function.
236
237Execution proceeds by first fetching from pseudo-code memory using the program counter---treated as an index into the pseudoinstruction list.
238No decoding is required.
239We then proceed by case analysis over the pseudoinstruction, reusing the code for object code for all instructions present in the MCS-51's instruction set.
240For all newly introduced pseudoinstructions, we simply translate labels to concrete addresses before behaving as a `real' instruction.
241
242In contrast to other approaches, we do not perform any kind of symbolic execution, wherein data is the disjoint union of bytes and addresses, with addresses kept opaque and immutable.
243Labels are immediately translated to concrete addresses, and registers and memory locations only ever contain bytes, never labels.
244As a consequence, we allow the programmer to mangle, change and generally adjust addresses as they want, under the proviso that the translation process may not be able to preserve the semantics of programs that do this.
245This will be further discussed in Subsection~\ref{subsect.total.correctness.for.well.behaved.assembly.programs}.
246
247% ---------------------------------------------------------------------------- %
248% SECTION                                                                      %
249% ---------------------------------------------------------------------------- %
250
251\subsection{The assembler}
252\label{subsect.the.assembler}
253
254Conceptually the assembler works in two passes.
255The first pass expands pseudoinstructions into a list of machine code instructions using the function \texttt{expand\_pseudo\_instruction}.
256The second pass encodes as a list of bytes the expanded instruction list by mapping the function \texttt{assembly1} across the list, and then flattening.
257\begin{displaymath}
258[\mathtt{P_1}, \ldots \mathtt{P_n}] \xrightarrow{\left(\mathtt{P_i} \xrightarrow{\mbox{\fontsize{7}{9}\selectfont$\mathtt{expand\_pseudo\_instruction}$}} \mathtt{[I^1_i, \ldots I^q_i]} \xrightarrow{\mbox{\fontsize{7}{9}\selectfont$\mathtt{~~~~~~~~assembly1^{*}~~~~~~~~}$}} \mathtt{[0110]}\right)^{*}} \mathtt{[010101]}
259\end{displaymath}
260The most complex of the two passes is the first, which expands pseudoinstructions and must perform the task of branch displacement~\cite{holmes:branch:2006}.
261The function \texttt{assembly\_1\_pseudo\_instruction} used in the body of the paper is essentially the composition of the two passes.
262
263The branch displacement problems consists of the problem of expanding pseudojumps into their concrete counterparts, preferably as efficiently as possible.
264For instance, the MCS-51 features three unconditional jump instructions: \texttt{LJMP} and \texttt{SJMP}---`long jump' and `short jump' respectively---and an 11-bit oddity of the MCS-51, \texttt{AJMP}.
265Each of these three instructions expects arguments in different sizes and behaves in markedly different ways: \texttt{SJMP} may only perform a `local jump'; \texttt{LJMP} may jump to any address in the MCS-51's memory space and \texttt{AJMP} may jump to any address in the current memory page.
266Consequently, the size of each opcode is different, and to squeeze as much code as possible into the MCS-51's limited code memory, the smallest possible opcode that will suffice should be selected.
267
268Similarly, a conditional pseudojump must be translated potentially into a configuration of machine code instructions, depending on the distance to the jump's target.
269For example, to translate a jump to a label, a single conditional jump pseudoinstruction may be translated into a block of three real instructions as follows (here, \texttt{JZ} is `jump if accumulator is zero'):
270{\small{
271\begin{displaymath}
272\begin{array}{r@{\quad}l@{\;\;}l@{\qquad}c@{\qquad}l@{\;\;}l}
273       & \mathtt{JZ}  & \mathtt{label}                      &                 & \mathtt{JZ}   & \text{size of \texttt{SJMP} instruction} \\
274       & \ldots       &                            & \text{translates to}   & \mathtt{SJMP} & \text{size of \texttt{LJMP} instruction} \\
275\mathtt{label:} & \mathtt{MOV} & \mathtt{A}\;\;\mathtt{B}   & \Longrightarrow & \mathtt{LJMP} & \text{address of \textit{label}} \\
276       &              &                            &                 & \ldots        & \\
277       &              &                            &                 & \mathtt{MOV}  & \mathtt{A}\;\;\mathtt{B}
278\end{array}
279\end{displaymath}}}
280Here, if \texttt{JZ} fails, we fall through to the \texttt{SJMP} which jumps over the \texttt{LJMP}.
281Naturally, if \texttt{label} is `close enough', a conditional jump pseudoinstruction is mapped directly to a conditional jump machine instruction; the above translation only applies if \texttt{label} is not sufficiently local.
282
283In order to implement branch displacement it is impossible to really make the \texttt{expand\_pseudo\_instruction} function completely independent of the encoding function.
284This is due to branch displacement requiring the distance in bytes of the target of the jump.
285Moreover the standard solutions for solving the branch displacement problem find their solutions iteratively, by either starting from a solution where all jumps are long, and shrinking them when possible, or starting from a state where all jumps are short and increasing their length as needed.
286Proving the correctness of such algorithms is already quite involved and the correctness of the assembler as a whole does not depend on the `quality' of the solution found to a branch displacement problem.
287For this reason, we try to isolate the computation of a branch displacement problem from the proof of correctness for the assembler by parameterising our \texttt{expand\_pseudo\_instruction} by a `policy'.
288
289\begin{lstlisting}
290definition expand_pseudo_instruction:
291 $\forall$lookup_labels: Identifier $\rightarrow$ Word.
292 $\forall$sigma: Word $\rightarrow$ Word.
293 $\forall$policy: Word $\rightarrow$ bool.
294 $\forall$ppc: Word.
295 $\forall$lookup_datalabels: Identifier $\rightarrow$ Word.
296 $\forall$pi: pseudo_instruction.
297  list instruction := ...
298\end{lstlisting}
299Here, the functions \texttt{lookup\_labels} and \texttt{lookup\_datalabels} are the functions that map labels and datalabels to program counters respectively, both of them used in the semantics of assembly.
300The input \texttt{pi} is the pseudoinstruction to be expanded and is found at address \texttt{ppc} in the assembly program.
301The policy is defined using the two functions \texttt{sigma} and \texttt{policy}, of which \texttt{sigma} is the most interesting.
302The function \texttt{sigma} maps pseudo program counters to program counters: the encoding of the expansion of the pseudoinstruction found at address \texttt{a} in the assembly code should be placed into code memory at address \texttt{sigma(a)}.
303Of course this is possible only if the policy is correct, which means that the encoding of consecutive assembly instructions must be consecutive in code memory.
304\begin{displaymath}
305\texttt{sigma}(\texttt{ppc} + 1) = \texttt{pc} + \texttt{current\_instruction\_size}
306\end{displaymath}
307Here, \texttt{current\_instruction\_size} is the size in bytes of the encoding of the expanded pseudoinstruction found at \texttt{ppc}.
308Note that the entanglement we hinted at is only partially solved in this way: the assembler code can ignore the implementation details of the algorithm that finds a policy;
309however, the algorithm that finds a policy must know the exact behaviour of the assembly program because it needs to predict the way the assembly will expand and encode pseudoinstructions, once fed with a policy.
310A companion submission to this one~\cite{boender:correctness:2012} certifies an algorithm that finds branch displacement policies for the assembler described in this paper.
311
312The \texttt{expand\_pseudo\_instruction} function uses the \texttt{sigma} map to determine the size of jump required when expanding pseudojumps, computing the jump size by examining the size of the differences between program counters.
313For instance, if at address \texttt{ppc} in the assembly program we found \texttt{Jmp l} such that \texttt{lookup\_labels l = a}, if the offset \texttt{d = sigma(a) - sigma(ppc + 1)} is such that \texttt{d} $< 128$ then \texttt{Jmp l} is normally translated to the best local solution, the short jump \texttt{SJMP d}.
314A global best solution to the branch displacement problem, however, is not always made of locally best solutions.
315Therefore, in some circumstances, it is necessary to force the assembler to expand jumps into larger ones.
316This is achieved by the \texttt{policy} function: if \texttt{policy ppc = true} then a \texttt{Jmp l} at address \texttt{ppc} is always translated to a long jump.
317An essentially identical mechanism exists for call instructions.
318
319% ---------------------------------------------------------------------------- %
320% SECTION                                                                      %
321% ---------------------------------------------------------------------------- %
322\subsection{Correctness of the assembler with respect to fetching}
323\label{subsect.total.correctness.of.the.assembler}
324Using our policies, we now work toward proving the total correctness of the assembler.
325By `total correctness', we mean that the assembly process never fails when provided with a correct policy and that the process does not change the semantics of a certain class of well behaved assembly programs.
326
327The aim of this section is to prove the following informal statement: when we fetch an assembly pseudoinstruction \texttt{I} at address \texttt{ppc}, then we can fetch the expanded pseudoinstruction(s) \texttt{[J1, \ldots, Jn] = fetch\_pseudo\_instruction \ldots\ I\ ppc} from \texttt{sigma(ppc)} in the code memory obtained by loading the assembled object code.
328This constitutes the first major step in the proof of correctness of the assembler, the next one being the simulation of \texttt{I} by \texttt{[J1, \ldots, Jn]} (see Subsection~\ref{subsect.total.correctness.for.well.behaved.assembly.programs}).
329
330The \texttt{assembly} function is given a Russell type (slightly simplified here):
331\begin{lstlisting}
332definition assembly:
333 $\forall$p: pseudo_assembly_program.
334 $\forall$sigma: Word $\rightarrow$ Word.
335 $\forall$policy: Word $\rightarrow$ bool.
336  $\Sigma$res:list Byte $\times$ (BitVectorTrie costlabel 16).
337   sigma_meets_specification p sigma policy $\rightarrow$
338   let $\langle$preamble, instr_list$\rangle$ := p in
339   |instr_list| < 2^16 $\rightarrow$
340   let $\langle$assembled,costs$\rangle$ := res in
341    $\forall$ppc. $\forall$ppc_ok:nat_of_bitvector $\ldots$ ppc < |instr_list|.
342    let $\langle$pi,newppc$\rangle$ := fetch_pseudo_instruction instr_list ppc ppc_ok in
343    let $\langle$l,a$\rangle$ := assembly_1_pseudoinstruction $\ldots$ sigma policy ppc $\ldots$ pi in
344     $\forall$j:nat. j < |a|
345      nth j a = nth (add $\ldots$ (sigma ppc) (bitvector_of_nat ? j))) assembled
346\end{lstlisting}
347In plain words, the type of assembly states the following.
348Suppose we are given a policy that is correct for the program we are assembling, and suppose the program to be assembled is fully addressable by a 16-bit word.
349Then if we fetch from the pseudo program counter \texttt{ppc} we get a pseudoinstruction \texttt{pi} and a new pseudo program counter \texttt{ppc}.
350Further, assembling the pseudoinstruction \texttt{pi} results in a list of bytes, \texttt{a}.
351Then, indexing into this list with any natural number \texttt{j} less than the length of \texttt{a} gives the same result as indexing into \texttt{assembled} with \texttt{sigma(ppc)} (the program counter pointing to the start of the expansion in \texttt{assembled}) plus \texttt{j}.
352
353Essentially the lemma above states that the \texttt{assembly} function correctly expands pseudoinstructions, and that the expanded instruction reside consecutively in memory.
354This result is lifted from lists of bytes into a result on tries of bytes (i.e. code memories), using an additional lemma: \texttt{assembly\_ok}.
355
356Lemma \texttt{fetch\_assembly} establishes that the \texttt{fetch} and \texttt{assembly1} functions interact correctly.
357The \texttt{fetch} function, as its name implies, fetches the instruction indexed by the program counter in the code memory, while \texttt{assembly1} maps a single instruction to its byte encoding:
358\begin{lstlisting}
359lemma fetch_assembly:
360 $\forall$pc: Word.
361 $\forall$i: instruction.
362 $\forall$code_memory: BitVectorTrie Byte 16.
363 $\forall$assembled: list Byte.
364  assembled = assembly1 i $\rightarrow$
365  let len := length $\ldots$ assembled in
366  let pc_plus_len := add $\ldots$ pc (bitvector_of_nat $\ldots$ len) in
367   encoding_check code_memory pc pc_plus_len assembled $\rightarrow$
368   let $\langle$instr, pc', ticks$\rangle$ := fetch code_memory pc in
369    instr = i $\wedge$ ticks = (ticks_of_instruction instr) $\wedge$ pc' = pc_plus_len.
370\end{lstlisting}
371In particular, we read \texttt{fetch\_assembly} as follows.
372Given an instruction, \texttt{i}, we first assemble the instruction to obtain \texttt{assembled}, checking that the assembled instruction was stored in code memory correctly.
373Fetching from code memory, we obtain a tuple consisting of the instruction, new program counter, and the number of ticks this instruction will take to execute.
374We finally check that the fetched instruction is the same instruction that we began with, and the number of ticks this instruction will take to execute is the same as the result returned by a lookup function, \texttt{ticks\_of\_instruction}, devoted to tracking this information.
375Or, in plainer words, assembling and then immediately fetching again gets you back to where you started.
376
377Lemma \texttt{fetch\_assembly\_pseudo} (slightly simplified, here) is obtained by composition of \texttt{expand\_pseudo\_instruction} and \texttt{assembly\_1\_pseudoinstruction}:
378\begin{lstlisting}
379lemma fetch_assembly_pseudo:
380 $\forall$program: pseudo_assembly_program.
381 $\forall$sigma: Word $\rightarrow$ Word.
382 $\forall$policy: Word $\rightarrow$ bool.
383 $\forall$ppc.
384 $\forall$code_memory.
385 let $\langle$preamble, instr_list$\rangle$ := program in
386 let pi := $\pi_1$ (fetch_pseudo_instruction instr_list ppc) in
387 let pc := sigma ppc in
388 let instrs := expand_pseudo_instruction $\ldots$ sigma policy ppc $\ldots$ pi in
389 let $\langle$l, a$\rangle$ := assembly_1_pseudoinstruction $\ldots$ sigma policy ppc $\ldots$ pi in
390 let pc_plus_len := add $\ldots$ pc (bitvector_of_nat $\ldots$ l) in
391  encoding_check code_memory pc pc_plus_len a $\rightarrow$
392   fetch_many code_memory pc_plus_len pc instructions.
393\end{lstlisting}
394Here, \texttt{l} is the number of machine code instructions the pseudoinstruction at hand has been expanded into.
395We assemble a single pseudoinstruction with \texttt{assembly\_1\_pseudoinstruction}, which internally calls \texttt{expand\_pseudo\_instruction}.
396The function \texttt{fetch\_many} fetches multiple machine code instructions from code memory and performs some routine checks.
397
398Intuitively, Lemma \texttt{fetch\_assembly\_pseudo} can be read as follows.
399Suppose we expand the pseudoinstruction at \texttt{ppc} with the policy decision \texttt{sigma}, obtaining the list of machine code instructions \texttt{instrs}.
400Suppose we also assemble the pseudoinstruction at \texttt{ppc} to obtain \texttt{a}, a list of bytes.
401Then, we check with \texttt{fetch\_many} that the number of machine instructions that were fetched matches the number of instruction that \texttt{expand\_pseudo\_instruction} expanded.
402
403The final lemma in this series is \texttt{fetch\_assembly\_pseudo2} that combines the Lemma \texttt{fetch\_assembly\_pseudo} with the correctness of the functions that load object code into the processor's memory.
404Again, we slightly simplify:
405\begin{lstlisting}
406lemma fetch_assembly_pseudo2:
407 $\forall$program.
408 $\forall$sigma.
409 $\forall$policy.
410 $\forall$sigma_meets_specification.
411 $\forall$ppc.
412  let $\langle$preamble, instr_list$\rangle$ := program in
413  let $\langle$labels, costs$\rangle$ := create_label_cost_map instr_list in
414  let $\langle$assembled, costs'$\rangle$ := $\pi_1$ $\ldots$ (assembly program sigma policy) in
415  let cmem := load_code_memory assembled in
416  let $\langle$pi, newppc$\rangle$ := fetch_pseudo_instruction instr_list ppc in
417  let instructions := expand_pseudo_instruction $\ldots$ sigma ppc $\ldots$ pi in
418    fetch_many cmem (sigma newppc) (sigma ppc) instructions.
419\end{lstlisting}
420
421Here we use $\pi_1 \ldots$ to eject out the existential witness from the Russell-typed function \texttt{assembly}.
422
423We read \texttt{fetch\_assembly\_pseudo2} as follows.
424Suppose we are able to successfully assemble an assembly program using \texttt{assembly} and produce a code memory, \texttt{cmem}.
425Then, fetching a pseudoinstruction from the pseudo-code memory at address \texttt{ppc} corresponds to fetching a sequence of instructions from the real code memory using \texttt{sigma} to expand pseudoinstructions.
426The fetched sequence corresponds to the expansion, according to \texttt{sigma}, of the pseudoinstruction.
427
428At first, the lemmas appears to immediately imply the correctness of the assembler.
429However, this property is \emph{not} strong enough to establish that the semantics of an assembly program has been preserved by the assembly process since it does not establish the correspondence between the semantics of a pseudoinstruction and that of its expansion.
430In particular, the two semantics differ on instructions that \emph{could} directly manipulate program addresses.
431
432% ---------------------------------------------------------------------------- %
433% SECTION                                                                      %
434% ---------------------------------------------------------------------------- %
435\subsection{Total correctness for `well behaved' assembly programs}
436\label{subsect.total.correctness.for.well.behaved.assembly.programs}
437
438The traditional approach to verifying the correctness of an assembler is to treat memory addresses as opaque structures that cannot be modified.
439Memory is represented as a map from opaque addresses to the disjoint union of data and opaque addresses---addresses are kept opaque to prevent their possible `semantics breaking' manipulation by assembly programs:
440\begin{displaymath}
441\mathtt{Mem} : \mathtt{Addr} \rightarrow \mathtt{Bytes} + \mathtt{Addr} \qquad \llbracket - \rrbracket : \mathtt{Instr} \rightarrow \mathtt{Mem} \rightarrow \mathtt{option\ Mem}
442\end{displaymath}
443The semantics of a pseudoinstruction, $\llbracket - \rrbracket$, is given as a possibly failing function from pseudoinstructions and memory spaces to new memory spaces.
444The semantic function proceeds by case analysis over the operands of a given instruction, failing if either operand is an opaque address, or otherwise succeeding, updating memory.
445\begin{gather*}
446\llbracket \mathtt{ADD\ @A1\ @A2} \rrbracket^\mathtt{M} = \begin{cases}
447                                                              \mathtt{Byte\ b1},\ \mathtt{Byte\ b2} & \rightarrow \mathtt{Some}(\mathtt{M}\ \text{with}\ \mathtt{b1} + \mathtt{b2}) \\
448                                                              -,\ \mathtt{Addr\ a} & \rightarrow \mathtt{None} \\
449                                                              \mathtt{Addr\ a},\ - & \rightarrow \mathtt{None}
450                                                            \end{cases}
451\end{gather*}
452In contrast, in this paper we take a different approach.
453We trace memory locations (and, potentially, registers) that contain memory addresses.
454We then prove that only those assembly programs that use addresses in `safe' ways have their semantics preserved by the assembly process---a sort of dynamic type system sitting atop memory.
455
456We believe that this approach is more flexible when compared to the traditional approach, as in principle it allows us to introduce some permitted \emph{benign} manipulations of addresses that the traditional approach, using opaque addresses, cannot handle, therefore expanding the set of input programs that can be assembled correctly.
457This approach, of using real addresses coupled with a weak, dynamic typing system sitting atop of memory, is similar to one taken by Huth \emph{et al}~\cite{tuch:types:2007}, for reasoning about low-level C code.
458
459Our analogue of the semantic function above is then merely a wrapper around the function that implements the semantics of machine code, paired with a function that keeps track of addresses.
460This permits a large amount of code reuse, as the semantics of pseudo- and machine code are essentially shared.
461The only thing that changes at the assembly level is the presence of the new tracking function.
462
463However, with this approach we must detect (at run time) programs that manipulate addresses in well behaved ways, according to some approximation of well-behavedness.
464We use an \texttt{internal\_pseudo\_address\_map} to trace addresses of code memory addresses in internal RAM:
465\begin{lstlisting}
466definition internal_pseudo_address_map :=
467  list ((BitVector 8) $\times$ (bool $\times$ Word)) $\times$ (option (bool $\times$ Word)).
468\end{lstlisting}
469The implementation of \texttt{internal\_pseudo\_address\_map} is complicated by some peculiarities of the MCS-51's instruction set.
470Note here that all addresses are 16 bit words, but are stored (and manipulated) as 8 bit bytes.
471All \texttt{MOV} instructions in the MCS-51 must use the accumulator \texttt{A} as an intermediary, moving a byte at a time.
472The second component of \texttt{internal\_pseudo\_address\_map} therefore states whether the accumulator currently holds a piece of an address, and if so, whether it is the upper or lower byte of the address (using the boolean flag) complete with the corresponding, source address in full.
473The first component, on the other hand, performs a similar task for the rest of external RAM.
474Again, we use a boolean flag to describe whether a byte is the upper or lower component of a 16-bit address.
475
476The \texttt{low\_internal\_ram\_of\_pseudo\_low\_internal\_ram} function converts the lower internal RAM of a \texttt{PseudoStatus} into the lower internal RAM of a \texttt{Status}.
477A similar function exists for high internal RAM.
478Note that both RAM segments are indexed using addresses 7-bits long.
479The function is currently axiomatised, and an associated set of axioms prescribe the behaviour of the function:
480\begin{lstlisting}
481axiom low_internal_ram_of_pseudo_low_internal_ram:
482 internal_pseudo_address_map$\rightarrow$BitVectorTrie Byte 7$\rightarrow$BitVectorTrie Byte 7.
483\end{lstlisting}
484
485Next, we are able to translate \texttt{PseudoStatus} records into \texttt{Status} records using \texttt{status\_of\_pseudo\_status}.
486Translating a \texttt{PseudoStatus}'s code memory requires we expand pseudoinstructions and then assemble to obtain a trie of bytes.
487This never fails, provided that our policy is correct:
488\begin{lstlisting}
489definition status_of_pseudo_status:
490 internal_pseudo_address_map $\rightarrow$ $\forall$pap. $\forall$ps: PseudoStatus pap.
491 $\forall$sigma: Word $\rightarrow$ Word. $\forall$policy: Word $\rightarrow$ bool.
492  Status (code_memory_of_pseudo_assembly_program pap sigma policy)
493\end{lstlisting}
494
495The \texttt{next\_internal\_pseudo\_address\_map} function is responsible for run time monitoring of the behaviour of assembly programs, in order to detect well behaved ones.
496It returns a map that traces memory addresses in internal RAM after execution of the next pseudoinstruction, failing when the instruction tampers with memory addresses in unanticipated (but potentially correct) ways.
497It thus decides the membership of a strict subset of the set of well behaved programs.
498\begin{lstlisting}
499definition next_internal_pseudo_address_map: internal_pseudo_address_map
500 $\rightarrow$ PseudoStatus $\rightarrow$ option internal_pseudo_address_map
501\end{lstlisting}
502Note, if we wished to allow `benign manipulations' of addresses, it would be this function that needs to be changed.
503
504The function \texttt{ticks\_of0} computes how long---in clock cycles---a pseudoinstruction will take to execute when expanded in accordance with a given policy.
505The function returns a pair of natural numbers, needed for recording the execution times of each branch of a conditional jump.
506\begin{lstlisting}
507definition ticks_of0:
508 pseudo_assembly_program $\rightarrow$ (Word $\rightarrow$ Word) $\rightarrow$ (Word $\rightarrow$ bool) $\rightarrow$ Word $\rightarrow$
509   pseudo_instruction $\rightarrow$ nat $\times$ nat := $\ldots$
510\end{lstlisting}
511An additional function, \texttt{ticks\_of}, is merely a wrapper around this function.
512
513Finally, we are able to state and prove our main theorem.
514This relates the execution of a single assembly instruction and the execution of (possibly) many machine code instructions, as long as we are able to track memory addresses properly:
515\begin{lstlisting}
516theorem main_thm:
517 $\forall$M, M': internal_pseudo_address_map.
518 $\forall$program: pseudo_assembly_program.
519 let $\langle$preamble, instr_list$\rangle$ := program in
520 $\forall$is_well_labelled: is_well_labelled_p instr_list.
521 $\forall$sigma: Word $\rightarrow$ Word.
522 $\forall$policy: Word $\rightarrow$ bool.
523 $\forall$sigma_meets_specification.
524 $\forall$ps: PseudoStatus program.
525 $\forall$program_counter_in_bounds.
526  next_internal_pseudo_address_map M program ps = Some $\ldots$ M' $\rightarrow$
527  $\exists$n. execute n $\ldots$ (status_of_pseudo_status M $\ldots$ ps sigma policy) =
528   status_of_pseudo_status M' $\ldots$ (execute_1_pseudo_instruction
529     (ticks_of program sigma policy) program ps) sigma policy.
530\end{lstlisting}
531The statement is standard for forward simulation, but restricted to \texttt{PseudoStatuses} \texttt{ps} whose next instruction to be executed is well-behaved with respect to the \texttt{internal\_pseudo\_address\_map} \texttt{M}.
532Further, we explicitly require proof that our policy is correct and the pseudo program counter lies within the bounds of the program.
533Theorem \texttt{main\_thm} establishes the total correctness of the assembly process and can simply be lifted to the forward simulation of an arbitrary number of well behaved steps on the assembly program.
534
535% ---------------------------------------------------------------------------- %
536% SECTION                                                                      %
537% ---------------------------------------------------------------------------- %
538\section{Conclusions}
539\label{sect.conclusions}
540
541We are proving the total correctness of an assembler for MCS-51 assembly language.
542In particular, our assembly language features labels, arbitrary conditional and unconditional jumps to labels, global data and instructions for moving this data into the MCS-51's single 16-bit register.
543Expanding these pseudoinstructions into machine code instructions is not trivial, and the proof that the assembly process is `correct', in that the semantics of a subset of assembly programs are not changed is complex.
544
545The formalisation is a key component of the CerCo project, which aims to produce a verified concrete complexity preserving compiler for a large subset of the C programming language.
546The verified assembler, complete with the underlying formalisation of the semantics of MCS-51 machine code, will form the bedrock layer upon which the rest of the CerCo project will build its verified compiler platform.
547
548It is interesting to compare our work to an `industrial grade' assembler for the MCS-51: SDCC~\cite{sdcc:2011}.
549SDCC is the only open source C compiler that targets the MCS-51 instruction set.
550It appears that all pseudojumps in SDCC assembly are expanded to \texttt{LJMP} instructions, the worst possible jump expansion policy from an efficiency point of view.
551Note that this policy is the only possible policy \emph{in theory} that can preserve the semantics of an assembly program during the assembly process.
552However, this comes at the expense of assembler completeness: the generated program may be too large to fit into code memory.
553In this respect, there is a trade-off between the completeness of the assembler and the efficiency of the assembled program.
554The definition and proof of a terminating, correct jump expansion policy is described in a companion publication to this one~\cite{boender:correctness:2012}.
555
556Aside from their application in verified compiler projects such as CerCo and CompCert, verified assemblers such as ours could also be applied to the verification of operating system kernels.
557Of particular note is the verified seL4 kernel~\cite{klein:sel4:2009,klein:sel4:2010}.
558This verification explicitly assumes the existence of, amongst other things, a trustworthy assembler and compiler.
559
560Note that both CompCert and the seL4 formalisation assume the existence of `trustworthy' assemblers.
561The observation that an optimising assembler cannot preserve the semantics of every assembly program may have important consequences for these projects.
562If CompCert chooses to assume the existence of an optimising assembler, then care should be made to ensure that any assembly program produced by the CompCert compiler falls into the subset of programs that have a hope of having their semantics preserved by an optimising assembler.
563
564Our formalisation exploits dependent types in different ways and for multiple purposes.
565The first purpose is to reduce potential errors in the formalisation of the microprocessor.
566In particular, dependent types are used to constraint the size of bitvectors and tries that represent memory quantities and memory areas respectively.
567They are also used to simulate polymorphic variants in Matita, in order to provide precise typings to various functions expecting only a subset of all possible addressing modes than the MCS-51 offers.
568Polymorphic variants nicely capture the absolutely unorthogonal instruction set of the MCS-51 where every opcode must accept its own subset of the 11 addressing mode of the processor.
569
570The second purpose is to single out the sources of incompleteness.
571By abstracting our functions over the dependent type of correct policies, we were able to manifest the fact that the compiler never refuses to compile a program where a correct policy exists.
572This also allowed to simplify the initial proof by dropping lemmas establishing that one function fails if and only if some previous function does so.
573
574Finally, dependent types, together with Matita's liberal system of coercions, allow us to simulate almost entirely---in user space---the proof methodology ``Russell'' of Sozeau~\cite{sozeau:subset:2006}.
575However, not every proof has been carried out in this way: we only used this style to prove that a function satisfies a specification that only involves that function in a significant way.
576For example, it would be unnatural to see the proof that fetch and assembly commute as the specification of one of the two functions.
577
578\subsection{Related work}
579\label{subsect.related.work}
580
581% piton
582We are not the first to consider the total correctness of an assembler for a non-trivial assembly language.
583Perhaps the most impressive piece of work in this domain is the Piton stack~\cite{moore:piton:1996,moore:grand:2005}.
584This was a stack of verified components, written and verified in ACL2, ranging from a proprietary FM9001 microprocessor verified at the gate level, to assemblers and compilers for two high-level languages---a dialect of Lisp and $\mu$Gypsy~\cite{moore:grand:2005}.
585
586% jinja
587Klein and Nipkow consider a Java-like programming language, Jinja~\cite{klein:machine:2006,klein:machine:2010}.
588They provide a compiler, virtual machine and operational semantics for the programming language and virtual machine, and prove that their compiler is semantics and type preserving.
589
590We believe some other verified assemblers exist in the literature.
591However, what sets our work apart from that above is our attempt to optimise the machine code generated by our assembler.
592This complicates any formalisation effort, as an attempt at the best possible selection of machine instructions must be made, especially important on a device such as the MCS-51 with a minuscule code memory.
593Further, care must be taken to ensure that the time properties of an assembly program are not modified by the assembly process lest we affect the semantics of any program employing the MCS-51's I/O facilities.
594This is only possible by inducing a cost model on the source code from the optimisation strategy and input program.
595This will be a \emph{leit motif} of CerCo.
596
597\subsection{Resources}
598\label{subsect.resources}
599
600All files relating to our formalisation effort can be found online at~\url{http://cerco.cs.unibo.it}.
601In particular, we have assumed several properties of ``library functions'' related in particular to modular arithmetic and datastructure manipulation.
602Moreover, we have axiomatised various ancillary functions needed to complete the main theorems, as well as some `routine' proof obligations of the theorems themselves, preferring instead to focus on the main meat of the theorems.
603We thus believe that the proof strategy is sound and that we will be able to close soon all axioms, up to possible minor bugs that should have local fixes that do not affect the global proof strategy.
604
605The development, including the definition of the executable semantics of the MCS-51, is spread across 29 files, totalling around 18,500 lines of Matita source.
606The bulk of the proof described herein is contained in a series of files, \texttt{AssemblyProof.ma}, \texttt{AssemblyProofSplit.ma} and \texttt{AssemblyProofSplitSplit.ma} consisting at the moment of approximately 4200 lines of Matita source.
607Numerous other lines of proofs are spread all over the development because of dependent types and the Russell proof style, which does not allow one to separate the code from the proofs.
608The low ratio between the number of lines of code and the number of lines of proof is unusual.
609It is justified by the fact that the pseudo-assembly and the assembly language share most constructs and that large parts of the semantics are also shared.
610Therefore many lines of code are required to describe the complex semantics of the processor, but, for the shared cases, the proof of preservation of the semantics is essentially trivial.
611
612\bibliography{cpp-2012-asm.bib}
613
614\end{document}\renewcommand{\verb}{\lstinline}
615\def\lstlanguagefiles{lst-grafite.tex}
616\lstset{language=Grafite}
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