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37 | \title{On the correctness of an assembler for the Intel MCS-51 microprocessor\thanks{The project CerCo acknowledges the financial support of the Future and Emerging Technologies (FET) programme within the Seventh Framework Programme for Research of the European Commission, under FET-Open grant number: 243881}} |
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38 | \author{Dominic P. Mulligan \and Claudio Sacerdoti Coen} |
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39 | \institute{Dipartimento di Scienze dell'Informazione, Universit\'a di Bologna} |
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40 | |
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41 | \bibliographystyle{splncs03} |
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42 | |
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43 | \begin{document} |
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44 | |
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45 | \maketitle |
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46 | |
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47 | \begin{abstract} |
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48 | We consider the formalisation of an assembler for Intel MCS-51 assembly language in the Matita proof assistant. |
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49 | This formalisation forms a major component of the EU-funded CerCo project, concering the construction and formalisation of a concrete complexity preserving compiler for a large subset of the C programming language. |
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50 | |
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51 | The efficient expansion of pseudoinstructions---particularly jumps---into MCS-51 machine instructions is complex. |
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52 | We employ a strategy, involving the use of `policies', that separates the decision making over how jumps should be expanded from the expansion process itself. |
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53 | This makes the proof of correctness for the assembler significantly more straightforward. |
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54 | |
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55 | We prove, under the assumption of the existence of a correct policy, that the assembly process never fails and preserves the semantics of a subset of assembly programs. |
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56 | Correct policies fail to exist only in a limited number of pathological circumstances. |
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57 | Our assembler is complete with respect to the choice of policy. |
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58 | |
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59 | Surprisingly, we observe that it is impossible for an optimising assembler to preserve the semantics of every assembly program. |
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60 | \end{abstract} |
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61 | |
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62 | % ---------------------------------------------------------------------------- % |
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63 | % SECTION % |
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64 | % ---------------------------------------------------------------------------- % |
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65 | \section{Introduction} |
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66 | \label{sect.introduction} |
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67 | |
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68 | We consider the formalisation of an assembler for the Intel MCS-51 8-bit microprocessor in the Matita proof assistant~\cite{asperti:user:2007}. |
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69 | This formalisation forms a major component of the EU-funded CerCo project~\cite{cerco:2011}, concering the construction and formalisation of a concrete complexity preserving compiler for a large subset of the C programming language. |
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70 | |
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71 | The MCS-51 dates from the early 1980s and is commonly called the 8051/8052. |
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72 | Despite the microprocessor's age, derivatives are still widely manufactured by a number of semiconductor foundries. |
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73 | As a result the processor is widely used, especially in embedded systems development, where well-tested, cheap, predictable microprocessors find their niche. |
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74 | |
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75 | The MCS-51 has a relative paucity of features compared to its more modern brethren. |
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76 | In particular, the MCS-51 does not possess a cache or any instruction pipelining that would make predicting the concrete cost of executing a single instruction an involved process. |
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77 | Instead, each semiconductor foundry that produces an MCS-51 derivative is able to provide accurate timing information in clock cycles for each instruction in their derivative's instruction set. |
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78 | It is important to stress that this timing information, unlike in more sophisticated processors, is not an estimate, it is a definition. |
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79 | For the MCS-51, if a manufacturer states that a particular opcode takes three clock cycles to execute, then that opcode \emph{always} takes three clock cycles to execute. |
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80 | |
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81 | This predicability of timing information is especially attractive to the CerCo consortium. |
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82 | We are in the process of constructing a certified, concrete complexity compiler for a realistic processor, and not for building and formalising the worst case execution time (WCET) tools that would be necessary to achieve the same result with, for example, a modern ARM or PowerPC microprocessor. |
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83 | |
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84 | However, the MCS-51's paucity of features is a double edged sword. |
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85 | In particular, the MCS-51 features relatively miniscule memory spaces (including read-only code memory, stack and internal/external random access memory) by modern standards. |
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86 | As a result our compiler, to have any sort of hope of successfully compiling realistic C programs, ought to produce `tight' machine code. |
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87 | This is not simple and requires the use of optimisations. |
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88 | |
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89 | For example, the MCS-51 features three unconditional jump instructions: \texttt{LJMP} and \texttt{SJMP}---`long jump' and `short jump' respectively---and an 11-bit oddity of the MCS-51, \texttt{AJMP}. |
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90 | Each of these three instructions expects arguments in different sizes and behaves in different ways: \texttt{SJMP} may only perform a `local jump'; \texttt{LJMP} may jump to any address in the MCS-51's memory space and \texttt{AJMP} may jump to any address in the current memory page. |
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91 | Consequently, the size of each opcode is different, and to squeeze as much code as possible into the MCS-51's limited code memory, the smallest possible opcode should be selected. |
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92 | |
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93 | The prototype CerCo C compiler does not attempt to select the smallest jump opcode in this manner, as this was thought to unneccessarily complicate the compilation chain. |
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94 | Instead, the compiler targets an assembly language, complete with pseudoinstructions including bespoke \texttt{Jmp} and \texttt{Call} instructions. |
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95 | Labels, conditional jumps to labels, a program preamble containing global data and a \texttt{MOV} instruction for moving this global data into the MCS-51's one 16-bit register also feature. |
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96 | This latter feature will ease any later consideration of separate compilation in the CerCo compiler. |
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97 | An assembler is used to expand pseudoinstructions into MCS-51 machine code. |
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98 | |
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99 | However, this assembly process is not trivial, for numerous reasons. |
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100 | For example, our conditional jumps to labels behave differently from their machine code counterparts. |
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101 | At the machine code level, all conditional jumps are `short', limiting their range. |
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102 | However, at the assembly level, conditional jumps may jump to a label that appears anywhere in the program, significantly liberalising the use of conditional jumps and further simplifying the design of the CerCo compiler. |
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103 | |
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104 | Further, trying to na\"ively relate assembly programs with their machine code counterparts simply does not work. |
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105 | Machine code programs that fetch from constant addresses in code memory or programs that combine the program counter with constant shifts do not make sense at the assembly level, since the position of instructions in code memory will be known only after assembly and optimisation. |
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106 | More generally, memory addresses can only be compared with other memory addresses. |
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107 | However, checking that memory addresses are only compared against each other at the assembly level is in fact undecidable. |
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108 | In short, we come to the shocking realisation that, with optimisations, the full preservation of the semantics of the two languages is impossible. |
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109 | We believe that this revelation is significant for large formalisation projects that assume the existence of a correct assembler. |
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110 | Projects in this class include both the recent CompCert~\cite{compcert:2011,leroy:formal:2009} and seL4 formalisations~\cite{klein:sel4:2009}. |
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111 | |
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112 | Yet, the situation is even more complex than having to expand pseudoinstructions correctly. |
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113 | In particular, when formalising the assembler, we must make sure that the assembly process does not change the timing characteristics of an assembly program for two reasons. |
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114 | First, the semantics of some functions of the MCS-51, notably I/O, depend on the microprocessor's clock. |
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115 | Changing how long a particular program takes to execute can affect the semantics of a program. |
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116 | This is undesirable. |
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117 | |
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118 | Second, as mentioned, the CerCo consortium is in the business of constructing a verified compiler for the C programming language. |
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119 | However, unlike CompCert~\cite{compcert:2011,leroy:formal:2009,leroy:formally:2009}---which currently represents the state of the art for `industrial grade' verified compilers---CerCo considers not just the \emph{extensional correctness} of the compiler, but also its \emph{intensional correctness}. |
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120 | That is, CompCert focusses solely on the preservation of the \emph{meaning} of a program during the compilation process, guaranteeing that the program's meaning does not change as it is gradually transformed into assembly code. |
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121 | However in any realistic compiler (even the CompCert compiler!) there is no guarantee that the program's time properties are preserved during the compilation process; a compiler's `optimisations' could, in theory, even conspire to degrade the concrete complexity of certain classes of programs. |
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122 | CerCo aims to expand the current state of the art by producing a compiler where this temporal degradation is guaranteed not to happen. |
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123 | Moreover, CerCo's approach lifts a program's timing information to the source (C language) level, wherein the programmer can reason about a program's intensional properties by directly examining the source code that they write. |
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124 | |
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125 | In order to achieve this CerCo imposes a cost model on programs, or more specifically, on simple blocks of instructions. |
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126 | This cost model is induced by the compilation process itself, and its non-compositional nature allows us to assign different costs to identical blocks of instructions depending on how they are compiled. |
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127 | In short, we aim to obtain a very precise costing for a program by embracing the compilation process, not ignoring it. |
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128 | This, however, complicates the proof of correctness for the compiler proper: for every translation pass from intermediate language to intermediate language, we must prove that not only has the meaning of a program been preserved, but also its complexity characteristics. |
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129 | This also applies for the translation from assembly language to machine code. |
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130 | |
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131 | How do we assign a cost to a pseudoinstruction? |
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132 | As mentioned, conditional jumps at the assembly level can jump to a label appearing anywhere in the program. |
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133 | However, at the machine code level, conditional jumps are limited to jumping `locally', using a measly byte offset. |
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134 | To translate a jump to a label, a single conditional jump pseudoinstruction may be translated into a block of three real instructions, as follows (here, \texttt{JZ} is `jump if accumulator is zero'): |
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135 | \begin{displaymath} |
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136 | \begin{array}{r@{\quad}l@{\;\;}l@{\qquad}c@{\qquad}l@{\;\;}l} |
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137 | & \mathtt{JZ} & label & & \mathtt{JZ} & \text{size of \texttt{SJMP} instruction} \\ |
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138 | & \ldots & & \text{translates to} & \mathtt{SJMP} & \text{size of \texttt{LJMP} instruction} \\ |
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139 | label: & \mathtt{MOV} & \mathtt{A}\;\;\mathtt{B} & \Longrightarrow & \mathtt{LJMP} & \text{address of \textit{label}} \\ |
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140 | & & & & \ldots & \\ |
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141 | & & & & \mathtt{MOV} & \mathtt{A}\;\;\mathtt{B} |
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142 | \end{array} |
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143 | \end{displaymath} |
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144 | In the translation, if \texttt{JZ} fails, we fall through to the \texttt{SJMP} which jumps over the \texttt{LJMP}. |
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145 | Naturally, if \textit{label} is close enough, a conditional jump pseudoinstruction is mapped directly to a conditional jump machine instruction; the above translation only applies if \textit{label} is not sufficiently local. |
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146 | This leaves the problem, addressed below, of calculating whether a label is indeed `close enough' for the simpler translation to be used. |
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147 | |
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148 | Crucially, the above translation demonstrates the difficulty in predicting how many clock cycles a pseudoinstruction will take to execute. |
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149 | A conditional jump may be mapped to a single machine instruction or a block of three. |
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150 | Perhaps more insidious, the number of cycles needed to execute the instructions in the two branches of a translated conditional jump may be different. |
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151 | Depending on the particular MCS-51 derivative at hand, an \texttt{SJMP} could in theory take a different number of clock cycles to execute than an \texttt{LJMP}. |
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152 | These issues must also be dealt with in order to prove that the translation pass preserves the concrete complexity of the code, and that the semantics of a program using the MCS-51's I/O facilities does not change. |
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153 | We address this problem by parameterizing the semantics over a cost model. |
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154 | We prove the preservation of concrete complexity only for the program-dependent cost model induced by the optimisation. |
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155 | |
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156 | The question remains: how do we decide whether to expand a jump into an \texttt{SJMP} or an \texttt{LJMP}? |
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157 | To understand why this problem is not trivial, consider the following snippet of assembly code: |
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158 | \begin{displaymath} |
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159 | \begin{array}{r@{\qquad}r@{\quad}l@{\;\;}l@{\qquad}l} |
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160 | \text{1:} & \mathtt{0x000} & \texttt{LJMP} & \texttt{0x100} & \text{\texttt{;; Jump forward 256.}} \\ |
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161 | \text{2:} & \mathtt{...} & \mathtt{...} & & \\ |
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162 | \text{3:} & \mathtt{0x0FA} & \texttt{LJMP} & \texttt{0x100} & \text{\texttt{;; Jump forward 256.}} \\ |
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163 | \text{4:} & \mathtt{...} & \mathtt{...} & & \\ |
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164 | \text{5:} & \mathtt{0x100} & \texttt{LJMP} & \texttt{0x100} & \text{\texttt{;; Jump forward 256.}} \\ |
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165 | \text{6:} & \mathtt{...} & \mathtt{...} & & \\ |
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166 | \text{7:} & \mathtt{0x1F9} & \texttt{LJMP} & \texttt{-0x300} & \text{\texttt{;; Arbitrary instruction.}} \\ |
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167 | \end{array} |
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168 | \end{displaymath} |
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169 | We observe that $100_{16} = 256_{10}$, and lies \emph{just} outside the range expressible in an 8-bit byte (0--255). |
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170 | |
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171 | As our example shows, given an occurence $l$ of an \texttt{LJMP} instruction, it may be possible to shrink $l$ to an occurence of an \texttt{SJMP}---consuming fewer bytes of code memory---provided we can shrink any \texttt{LJMP}s that exist between $l$ and its target location. |
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172 | In particular, if we can somehow shrink the \texttt{LJMP} occurring at line 5, the \texttt{LJMP}s occurring at lines 1 and 3 above may both be replaced by \texttt{SJMP}s, provided that \emph{both} jumps at 1 and 3 are replaced at the same time. |
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173 | Thinking more, it is easy to imagine knotty, circular configurations of jumps developing, each jump occurrence only being shrinkable if every other is. |
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174 | Finding a solution to this `shrinking jumps' problem then involves us finding a method to break any vicious circularities that develop. |
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175 | |
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176 | How we went about resolving this problem affected the shape of our proof of correctness for the whole assembler in a rather profound way. |
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177 | We first attempted to synthesize a solution bottom up: starting with no solution, we gradually refine a solution using the same functions that implement the jump expansion. |
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178 | Using this technique, solutions can fail to exist, and the proof quickly descends into a diabolical quagmire. |
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179 | |
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180 | Abandoning this attempt, we instead split the `policy'---the decision over how any particular jump should be expanded---from the implementation that actually expands assembly programs into machine code. |
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181 | Assuming the existence of a correct policy, we proved the implementation of the assembler correct. |
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182 | Further, we proved that the assembler fails to assemble an assembly program if and only if a correct policy does not exist. |
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183 | Policies do not exist in only a limited number of circumstances: namely, if a pseudoinstruction attempts to jump to a label that does not exist, or the program is too large to fit in code memory. |
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184 | The first case would constitute a serious compiler error, and hopefully certifying the rest of the compiler would rule this possibility out. |
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185 | The second case is unavoidable---certified compiler or not, trying to load a huge program into a small code memory will break \emph{something}. |
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186 | |
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187 | The rest of this paper is a detailed description of this proof. |
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188 | |
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189 | % ---------------------------------------------------------------------------- % |
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190 | % SECTION % |
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191 | % ---------------------------------------------------------------------------- % |
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192 | \subsection{Overview of the paper} |
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193 | \label{subsect.overview.of.the.paper} |
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194 | In Section~\ref{sect.matita} we provide a brief overview of the Matita proof assistant for the unfamiliar reader. |
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195 | In Section~\ref{sect.the.proof} we discuss the design and implementation of the proof proper. |
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196 | In Section~\ref{sect.conclusions} we conclude. |
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197 | |
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198 | % ---------------------------------------------------------------------------- % |
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199 | % SECTION % |
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200 | % ---------------------------------------------------------------------------- % |
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201 | \section{Matita} |
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202 | \label{sect.matita} |
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203 | |
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204 | Matita is a proof assistant based on the Calculus of (Co)inductive Constructions~\cite{asperti:user:2007}. |
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205 | For those familiar with Coq, Matita's syntax and mode of operation should be entirely familiar. |
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206 | However, we take time here to explain one of Matita's syntactic idiosyncrasies. |
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207 | The use of `$\mathtt{?}$' or `$\mathtt{\ldots}$' in an argument position denotes a term or terms to be inferred automatically by unification, respectively. |
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208 | The use of `$\mathtt{?}$' in the body of a definition, lemma or axiom denotes an incomplete term that is to be closed, by hand, using tactics. |
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209 | |
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210 | % ---------------------------------------------------------------------------- % |
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211 | % SECTION % |
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212 | % ---------------------------------------------------------------------------- % |
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213 | \section{The proof} |
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214 | \label{sect.the.proof} |
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215 | |
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216 | \subsection{The assembler and semantics of machine code} |
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217 | \label{subsect.the.assembler.and.semantics.of.machine.code} |
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218 | |
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219 | The formalisation in Matita of the semantics of MCS-51 machine code is described in~\cite{mulligan:executable:2011}. |
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220 | We merely describe enough here to understand the rest of the proof. |
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221 | |
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222 | At heart, the MCS-51 emulator centres around a \texttt{Status} record, describing the current state of the microprocessor. |
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223 | This record contains fields corresponding to the microprocessor's program counter, special function registers, and so on. |
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224 | At the machine code level, code memory is implemented as a trie of bytes, addressed by the program counter. |
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225 | Machine code programs are loaded into \texttt{Status} using the \texttt{load\_code\_memory} function. |
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226 | |
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227 | We may execut a single step of a machine code program using the \texttt{execute\_1} function, which returns an updated \texttt{Status}: |
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228 | \begin{lstlisting} |
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229 | definition execute_1: Status $\rightarrow$ Status := $\ldots$ |
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230 | \end{lstlisting} |
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231 | The function \texttt{execute} allows one to execute an arbitrary, but fixed (due to Matita's normalisation requirement!) number of steps of a program. |
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232 | |
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233 | Naturally, assembly programs have analogues. |
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234 | The counterpart of the \texttt{Status} record is \texttt{PseudoStatus}. |
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235 | Instead of code memory being implemented as tries of bytes, code memory is here implemented as lists of pseudoinstructions, and program counters are merely indices into this list. |
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236 | In actual fact, both \texttt{Status} and \texttt{PseudoStatus} are both specialisations of the same \texttt{PreStatus} record, parametric in the representation of code memory. |
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237 | This allows us to share some code that is common to both records (for instance, `setter' and `getter' functions). |
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238 | A further benefit of this sharing is that those instructions that are completely ambivalent about the particular representation of code memory can be factored out into their own type. |
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239 | |
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240 | Our analogue of \texttt{execute\_1} is \texttt{execute\_1\_pseudo\_instruction}: |
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241 | \begin{lstlisting} |
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242 | definition execute_1_pseudo_instruction: (Word $\rightarrow$ nat $\times$ nat) $\rightarrow$ |
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243 | PseudoStatus $\rightarrow$ PseudoStatus := $\ldots$ |
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244 | \end{lstlisting} |
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245 | Notice, here, that the emulation function for assembly programs takes an additional argument. |
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246 | This is a function that maps program counters (at the assembly level) to pairs of natural numbers representing the number of clock ticks that the pseudoinstruction needs to execute, post expansion. |
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247 | We call this function a \emph{costing}, and note that the costing is induced by the particular strategy we use to expand pseudoinstructions. |
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248 | If we change how we expand conditional jumps to labels, for instance, then the costing needs to change, hence \texttt{execute\_1\_pseudo\_instruction}'s parametricity in the costing. |
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249 | |
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250 | The costing returns \emph{pairs} of natural numbers because, in the case of expanding conditional jumps to labels, the expansion of the `true branch' and `false branch' may differ in the number of clock ticks needed for execution. |
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251 | This timing information is used inside \texttt{execute\_1\_pseudo\_instruction} to update the clock of the \texttt{PseudoStatus}. |
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252 | During the proof of correctness of the assembler we relate the clocks of \texttt{Status}es and \texttt{PseudoStatus}es for the policy induced by the cost model and optimisations. |
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253 | |
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254 | The assembler, mapping programs consisting of lists of pseudoinstructions to lists of bytes, operates in a mostly straightforward manner. |
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255 | To a degree of approximation, the assembler on an assembly program, consisting of $n$ pseudoinstructions $\mathtt{P_i}$ for $1 \leq i \leq n$, works as in the following diagram (we use $-^{*}$ to denote a combined map and flatten operation): |
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256 | \begin{displaymath} |
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257 | [\mathtt{P_1}, \ldots \mathtt{P_n}] \xrightarrow{\left(\mathtt{P_i} \xrightarrow{\mbox{\fontsize{7}{9}\selectfont$\mathtt{expand\_pseudo\_instruction}$}} \mathtt{[I_1^i, \ldots I^q_i]} \xrightarrow{\mbox{\fontsize{7}{9}\selectfont$\mathtt{~~~~~~~~assembly1^{*}~~~~~~~~}$}} \mathtt{[0110]}\right)^{*}} \mathtt{[010101]} |
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258 | \end{displaymath} |
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259 | Here $\mathtt{I^i_j}$ for $1 \leq j \leq q$ are the $q$ machine code instructions obtained by expanding, with \texttt{expand\_pseudo\_instruction}, a single pseudoinstruction. |
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260 | Each machine code instruction $\mathtt{I^i_j}$ is then assembled, using the \texttt{assembly1} function, into a list of bytes. |
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261 | This process is iterated for each pseudoinstruction, before the lists are flattened into a single bit list representation of the original assembly program. |
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262 | |
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263 | By inspecting the above diagram, it would appear that the best way to proceed with a proof that the assembly process does not change the semantics of an assembly program is via a decomposition of the problem into two subproblems. |
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264 | Namely, we first expand any and all pseudoinstructions into lists of machine instructions, and provide a proof that this process does not change our program's semantics. |
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265 | Finally, we assemble all machine code instructions into machine code---lists of bytes---and prove once more that this process does not have an adverse effect on a program's semantics. |
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266 | By composition, we then have that the whole assembly process is semantics preserving. |
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267 | |
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268 | %This is a tempting approach to the proof, but ultimately the wrong approach. |
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269 | %In particular, it is important that we track how the program counter indexing into the assembly program, and the machine's program counter evolve, so that we can relate them. |
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270 | %Expanding pseudoinstructions requires that the machine's program counter be incremented by $n$ steps, for $1 \leq n$, for every increment of the assembly program's program counter. |
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271 | %Keeping track of the correspondence between the two program counters quickly becomes unfeasible using a compositional approach, and hence the proof must be monolithic. |
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272 | |
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273 | % ---------------------------------------------------------------------------- % |
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274 | % SECTION % |
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275 | % ---------------------------------------------------------------------------- % |
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276 | \subsection{Policies} |
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277 | \label{subsect.policies} |
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278 | |
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279 | Policies exist to dictate how conditional and unconditional jumps at the assembly level should be expanded into machine code instructions. |
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280 | Using policies, we are able to completely decouple the decision over how jumps are expanded with the act of expansion, simplifying our proofs. |
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281 | As mentioned, the MCS-51 instruction set includes three different jump instructions: \texttt{SJMP}, \texttt{AJMP} and \texttt{LJMP}; call these `short', `medium' and `long' jumps, respectively: |
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282 | \begin{lstlisting} |
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283 | inductive jump_length: Type[0] := |
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284 | | short_jump: jump_length |
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285 | | medium_jump: jump_length |
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286 | | long_jump: jump_length. |
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287 | \end{lstlisting} |
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288 | A \texttt{jump\_expansion\_policy} is a map from \texttt{Word}s to \texttt{jump\_length}s, implemented as a trie. |
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289 | Intuitively, a policy maps positions in a program (indexed using program counters implemented as \texttt{Word}s) to a particular variety of jump. |
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290 | \begin{lstlisting} |
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291 | definition jump_expansion_policy := BitVectorTrie jump_length 16. |
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292 | \end{lstlisting} |
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293 | Next, we require a series of `sigma' functions. |
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294 | These functions map assembly program counters to their machine code counterparts, establishing the correspondence between `positions' in an assembly program and `positions' in a machine code program. |
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295 | At the heart of this process is \texttt{sigma0} which traverses an assembly program building maps from program counter to program counter. |
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296 | This function fails if and only if an internal call to \texttt{assembly\_1\_pseudoinstruction} fails: |
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297 | \begin{lstlisting} |
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298 | definition sigma0: pseudo_assembly_program |
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299 | $\rightarrow$ option (nat $\times$ (nat $\times$ (BitVectorTrie Word 16))) := $\ldots$ |
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300 | \end{lstlisting} |
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301 | We eventually lift this to functions from program counters to program counters: |
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302 | \begin{lstlisting} |
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303 | definition sigma_safe: |
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304 | pseudo_assembly_program $\rightarrow$ option (Word $\rightarrow$ Word) := $\ldots$ |
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305 | \end{lstlisting} |
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306 | Now, it's possible to define what a `good policy' is i.e. one that does not cause \texttt{sigma\_safe} to fail. |
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307 | As mentioned, \texttt{sigma\_safe} can only fail if an assembly program fails to be assembled: |
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308 | \begin{lstlisting} |
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309 | definition policy_ok := $\lambda$p. sigma_safe p $\neq$ None $\ldots$. |
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310 | \end{lstlisting} |
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311 | Finally, we obtain \texttt{sigma}, a map from program counters to program counters, which is guranteed not to fail as we internally provide a that |
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312 | \begin{lstlisting} |
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313 | definition sigma: pseudo_assembly_program $\rightarrow$ Word $\rightarrow$ Word := $\ldots$ |
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314 | \end{lstlisting} |
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315 | |
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316 | % ---------------------------------------------------------------------------- % |
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317 | % SECTION % |
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318 | % ---------------------------------------------------------------------------- % |
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319 | \subsection{Total correctness of the assembler} |
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320 | \label{subsect.total.correctness.of.the.assembler} |
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321 | |
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322 | Using our policies, we now work toward proving the total correctness of the assembler. |
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323 | By total correctness, we mean that the assembly process does not change the semantics of an assembly program. |
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324 | Naturally, this necessitates keeping some sort of correspondence between program counters at the assembly level, and program counters at the machine code level. |
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325 | For this, we use the \texttt{sigma} machinery defined at the end of Subsection~\ref{subsect.policies}. |
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326 | |
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327 | We expand pseudoinstructions using the function \texttt{expand\_pseudo\_instruction}. |
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328 | This function accepts a `policy decision'---an element of type \texttt{jump\_length}---that is used when expanding a \texttt{Call}, \texttt{Jmp} or conditional jump to a label into the correct machine instruction. |
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329 | This \texttt{policy\_decision} is asssumed to originate from a policy as defined in Subsection~\ref{subsect.policies}. |
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330 | \begin{lstlisting} |
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331 | definition expand_pseudo_instruction: |
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332 | ∀lookup_labels, lookup_datalabels, pc, policy_decision. |
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333 | pseudo_instruction $\rightarrow$ option list instruction := $\ldots$ |
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334 | \end{lstlisting} |
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335 | Under the assumption that a correct policy exists, \texttt{expand\_pseudo\_instruction} should never fail, and therefore the option type may be dispensed with. |
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336 | This is because the only failure conditions for \texttt{expand\_pseudo\_instruction} result from trying to expand a pseudoinstruction into an `impossible' combination of machine code instructions. |
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337 | For instance, if the policy decision dictates that we should expand a \texttt{Call} pseudoinstruction into a `short jump', then we fail, as the MCS-51's instruction set only features instructions \texttt{ACALL} and \texttt{LCALL}. |
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338 | |
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339 | % dpm todo |
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340 | \begin{lstlisting} |
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341 | axiom assembly_ok: ∀program,assembled,costs,labels. |
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342 | Some $\ldots$ $\langle$labels, costs$\rangle$ = build_maps program $\rightarrow$ |
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343 | Some $\ldots$ $\langle$assembled, costs$\rangle$ = assembly program $\rightarrow$ |
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344 | let code_memory := load_code_memory assembled in |
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345 | let preamble := $\pi_1$ program in |
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346 | let datalabels := construct_datalabels preamble in |
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347 | let lk_labels := |
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348 | $\lambda$x. sigma program (address_of_word_labels_code_mem ($\pi_2$ program) x) in |
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349 | let lk_dlabels := $\lambda$x. lookup ? ? x datalabels (zero ?) in |
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350 | ∀ppc,len,assembledi. |
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351 | let $\langle$pi, newppc$\rangle$ := fetch_pseudo_instruction ($\pi_2$ program) ppc in |
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352 | let assembly' := assembly_1_pseudoinstruction program ppc |
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353 | (sigma program ppc) lk_labels lk_dlabels pi in |
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354 | let newpc := (sigma program ppc) + len in |
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355 | let echeck := |
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356 | encoding_check code_memory (sigma program ppc) slen assembledi in |
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357 | Some $\ldots$ $\langle$len, assembledi$\rangle$ = assembly' $\rightarrow$ |
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358 | echeck $\wedge$ sigma program newppc = newpc. |
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359 | \end{lstlisting} |
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360 | |
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361 | % dpm todo |
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362 | \begin{lstlisting} |
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363 | theorem fetch_assembly: $\forall$pc, i, cmem, assembled. |
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364 | assembled = assembly1 i $\rightarrow$ |
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365 | let len := length $\ldots$ assembled in |
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366 | encoding_check cmem pc (pc + len) assembled $\rightarrow$ |
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367 | let fetched := fetch code_memory (bitvector_of_nat $\ldots$ pc) in |
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368 | let $\langle$instr_pc, ticks$\rangle$ := fetched in |
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369 | let $\langle$instr, pc'$\rangle$ := instr_pc in |
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370 | (eq_instruction instr i $\wedge$ |
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371 | eqb ticks (ticks_of_instruction instr) $\wedge$ |
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372 | eq_bv $\ldots$ pc' (pc + len)) = true. |
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373 | \end{lstlisting} |
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374 | |
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375 | Lemma \texttt{fetch\_assembly\_pseudo} establishes a basic relationship between \texttt{expand\_pseudo\_instruction} and \texttt{assembly\_1\_pseudoinstruction}: |
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376 | \begin{lstlisting} |
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377 | lemma fetch_assembly_pseudo: $\forall$program, ppc, lk_labels, lk_dlabels. |
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378 | $\forall$pi, code_memory, len, assembled, instructions, pc. |
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379 | let jexp := jump_expansion ppc program in |
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380 | let exp := |
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381 | expand_pseudo_instruction lk_labels lk_dlabels pc jexp pi |
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382 | let ass := |
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383 | assembly_1_pseudoinstruction program ppc pc lk_labels lk_dlabels pi in |
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384 | Some ? instructions = exp $\rightarrow$ |
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385 | Some $\ldots$ $\langle$len, assembled$\rangle$ = ass $\rightarrow$ |
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386 | encoding_check code_memory pc (pc + len) assembled $\rightarrow$ |
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387 | fetch_many code_memory (pc + len) pc instructions. |
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388 | \end{lstlisting} |
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389 | Here, \texttt{len} is the number of machine code instructions the pseudoinstruction at hand has been expanded into, \texttt{encoding\_check} is a recursive function that checks for any possible corruption of the code memory, resulting from expanding the pseudoinstruction. |
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390 | We assemble a single pseudoinstruction with \texttt{assembly\_1\_pseudoinstruction}, which internally calls \texttt{jump\_expansion} and \texttt{expand\_pseudo\_instruction}. |
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391 | The function \texttt{fetch\_many} fetches multiple machine code instructions from code memory and performs some routine checks. |
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392 | |
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393 | Intuitively, Lemma \texttt{fetch\_assembly\_pseudo} can be read as follows. |
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394 | Suppose our policy \texttt{jump\_expansion} dictates that the pseudoinstruction indexed by the pseudo program counter \texttt{ppc} in assembly program \texttt{program} gives us the policy decision \texttt{jexp}. |
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395 | Further, suppose we expand the pseudoinstruction at \texttt{ppc} with the policy decision \texttt{jexp}, obtaining an (optional) list of machine code instructions \texttt{exp}. |
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396 | Suppose we also assemble the pseudoinstruction at \texttt{ppc} to obtain \texttt{ass}, a list of bytes. |
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397 | Then, under the assumption that neither the expansion of the pseudoinstruction to obtain \texttt{exp}, nor the assembly of the pseudoinstruction to obtain \texttt{ass}, failed, we check with \texttt{fetch\_many} that the number of machine instructions that were fetched matches the number of instruction that \texttt{expand\_pseudo\_instruction} expanded. |
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398 | |
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399 | At first sight, Lemma \texttt{fetch\_assembly\_pseudo2} appears to nearly establish the correctness of the assembler: |
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400 | \begin{lstlisting} |
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401 | lemma fetch_assembly_pseudo2: $\forall$program, assembled, costs, labels. |
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402 | Some $\ldots$ $\langle$labels, costs$\rangle$ = build_maps program $\rightarrow$ |
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403 | Some $\ldots$ $\langle$assembled, costs$\rangle$ = assembly program $\rightarrow$ $\forall$ppc. |
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404 | let code_memory := load_code_memory assembled in |
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405 | let preamble := $\pi_1$ program in |
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406 | let data_labels := construct_datalabels preamble in |
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407 | let lk_labels := |
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408 | λx. sigma program (address_of_word_labels_code_mem ($\pi_2$ program) x) in |
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409 | let lk_dlabels := λx. lookup ? ? x data_labels (zero ?) in |
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410 | let expansion := jump_expansion ppc program in |
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411 | let $\langle$pi, newppc$\rangle$ := fetch_pseudo_instruction ($\pi_2$ program) ppc in |
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412 | let ppc' := sigma program ppc in |
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413 | let newppc' := sigma program newppc in |
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414 | let instructions' := |
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415 | expand_pseudo_instruction lk_labels lk_dlabels ppc' expansion pi in |
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416 | let fetched := $\lambda$instr. fetch_many code_memory newppc' ppc' instr in |
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417 | $\exists$instrs. Some ? instrs = instructions' $\wedge$ fetched instrs. |
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418 | \end{lstlisting} |
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419 | Intuitively, we may read \texttt{fetch\_assembly\_pseudo2} as follows. |
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420 | Suppose we are able to successfully assemble an assembly program using \texttt{assembly} and produce a code memory, \texttt{code\_memory}. |
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421 | Then there exists some list of machine instructions equal to the expansion of a pseudoinstruction and the number of machine instructions that need to be fetched is equal to the number of machine instructions that the pseudoinstruction was expanded into. |
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422 | |
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423 | However, this property is \emph{not} strong enough to establish that the semantics of an assembly program has been preserved by the assembly process. |
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424 | In particular, \texttt{fetch\_assembly\_pseudo2} says nothing about how memory addresses evolve during assembly. |
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425 | Memory addresses in one memory space may be mapped to memory addresses in a completely different memory space during assembly. |
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426 | To handle this problem, we need some more machinery. |
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427 | |
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428 | We use an \texttt{internal\_pseudo\_address\_map} for this purpose. |
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429 | An \texttt{internal\_pseudo\_address\_map} associates positions in the memory of a \texttt{PseudoStatus} with a physical memory address: |
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430 | \begin{lstlisting} |
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431 | definition internal_pseudo_address_map := list (BitVector 8). |
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432 | \end{lstlisting} |
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433 | We use \texttt{internal\_pseudo\_address\_map}s to convert the lower internal RAM of a \texttt{PseudoStatus} into the lower internal RAM of a \texttt{Status}. |
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434 | The actual conversion process is performed by \texttt{low\_internal\_ram\_of\_pseudo\_low\_internal\_ram}:\footnote{An associated set of axioms describe how \texttt{low\_internal\_ram\_of\_pseudo\_low\_internal\_ram} behaves. This is a form of parametricity. We don't care about the particulars of the conversion functions, as long as they behave in accordance with our axioms.} |
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435 | |
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436 | \begin{lstlisting} |
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437 | axiom low_internal_ram_of_pseudo_low_internal_ram: |
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438 | internal_pseudo_address_map $\rightarrow$ BitVectorTrie Byte 7 $\rightarrow$ BitVectorTrie Byte 7. |
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439 | \end{lstlisting} |
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440 | A similar axiom exists for high internal RAM. |
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441 | |
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442 | Notice, the MCS-51's internal RAM is addressed with a 7-bit `byte'. |
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443 | % dpm: ugly English, fix |
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444 | The whole of the internal RAM space is addressed with bytes: the first bit is used to distinguish between the programmer addressing low and high internal memory. |
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445 | |
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446 | Next, we are able to translate \texttt{PseudoStatus} records into \texttt{Status} records using \texttt{status\_of\_pseudo\_status}. |
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447 | Translating a \texttt{PseudoStatus}'s code memory requires we expand pseudoinstructions and then assemble to obtain a trie of bytes. |
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448 | This can fail, as mentioned, in a limited number of situations, related to improper use of labels in an assembly program. |
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449 | However, it is possible to `tighten' the type of \texttt{status\_of\_pseudo\_status}, removing the option type, by using the fact that if any `good policy' exists, assembly will never fail. |
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450 | \begin{lstlisting} |
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451 | definition status_of_pseudo_status: |
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452 | internal_pseudo_address_map → PseudoStatus → option Status |
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453 | \end{lstlisting} |
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454 | After fetching an assembly instruction we must update any \texttt{internal\_pseudo\hyp{}\_address\_map}s that may be laying around. |
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455 | This is done with the following function: |
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456 | \begin{lstlisting} |
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457 | definition next_internal_pseudo_address_map: internal_pseudo_address_map |
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458 | $\rightarrow$ PseudoStatus $\rightarrow$ option internal_pseudo_address_map |
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459 | \end{lstlisting} |
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460 | Finally, we are able to state and prove our main theorem. |
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461 | This relates the execution of a single assembly instruction and the execution of (possibly) many machine code instructions. |
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462 | That is, the assembly process preserves the semantics of an assembly program, as it is translated into machine code: |
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463 | \begin{lstlisting} |
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464 | theorem main_thm: |
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465 | ∀M,M',ps,s,s''. |
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466 | next_internal_pseudo_address_map M ps = Some $\ldots$ M' $\rightarrow$ |
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467 | status_of_pseudo_status M ps = Some $\ldots$ s $\rightarrow$ |
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468 | status_of_pseudo_status M' |
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469 | (execute_1_pseudo_instruction |
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470 | (ticks_of (code_memory $\ldots$ ps)) ps) = Some $\ldots$ s'' $\rightarrow$ |
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471 | $\exists$n. execute n s = s''. |
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472 | \end{lstlisting} |
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473 | The statement can be given an intuitive reading as follows. |
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474 | Suppose our \texttt{PseudoStatus}, \texttt{ps}, can be successfully converted into a \texttt{Status}, \texttt{s}. |
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475 | Suppose further that, after executing a single assembly instruction and converting the resulting \texttt{PseudoStatus} into a \texttt{Status}, we obtain \texttt{s''}, being careful to track the number of ticks executed. |
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476 | Then, there exists some number \texttt{n}, so that executing \texttt{n} machine code instructions in \texttt{Status} \texttt{s} gives us \texttt{Status} \texttt{s''}. |
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477 | Theorem \texttt{main\_thm} establishes the correctness of the assembly process. |
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478 | |
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479 | % ---------------------------------------------------------------------------- % |
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480 | % SECTION % |
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481 | % ---------------------------------------------------------------------------- % |
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482 | \section{Conclusions} |
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483 | \label{sect.conclusions} |
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484 | |
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485 | We have proved the total correctness of an assembler for MCS-51 assembly language. |
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486 | In particular, our assembly language featured labels, arbitrary conditional and unconditional jumps to labels, global data and instructions for moving this data into the MCS-51's single 16-bit register. |
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487 | Expanding these pseudoinstructions into machine code instructions is not trivial, and the proof that the assembly process is `correct', in that the semantics of a subset of assembly programs are not changed is complex. |
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488 | Further, we have observed the `shocking' fact that any optimising assembler cannot preserve the semantics of all assembly programs. |
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489 | |
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490 | The formalisation is a key component of the CerCo project, which aims to produce a verified concrete complexity preserving compiler for a large subset of the C programming language. |
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491 | The verified assembler, complete with the underlying formalisation of the semantics of MCS-51 machine code (described fully in~\cite{mulligan:executable:2011}), will form the bedrock layer upon which the rest of the CerCo project will build its verified compiler platform. |
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492 | However, further work is needed. |
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493 | In particular, as it stands, the code produced by the prototype CerCo C compiler does not fall into the `semantics preserving' subset of assembly programs for our assembler. |
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494 | This is because the MCS-51 features a small stack space, and a larger stack is customarily manually emulated in external RAM. |
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495 | As a result, the majority of programs feature slices of memory addresses and program counters being moved in-and-out of external RAM via the registers, simulating the stack mechanism. |
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496 | At the moment, this movement is not tracked by \texttt{internal\_pseudo\_address\_map}, which only tracks the movement of memory addresses in low internal RAM. |
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497 | We leave extending this tracking of memory addresses throughout the whole of the MCS-51's address spaces as future work. |
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498 | |
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499 | Aside from their application in verified compiler projects such as CerCo and CompCert, verified assemblers such as ours could also be applied to the verification of operating system kernels. |
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500 | Of particular note is the verified seL4 kernel~\cite{klein:sel4:2009,klein:sel4:2010}. |
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501 | This verification explicitly assumes the existence of, amongst other things, a trustworthy assembler and compiler. |
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502 | |
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503 | We note here that both CompCert and the seL4 formalisation assume the existence of `trustworthy' assemblers. |
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504 | Our observation that an optimising assembler cannot preserve the semantics of every assembly program may have important consequences for these projects. |
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505 | In particular, if CompCert chooses to assume the existence of an optimising assembler, then care should be made to ensure that any assembly program produced by the CompCert C compiler falls into the class of assembly programs that have a hope of having their semantics preserved by an optimising assembler. |
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506 | |
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507 | In certain places in our formalisation (e.g. in proving \texttt{build\_maps} is correct) we made use of Matita's implementation of Russell~\cite{sozeau:subset:2006}. |
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508 | In Matita, Russell may be implemented using two coercions and some notational sugaring. |
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509 | % more |
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510 | |
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511 | \subsection{Related work} |
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512 | \label{subsect.related.work} |
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513 | |
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514 | % piton |
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515 | We are not the first to consider the total correctness of an assembler for a non-trivial assembly language. |
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516 | Perhaps the most impressive piece of work in this domain is the Piton stack~\cite{moore:piton:1996,moore:grand:2005}. |
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517 | This was a stack of verified components, written and verified in ACL2, ranging from a proprietary FM9001 microprocessor verified at the gate level, to assemblers and compilers for two high-level languages---a dialect of Lisp and $\mu$Gypsy~\cite{moore:grand:2005}. |
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518 | |
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519 | % jinja |
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520 | Klein and Nipkow consider a Java-like programming language, Jinja~\cite{klein:machine:2006,klein:machine:2010}. |
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521 | They provide a compiler, virtual machine and operational semantics for the programming language and virtual machine, and prove that their compiler is semantics and type preserving. |
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522 | |
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523 | We believe many other verified assemblers exist in the literature. |
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524 | However, what sets our work apart from that above is our attempt to optimise the machine code generated by our assembler. |
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525 | This complicates any formalisation effort, as the best possible selection of machine instructions must be made, especially important on a device such as the MCS-51 with a miniscule code memory. |
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526 | Further, care must be taken to ensure that the time properties of an assembly program are not modified by the assembly process lest we affect the semantics of any program employing the MCS-51's I/O facilities. |
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527 | |
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528 | Finally, mention of CerCo will invariably invite comparisons with CompCert~\cite{compcert:2011,leroy:formal:2009}, another verified compiler project closely related to CerCo. |
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529 | As previously mentioned, CompCert considers only extensional correctness of the compiler, and not intensional correctness, which CerCo focusses on. |
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530 | However, CerCo also extends CompCert in other ways. |
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531 | Namely, the CompCert verified compilation chain terminates at the PowerPC or ARM assembly level, and takes for granted the existence of a trustworthy assembler. |
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532 | CerCo chooses to go further, by considering a verified compilation chain all the way down to the machine code level. |
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533 | In essence, the work presented in this publication is one part of CerCo's extension over CompCert. |
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534 | |
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535 | \subsection{Source code} |
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536 | \label{subsect.source.code} |
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537 | |
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538 | All files relating to our formalisation effort can be found online at~\url{http://cerco.cs.unibo.it}. |
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539 | |
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540 | \bibliography{cpp-2011.bib} |
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541 | |
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542 | \end{document}\renewcommand{\verb}{\lstinline} |
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543 | \def\lstlanguagefiles{lst-grafite.tex} |
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544 | \lstset{language=Grafite} |
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