# source:src/ASM/CPP2011/cpp-2011.tex@1003

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37\title{On the correctness of an assembler for the Intel MCS-51 microprocessor\thanks{The project CerCo acknowledges the financial support of the Future and Emerging Technologies (FET) programme within the Seventh Framework Programme for Research of the European Commission, under FET-Open grant number: 243881}}
38\author{Dominic P. Mulligan \and Claudio Sacerdoti Coen}
39\institute{Dipartimento di Scienze dell'Informazione, Universit\'a di Bologna}
40
41\bibliographystyle{splncs03}
42
43\begin{document}
44
45\maketitle
46
47\begin{abstract}
48We consider the formalisation of an assembler for Intel MCS-51 assembly language in the Matita proof assistant.
49This formalisation forms a major component of the EU-funded CerCo project, concering the construction and formalisation of a concrete complexity preserving compiler for a large subset of the C programming language.
50
51The efficient expansion of pseudoinstructions---particularly jumps---into MCS-51 machine instructions is complex.
52We employ a strategy, involving the use of policies', that separates the decision making over how jumps should be expanded from the expansion process itself.
53This makes the proof of correctness for the assembler significantly more straightforward.
54
55We prove, under the assumption of the existence of a correct policy, that the assembly process never fails and preserves the semantics of a subset of assembly programs.
56Correct policies fail to exist only in a limited number of pathological circumstances.
57Our assembler is complete with respect to the choice of policy.
58
59Surprisingly, we observe that it is impossible for an optimising assembler to preserve the semantics of every assembly program.
60\end{abstract}
61
62% ---------------------------------------------------------------------------- %
63% SECTION                                                                      %
64% ---------------------------------------------------------------------------- %
65\section{Introduction}
66\label{sect.introduction}
67
68We consider the formalisation of an assembler for the Intel MCS-51 8-bit microprocessor in the Matita proof assistant~\cite{asperti:user:2007}.
69This formalisation forms a major component of the EU-funded CerCo project~\cite{cerco:2011}, concering the construction and formalisation of a concrete complexity preserving compiler for a large subset of the C programming language.
70
71The MCS-51 dates from the early 1980s and is commonly called the 8051/8052.
72Despite the microprocessor's age, derivatives are still widely manufactured by a number of semiconductor foundries.
73As a result the processor is widely used, especially in embedded systems development, where well-tested, cheap, predictable microprocessors find their niche.
74
75The MCS-51 has a relative paucity of features compared to its more modern brethren.
76In particular, the MCS-51 does not possess a cache or any instruction pipelining that would make predicting the concrete cost of executing a single instruction an involved process.
77Instead, each semiconductor foundry that produces an MCS-51 derivative is able to provide accurate timing information in clock cycles for each instruction in their derivative's instruction set.
78It is important to stress that this timing information, unlike in more sophisticated processors, is not an estimate, it is a definition.
79For the MCS-51, if a manufacturer states that a particular opcode takes three clock cycles to execute, then that opcode \emph{always} takes three clock cycles to execute.
80
81This predicability of timing information is especially attractive to the CerCo consortium.
82We are in the process of constructing a certified, concrete complexity compiler for a realistic processor, and not for building and formalising the worst case execution time (WCET) tools that would be necessary to achieve the same result with, for example, a modern ARM or PowerPC microprocessor.
83
84However, the MCS-51's paucity of features is a double edged sword.
85In particular, the MCS-51 features relatively miniscule memory spaces (including read-only code memory, stack and internal/external random access memory) by modern standards.
86As a result our compiler, to have any sort of hope of successfully compiling realistic C programs, ought to produce tight' machine code.
87This is not simple and requires the use of optimisations.
88
89For example, the MCS-51 features three unconditional jump instructions: \texttt{LJMP} and \texttt{SJMP}---long jump' and short jump' respectively---and an 11-bit oddity of the MCS-51, \texttt{AJMP}.
90Each of these three instructions expects arguments in different sizes and behaves in different ways: \texttt{SJMP} may only perform a local jump'; \texttt{LJMP} may jump to any address in the MCS-51's memory space and \texttt{AJMP} may jump to any address in the current memory page.
91Consequently, the size of each opcode is different, and to squeeze as much code as possible into the MCS-51's limited code memory, the smallest possible opcode should be selected.
92
93The prototype CerCo C compiler does not attempt to select the smallest jump opcode in this manner, as this was thought to unneccessarily complicate the compilation chain.
94Instead, the compiler targets an assembly language, complete with pseudoinstructions including bespoke \texttt{Jmp} and \texttt{Call} instructions.
95Labels, conditional jumps to labels, a program preamble containing global data and a \texttt{MOV} instruction for moving this global data into the MCS-51's one 16-bit register also feature.
96This latter feature will ease any later consideration of separate compilation in the CerCo compiler.
97An assembler is used to expand pseudoinstructions into MCS-51 machine code.
98
99However, this assembly process is not trivial, for numerous reasons.
100For example, our conditional jumps to labels behave differently from their machine code counterparts.
101At the machine code level, all conditional jumps are short', limiting their range.
102However, at the assembly level, conditional jumps may jump to a label that appears anywhere in the program, significantly liberalising the use of conditional jumps and further simplifying the design of the CerCo compiler.
103
104Further, trying to na\"ively relate assembly programs with their machine code counterparts simply does not work.
105Machine code programs that fetch from constant addresses in code memory or programs that combine the program counter with constant shifts do not make sense at the assembly level, since the position of instructions in code memory will be known only after assembly and optimisation.
106More generally, memory addresses can only be compared with other memory addresses.
107However, checking that memory addresses are only compared against each other at the assembly level is in fact undecidable.
108In short, we come to the shocking realisation that, with optimisations, the full preservation of the semantics of the two languages is impossible.
109We believe that this revelation is significant for large formalisation projects that assume the existence of a correct assembler.
110Projects in this class include both the recent CompCert~\cite{compcert:2011,leroy:formal:2009} and seL4 formalisations~\cite{klein:sel4:2009}.
111
112Yet, the situation is even more complex than having to expand pseudoinstructions correctly.
113In particular, when formalising the assembler, we must make sure that the assembly process does not change the timing characteristics of an assembly program for two reasons.
114First, the semantics of some functions of the MCS-51, notably I/O, depend on the microprocessor's clock.
115Changing how long a particular program takes to execute can affect the semantics of a program.
116This is undesirable.
117
118Second, as mentioned, the CerCo consortium is in the business of constructing a verified compiler for the C programming language.
119However, unlike CompCert~\cite{compcert:2011,leroy:formal:2009,leroy:formally:2009}---which currently represents the state of the art for industrial grade' verified compilers---CerCo considers not just the \emph{extensional correctness} of the compiler, but also its \emph{intensional correctness}.
120That is, CompCert focusses solely on the preservation of the \emph{meaning} of a program during the compilation process, guaranteeing that the program's meaning does not change as it is gradually transformed into assembly code.
121However in any realistic compiler (even the CompCert compiler!) there is no guarantee that the program's time properties are preserved during the compilation process; a compiler's optimisations' could, in theory, even conspire to degrade the concrete complexity of certain classes of programs.
122CerCo aims to expand the current state of the art by producing a compiler where this temporal degradation is guaranteed not to happen.
123Moreover, CerCo's approach lifts a program's timing information to the source (C language) level, wherein the programmer can reason about a program's intensional properties by directly examining the source code that they write.
124
125In order to achieve this CerCo imposes a cost model on programs, or more specifically, on simple blocks of instructions.
126This cost model is induced by the compilation process itself, and its non-compositional nature allows us to assign different costs to identical blocks of instructions depending on how they are compiled.
127In short, we aim to obtain a very precise costing for a program by embracing the compilation process, not ignoring it.
128This, however, complicates the proof of correctness for the compiler proper: for every translation pass from intermediate language to intermediate language, we must prove that not only has the meaning of a program been preserved, but also its complexity characteristics.
129This also applies for the translation from assembly language to machine code.
130
131How do we assign a cost to a pseudoinstruction?
132As mentioned, conditional jumps at the assembly level can jump to a label appearing anywhere in the program.
133However, at the machine code level, conditional jumps are limited to jumping locally', using a measly byte offset.
134To translate a jump to a label, a single conditional jump pseudoinstruction may be translated into a block of three real instructions, as follows (here, \texttt{JZ} is jump if accumulator is zero'):
135\begin{displaymath}
137       & \mathtt{JZ}  & label                      &                 & \mathtt{JZ}   & \text{size of \texttt{SJMP} instruction} \\
138       & \ldots       &                            & \text{translates to}   & \mathtt{SJMP} & \text{size of \texttt{LJMP} instruction} \\
139label: & \mathtt{MOV} & \mathtt{A}\;\;\mathtt{B}   & \Longrightarrow & \mathtt{LJMP} & \text{address of \textit{label}} \\
140       &              &                            &                 & \ldots        & \\
141       &              &                            &                 & \mathtt{MOV}  & \mathtt{A}\;\;\mathtt{B}
142\end{array}
143\end{displaymath}
144In the translation, if \texttt{JZ} fails, we fall through to the \texttt{SJMP} which jumps over the \texttt{LJMP}.
145Naturally, if \textit{label} is close enough, a conditional jump pseudoinstruction is mapped directly to a conditional jump machine instruction; the above translation only applies if \textit{label} is not sufficiently local.
146This leaves the problem, addressed below, of calculating whether a label is indeed close enough' for the simpler translation to be used.
147
148Crucially, the above translation demonstrates the difficulty in predicting how many clock cycles a pseudoinstruction will take to execute.
149A conditional jump may be mapped to a single machine instruction or a block of three.
150Perhaps more insidious, the number of cycles needed to execute the instructions in the two branches of a translated conditional jump may be different.
151Depending on the particular MCS-51 derivative at hand, an \texttt{SJMP} could in theory take a different number of clock cycles to execute than an \texttt{LJMP}.
152These issues must also be dealt with in order to prove that the translation pass preserves the concrete complexity of the code, and that the semantics of a program using the MCS-51's I/O facilities does not change.
153We address this problem by parameterizing the semantics over a cost model.
154We prove the preservation of concrete complexity only for the program-dependent cost model induced by the optimisation.
155
156The question remains: how do we decide whether to expand a jump into an \texttt{SJMP} or an \texttt{LJMP}?
157To understand why this problem is not trivial, consider the following snippet of assembly code:
158\begin{displaymath}
160\text{1:} & \mathtt{(0x000)}  & \texttt{LJMP} & \texttt{0x100}  & \text{\texttt{;; Jump forward 256.}} \\
161\text{2:} & \mathtt{...}    & \mathtt{...}  &                 &                                               \\
162\text{3:} & \mathtt{(0x0FA)}  & \texttt{LJMP} & \texttt{0x100}  & \text{\texttt{;; Jump forward 256.}} \\
163\text{4:} & \mathtt{...}    & \mathtt{...}  &                 &                                               \\
164\text{5:} & \mathtt{(0x100)}  & \texttt{LJMP} & \texttt{0x-100}  & \text{\texttt{;; Jump backward 256.}} \\
165\end{array}
166\end{displaymath}
167We observe that $100_{16} = 256_{10}$, and lies \emph{just} outside the range expressible in an 8-bit byte (0--255).
168
169As our example shows, given an occurence $l$ of an \texttt{LJMP} instruction, it may be possible to shrink $l$ to an occurence of an \texttt{SJMP}---consuming fewer bytes of code memory---provided we can shrink any \texttt{LJMP}s that exist between $l$ and its target location.
170In particular, if we wish to shrink the \texttt{LJMP} occurring at line 1, then we must shrink the \texttt{LJMP} occurring at line 3.
171However, to shrink the \texttt{LJMP} occurring at line 3 we must also shrink the \texttt{LJMP} occurring at line 5, and \emph{vice versa}.
172
173Further, consider what happens if, instead of appearing at memory address \texttt{0x100}, the instruction at line 5 instead appeared \emph{just} beyond the size of code memory, and all other memory addresses were shifted accordingly.
174Now, in order to be able to successfully fit our program into the MCS-51's code memory, we are \emph{obliged} to shrink the \texttt{LJMP} occurring at line 5.
175That is, the shrinking process is not just related to optimisation, but also the completeness of the assembler.
176
177Thinking more, it is easy to imagine knotty, circular configurations of jumps developing, each jump occurrence only being shrinkable if every other is.
178Finding a solution to this shrinking jumps' problem then involves us finding a method to break any vicious circularities that develop.
179
180How we went about resolving this problem affected the shape of our proof of correctness for the whole assembler in a rather profound way.
181We first attempted to synthesize a solution bottom up: starting with no solution, we gradually refine a solution using the same functions that implement the jump expansion.
182Using this technique, solutions can fail to exist, and the proof quickly descends into a diabolical quagmire.
183
184Abandoning this attempt, we instead split the policy'---the decision over how any particular jump should be expanded---from the implementation that actually expands assembly programs into machine code.
185Assuming the existence of a correct policy, we proved the implementation of the assembler correct.
186Further, we proved that the assembler fails to assemble an assembly program if and only if a correct policy does not exist.
187Policies do not exist in only a limited number of circumstances: namely, if a pseudoinstruction attempts to jump to a label that does not exist, or the program is too large to fit in code memory.
188The first case would constitute a serious compiler error, and hopefully certifying the rest of the compiler would rule this possibility out.
189The second case is unavoidable---certified compiler or not, trying to load a huge program into a small code memory will break \emph{something}.
190
191The rest of this paper is a detailed description of this proof.
192
193% ---------------------------------------------------------------------------- %
194% SECTION                                                                      %
195% ---------------------------------------------------------------------------- %
196\subsection{Overview of the paper}
197\label{subsect.overview.of.the.paper}
198In Section~\ref{sect.matita} we provide a brief overview of the Matita proof assistant for the unfamiliar reader.
199In Section~\ref{sect.the.proof} we discuss the design and implementation of the proof proper.
200In Section~\ref{sect.conclusions} we conclude.
201
202% ---------------------------------------------------------------------------- %
203% SECTION                                                                      %
204% ---------------------------------------------------------------------------- %
205\section{Matita}
206\label{sect.matita}
207
208Matita is a proof assistant based on the Calculus of (Co)inductive Constructions~\cite{asperti:user:2007}.
209For those familiar with Coq, Matita's syntax and mode of operation should be entirely familiar.
210However, we take time here to explain one of Matita's syntactic idiosyncrasies.
211The use of $\mathtt{?}$' or $\mathtt{\ldots}$' in an argument position denotes a term or terms to be inferred automatically by unification, respectively.
212The use of $\mathtt{?}$' in the body of a definition, lemma or axiom denotes an incomplete term that is to be closed, by hand, using tactics.
213
214% ---------------------------------------------------------------------------- %
215% SECTION                                                                      %
216% ---------------------------------------------------------------------------- %
217\section{The proof}
218\label{sect.the.proof}
219
220\subsection{The assembler and semantics of machine code}
221\label{subsect.the.assembler.and.semantics.of.machine.code}
222
223The formalisation in Matita of the semantics of MCS-51 machine code is described in~\cite{mulligan:executable:2011}.
224We merely describe enough here to understand the rest of the proof.
225
226At heart, the MCS-51 emulator centres around a \texttt{Status} record, describing the current state of the microprocessor.
227This record contains fields corresponding to the microprocessor's program counter, special function registers, and so on.
228At the machine code level, code memory is implemented as a trie of bytes, addressed by the program counter.
230
231We may execut a single step of a machine code program using the \texttt{execute\_1} function, which returns an updated \texttt{Status}:
232\begin{lstlisting}
233definition execute_1: Status $\rightarrow$ Status := $\ldots$
234\end{lstlisting}
235The function \texttt{execute} allows one to execute an arbitrary, but fixed (due to Matita's normalisation requirement!) number of steps of a program.
236
237Naturally, assembly programs have analogues.
238The counterpart of the \texttt{Status} record is \texttt{PseudoStatus}.
239Instead of code memory being implemented as tries of bytes, code memory is here implemented as lists of pseudoinstructions, and program counters are merely indices into this list.
240In actual fact, both \texttt{Status} and \texttt{PseudoStatus} are both specialisations of the same \texttt{PreStatus} record, parametric in the representation of code memory.
241This allows us to share some code that is common to both records (for instance, setter' and getter' functions).
242A further benefit of this sharing is that those instructions that are completely ambivalent about the particular representation of code memory can be factored out into their own type.
243
244Our analogue of \texttt{execute\_1} is \texttt{execute\_1\_pseudo\_instruction}:
245\begin{lstlisting}
246definition execute_1_pseudo_instruction: (Word $\rightarrow$ nat $\times$ nat) $\rightarrow$
247                                         PseudoStatus $\rightarrow$ PseudoStatus := $\ldots$
248\end{lstlisting}
249Notice, here, that the emulation function for assembly programs takes an additional argument.
250This is a function that maps program counters (at the assembly level) to pairs of natural numbers representing the number of clock ticks that the pseudoinstruction needs to execute, post expansion.
251We call this function a \emph{costing}, and note that the costing is induced by the particular strategy we use to expand pseudoinstructions.
252If we change how we expand conditional jumps to labels, for instance, then the costing needs to change, hence \texttt{execute\_1\_pseudo\_instruction}'s parametricity in the costing.
253
254The costing returns \emph{pairs} of natural numbers because, in the case of expanding conditional jumps to labels, the expansion of the true branch' and false branch' may differ in the number of clock ticks needed for execution.
255This timing information is used inside \texttt{execute\_1\_pseudo\_instruction} to update the clock of the \texttt{PseudoStatus}.
256During the proof of correctness of the assembler we relate the clocks of \texttt{Status}es and \texttt{PseudoStatus}es for the policy induced by the cost model and optimisations.
257
258The assembler, mapping programs consisting of lists of pseudoinstructions to lists of bytes, operates in a mostly straightforward manner.
259To a degree of approximation, the assembler on an assembly program, consisting of $n$ pseudoinstructions $\mathtt{P_i}$ for $1 \leq i \leq n$, works as in the following diagram (we use $-^{*}$ to denote a combined map and flatten operation):
260\begin{displaymath}
261[\mathtt{P_1}, \ldots \mathtt{P_n}] \xrightarrow{\left(\mathtt{P_i} \xrightarrow{\mbox{\fontsize{7}{9}\selectfont$\mathtt{expand\_pseudo\_instruction}$}} \mathtt{[I_1^i, \ldots I^q_i]} \xrightarrow{\mbox{\fontsize{7}{9}\selectfont$\mathtt{~~~~~~~~assembly1^{*}~~~~~~~~}$}} \mathtt{[0110]}\right)^{*}} \mathtt{[010101]}
262\end{displaymath}
263Here $\mathtt{I^i_j}$ for $1 \leq j \leq q$ are the $q$ machine code instructions obtained by expanding, with \texttt{expand\_pseudo\_instruction}, a single pseudoinstruction.
264Each machine code instruction $\mathtt{I^i_j}$ is then assembled, using the \texttt{assembly1} function, into a list of bytes.
265This process is iterated for each pseudoinstruction, before the lists are flattened into a single bit list representation of the original assembly program.
266
267By inspecting the above diagram, it would appear that the best way to proceed with a proof that the assembly process does not change the semantics of an assembly program is via a decomposition of the problem into two subproblems.
268Namely, we first expand any and all pseudoinstructions into lists of machine instructions, and provide a proof that this process does not change our program's semantics.
269Finally, we assemble all machine code instructions into machine code---lists of bytes---and prove once more that this process does not have an adverse effect on a program's semantics.
270By composition, we then have that the whole assembly process is semantics preserving.
271
272%This is a tempting approach to the proof, but ultimately the wrong approach.
273%In particular, it is important that we track how the program counter indexing into the assembly program, and the machine's program counter evolve, so that we can relate them.
274%Expanding pseudoinstructions requires that the machine's program counter be incremented by $n$ steps, for $1 \leq n$, for every increment of the assembly program's program counter.
275%Keeping track of the correspondence between the two program counters quickly becomes unfeasible using a compositional approach, and hence the proof must be monolithic.
276
277% ---------------------------------------------------------------------------- %
278% SECTION                                                                      %
279% ---------------------------------------------------------------------------- %
280\subsection{Policies}
281\label{subsect.policies}
282
283Policies exist to dictate how conditional and unconditional jumps at the assembly level should be expanded into machine code instructions.
284Using policies, we are able to completely decouple the decision over how jumps are expanded with the act of expansion, simplifying our proofs.
285As mentioned, the MCS-51 instruction set includes three different jump instructions: \texttt{SJMP}, \texttt{AJMP} and \texttt{LJMP}; call these short', medium' and long' jumps, respectively:
286\begin{lstlisting}
287inductive jump_length: Type[0] :=
288  | short_jump: jump_length
289  | medium_jump: jump_length
290  | long_jump: jump_length.
291\end{lstlisting}
292A \texttt{jump\_expansion\_policy} is a map from pseudo program counters (implemented as \texttt{Word}s) to \texttt{jump\_length}s, implemented as a trie.
293Intuitively, a policy maps positions in a program (indexed using program counters implemented as \texttt{Word}s) to a particular variety of jump.
294\begin{lstlisting}
295definition jump_expansion_policy := BitVectorTrie jump_length 16.
296\end{lstlisting}
297Next, we require a series of sigma' functions.
298These functions map assembly program counters to their machine code counterparts, establishing the correspondence between positions' in an assembly program and positions' in a machine code program.
299At the heart of this process is \texttt{sigma0} which traverses an assembly program building maps from pseudo program counters to program counters.
300This function fails if and only if an internal call to \texttt{assembly\_1\_pseudoinstruction} fails:
301\begin{lstlisting}
302definition sigma0: pseudo_assembly_program
303  $\rightarrow$ option (nat $\times$ (nat $\times$ (BitVectorTrie Word 16))) := $\ldots$
304\end{lstlisting}
305We eventually lift this to functions from program counters to program counters:
306\begin{lstlisting}
307definition sigma_safe:
308  pseudo_assembly_program $\rightarrow$ option (Word $\rightarrow$ Word) := $\ldots$
309\end{lstlisting}
310Now, it's possible to define what a good policy' is i.e. one that does not cause \texttt{sigma\_safe} to fail.
311As mentioned, \texttt{sigma\_safe} can only fail if an assembly program fails to be assembled:
312\begin{lstlisting}
313definition policy_ok := $\lambda$p. sigma_safe p $\neq$ None $\ldots$.
314\end{lstlisting}
315Finally, we obtain \texttt{sigma}, a map from program counters to program counters, which is guranteed not to fail as we internally provide a that
316\begin{lstlisting}
317definition sigma: pseudo_assembly_program $\rightarrow$ Word $\rightarrow$ Word := $\ldots$
318\end{lstlisting}
319
320% ---------------------------------------------------------------------------- %
321% SECTION                                                                      %
322% ---------------------------------------------------------------------------- %
323\subsection{Total correctness of the assembler}
324\label{subsect.total.correctness.of.the.assembler}
325
326Using our policies, we now work toward proving the total correctness of the assembler.
327By total correctness, we mean that the assembly process does not change the semantics of an assembly program.
328Naturally, this necessitates keeping some sort of correspondence between program counters at the assembly level, and program counters at the machine code level.
329For this, we use the \texttt{sigma} machinery defined at the end of Subsection~\ref{subsect.policies}.
330
331We expand pseudoinstructions using the function \texttt{expand\_pseudo\_instruction}.
332This function accepts a policy decision'---an element of type \texttt{jump\_length}---that is used when expanding a \texttt{Call}, \texttt{Jmp} or conditional jump to a label into the correct machine instruction.
333This \texttt{policy\_decision} is asssumed to originate from a policy as defined in Subsection~\ref{subsect.policies}.
334\begin{lstlisting}
335definition expand_pseudo_instruction:
336  ∀lookup_labels, lookup_datalabels, pc, policy_decision.
337    pseudo_instruction $\rightarrow$ option list instruction := $\ldots$
338\end{lstlisting}
339Under the assumption that a correct policy exists, \texttt{expand\_pseudo\_instruction} should never fail, and therefore the option type may be dispensed with.
340This is because the only failure conditions for \texttt{expand\_pseudo\_instruction} result from trying to expand a pseudoinstruction into an impossible' combination of machine code instructions.
341For instance, if the policy decision dictates that we should expand a \texttt{Call} pseudoinstruction into a short jump', then we fail, as the MCS-51's instruction set only features instructions \texttt{ACALL} and \texttt{LCALL}.
342
343% dpm todo
344\begin{lstlisting}
345axiom assembly_ok: ∀program,assembled,costs,labels.
346  Some $\ldots$ $\langle$labels, costs$\rangle$ = build_maps program $\rightarrow$
347  Some $\ldots$ $\langle$assembled, costs$\rangle$ = assembly program $\rightarrow$
348  let code_memory := load_code_memory assembled in
349  let preamble := $\pi_1$ program in
350  let datalabels := construct_datalabels preamble in
351  let lk_labels :=
352    $\lambda$x. sigma program (address_of_word_labels_code_mem ($\pi_2$ program) x) in
353  let lk_dlabels := $\lambda$x. lookup ? ? x datalabels (zero ?) in
354   ∀ppc,len,assembledi.
355    let $\langle$pi, newppc$\rangle$ := fetch_pseudo_instruction ($\pi_2$ program) ppc in
356    let assembly' := assembly_1_pseudoinstruction program ppc
357      (sigma program ppc) lk_labels lk_dlabels pi in
358    let newpc := (sigma program ppc) + len in
359    let echeck :=
360      encoding_check code_memory (sigma program ppc) slen assembledi in
361     Some $\ldots$ $\langle$len, assembledi$\rangle$ = assembly' $\rightarrow$
362      echeck $\wedge$ sigma program newppc = newpc.
363\end{lstlisting}
364
365% dpm todo
366\begin{lstlisting}
367theorem fetch_assembly: $\forall$pc, i, cmem, assembled.
368  assembled = assembly1 i $\rightarrow$
369  let len := length $\ldots$ assembled in
370    encoding_check cmem pc (pc + len) assembled $\rightarrow$
371    let fetched := fetch code_memory (bitvector_of_nat $\ldots$ pc) in
372    let $\langle$instr_pc, ticks$\rangle$ := fetched in
373    let $\langle$instr, pc'$\rangle$ := instr_pc in
374      (eq_instruction instr i $\wedge$
375       eqb ticks (ticks_of_instruction instr) $\wedge$
376       eq_bv $\ldots$ pc' (pc + len)) = true.
377\end{lstlisting}
378
379Lemma \texttt{fetch\_assembly\_pseudo} establishes a basic relationship between \texttt{expand\_pseudo\_instruction} and \texttt{assembly\_1\_pseudoinstruction}:
380\begin{lstlisting}
381lemma fetch_assembly_pseudo: $\forall$program, ppc, lk_labels, lk_dlabels.
382  $\forall$pi, code_memory, len, assembled, instructions, pc.
383  let jexp := jump_expansion ppc program in
384  let exp :=
385    expand_pseudo_instruction lk_labels lk_dlabels pc jexp pi
386  let ass :=
387    assembly_1_pseudoinstruction program ppc pc lk_labels lk_dlabels pi in
388  Some ? instructions = exp $\rightarrow$
389    Some $\ldots$ $\langle$len, assembled$\rangle$ = ass $\rightarrow$
390      encoding_check code_memory pc (pc + len) assembled $\rightarrow$
391        fetch_many code_memory (pc + len) pc instructions.
392\end{lstlisting}
393Here, \texttt{len} is the number of machine code instructions the pseudoinstruction at hand has been expanded into, \texttt{encoding\_check} is a recursive function that checks for any possible corruption of the code memory, resulting from expanding the pseudoinstruction.
394We assemble a single pseudoinstruction with \texttt{assembly\_1\_pseudoinstruction}, which internally calls \texttt{jump\_expansion} and \texttt{expand\_pseudo\_instruction}.
395The function \texttt{fetch\_many} fetches multiple machine code instructions from code memory and performs some routine checks.
396
397Intuitively, Lemma \texttt{fetch\_assembly\_pseudo} can be read as follows.
398Suppose our policy \texttt{jump\_expansion} dictates that the pseudoinstruction indexed by the pseudo program counter \texttt{ppc} in assembly program \texttt{program} gives us the policy decision \texttt{jexp}.
399Further, suppose we expand the pseudoinstruction at \texttt{ppc} with the policy decision \texttt{jexp}, obtaining an (optional) list of machine code instructions \texttt{exp}.
400Suppose we also assemble the pseudoinstruction at \texttt{ppc} to obtain \texttt{ass}, a list of bytes.
401Then, under the assumption that neither the expansion of the pseudoinstruction to obtain \texttt{exp}, nor the assembly of the pseudoinstruction to obtain \texttt{ass}, failed, we check with \texttt{fetch\_many} that the number of machine instructions that were fetched matches the number of instruction that \texttt{expand\_pseudo\_instruction} expanded.
402
403At first sight, Lemma \texttt{fetch\_assembly\_pseudo2} appears to nearly establish the correctness of the assembler:
404\begin{lstlisting}
405lemma fetch_assembly_pseudo2: $\forall$program, assembled, costs, labels.
406  Some $\ldots$ $\langle$labels, costs$\rangle$ = build_maps program $\rightarrow$
407  Some $\ldots$ $\langle$assembled, costs$\rangle$ = assembly program $\rightarrow$ $\forall$ppc.
408  let code_memory := load_code_memory assembled in
409  let preamble := $\pi_1$ program in
410  let data_labels := construct_datalabels preamble in
411  let lk_labels :=
412    λx. sigma program (address_of_word_labels_code_mem ($\pi_2$ program) x) in
413  let lk_dlabels := λx. lookup ? ? x data_labels (zero ?) in
414  let expansion := jump_expansion ppc program in
415  let $\langle$pi, newppc$\rangle$ := fetch_pseudo_instruction ($\pi_2$ program) ppc in
416  let ppc' := sigma program ppc in
417  let newppc' := sigma program newppc in
418  let instructions' :=
419    expand_pseudo_instruction lk_labels lk_dlabels ppc' expansion pi in
420  let fetched := $\lambda$instr. fetch_many code_memory newppc' ppc' instr in
421    $\exists$instrs. Some ? instrs = instructions' $\wedge$ fetched instrs.
422\end{lstlisting}
423Intuitively, we may read \texttt{fetch\_assembly\_pseudo2} as follows.
424Suppose we are able to successfully assemble an assembly program using \texttt{assembly} and produce a code memory, \texttt{code\_memory}.
425Then there exists some list of machine instructions equal to the expansion of a pseudoinstruction and the number of machine instructions that need to be fetched is equal to the number of machine instructions that the pseudoinstruction was expanded into.
426
427However, this property is \emph{not} strong enough to establish that the semantics of an assembly program has been preserved by the assembly process.
428In particular, \texttt{fetch\_assembly\_pseudo2} says nothing about how memory addresses evolve during assembly.
429Memory addresses in one memory space may be mapped to memory addresses in a completely different memory space during assembly.
430To handle this problem, we need some more machinery.
431
432We use an \texttt{internal\_pseudo\_address\_map} for this purpose.
433An \texttt{internal\_pseudo\_address\_map} associates positions in the memory of a \texttt{PseudoStatus} with a physical memory address:
434\begin{lstlisting}
435definition internal_pseudo_address_map := list (BitVector 8).
436\end{lstlisting}
437We use \texttt{internal\_pseudo\_address\_map}s to convert the lower internal RAM of a \texttt{PseudoStatus} into the lower internal RAM of a \texttt{Status}.
438The actual conversion process is performed by \texttt{low\_internal\_ram\_of\_pseudo\_low\_internal\_ram}:\footnote{An associated set of axioms describe how \texttt{low\_internal\_ram\_of\_pseudo\_low\_internal\_ram} behaves.  This is a form of parametricity.  We don't care about the particulars of the conversion functions, as long as they behave in accordance with our axioms.}
439
440\begin{lstlisting}
441axiom low_internal_ram_of_pseudo_low_internal_ram:
442  internal_pseudo_address_map $\rightarrow$ BitVectorTrie Byte 7 $\rightarrow$ BitVectorTrie Byte 7.
443\end{lstlisting}
444A similar axiom exists for high internal RAM.
445
446Notice, the MCS-51's internal RAM is addressed with a 7-bit byte'.
447% dpm: ugly English, fix
448The whole of the internal RAM space is addressed with bytes: the first bit is used to distinguish between the programmer addressing low and high internal memory.
449
450Next, we are able to translate \texttt{PseudoStatus} records into \texttt{Status} records using \texttt{status\_of\_pseudo\_status}.
451Translating a \texttt{PseudoStatus}'s code memory requires we expand pseudoinstructions and then assemble to obtain a trie of bytes.
452This can fail, as mentioned, in a limited number of situations, related to improper use of labels in an assembly program.
453However, it is possible to tighten' the type of \texttt{status\_of\_pseudo\_status}, removing the option type, by using the fact that if any good policy' exists, assembly will never fail.
454\begin{lstlisting}
455definition status_of_pseudo_status:
456 internal_pseudo_address_map → PseudoStatus → option Status
457\end{lstlisting}
458After fetching an assembly instruction we must update any \texttt{internal\_pseudo\hyp{}\_address\_map}s that may be laying around.
459This is done with the following function:
460\begin{lstlisting}
462  $\rightarrow$ PseudoStatus $\rightarrow$ option internal_pseudo_address_map
463\end{lstlisting}
464Finally, we are able to state and prove our main theorem.
465This relates the execution of a single assembly instruction and the execution of (possibly) many machine code instructions.
466That is, the assembly process preserves the semantics of an assembly program, as it is translated into machine code:
467\begin{lstlisting}
468theorem main_thm:
469  ∀M,M',ps,s,s''.
470    next_internal_pseudo_address_map M ps = Some $\ldots$ M' $\rightarrow$
471      status_of_pseudo_status M ps = Some $\ldots$ s $\rightarrow$
472        status_of_pseudo_status M'
473          (execute_1_pseudo_instruction
474            (ticks_of (code_memory $\ldots$ ps)) ps) = Some $\ldots$ s'' $\rightarrow$
475              $\exists$n. execute n s = s''.
476\end{lstlisting}
477The statement can be given an intuitive reading as follows.
478Suppose our \texttt{PseudoStatus}, \texttt{ps}, can be successfully converted into a \texttt{Status}, \texttt{s}.
479Suppose further that, after executing a single assembly instruction and converting the resulting \texttt{PseudoStatus} into a \texttt{Status}, we obtain \texttt{s''}, being careful to track the number of ticks executed.
480Then, there exists some number \texttt{n}, so that executing \texttt{n} machine code instructions in \texttt{Status} \texttt{s} gives us \texttt{Status} \texttt{s''}.
481Theorem \texttt{main\_thm} establishes the correctness of the assembly process.
482
483% ---------------------------------------------------------------------------- %
484% SECTION                                                                      %
485% ---------------------------------------------------------------------------- %
486\section{Conclusions}
487\label{sect.conclusions}
488
489We have proved the total correctness of an assembler for MCS-51 assembly language.
490In particular, our assembly language featured labels, arbitrary conditional and unconditional jumps to labels, global data and instructions for moving this data into the MCS-51's single 16-bit register.
491Expanding these pseudoinstructions into machine code instructions is not trivial, and the proof that the assembly process is correct', in that the semantics of a subset of assembly programs are not changed is complex.
492Further, we have observed the shocking' fact that any optimising assembler cannot preserve the semantics of all assembly programs.
493
494The formalisation is a key component of the CerCo project, which aims to produce a verified concrete complexity preserving compiler for a large subset of the C programming language.
495The verified assembler, complete with the underlying formalisation of the semantics of MCS-51 machine code (described fully in~\cite{mulligan:executable:2011}), will form the bedrock layer upon which the rest of the CerCo project will build its verified compiler platform.
496However, further work is needed.
497In particular, as it stands, the code produced by the prototype CerCo C compiler does not fall into the semantics preserving' subset of assembly programs for our assembler.
498This is because the MCS-51 features a small stack space, and a larger stack is customarily manually emulated in external RAM.
499As a result, the majority of programs feature slices of memory addresses and program counters being moved in-and-out of external RAM via the registers, simulating the stack mechanism.
500At the moment, this movement is not tracked by \texttt{internal\_pseudo\_address\_map}, which only tracks the movement of memory addresses in low internal RAM.
501We leave extending this tracking of memory addresses throughout the whole of the MCS-51's address spaces as future work.
502
503Aside from their application in verified compiler projects such as CerCo and CompCert, verified assemblers such as ours could also be applied to the verification of operating system kernels.
504Of particular note is the verified seL4 kernel~\cite{klein:sel4:2009,klein:sel4:2010}.
505This verification explicitly assumes the existence of, amongst other things, a trustworthy assembler and compiler.
506
507We note here that both CompCert and the seL4 formalisation assume the existence of `trustworthy' assemblers.
508Our observation that an optimising assembler cannot preserve the semantics of every assembly program may have important consequences for these projects.
509In particular, if CompCert chooses to assume the existence of an optimising assembler, then care should be made to ensure that any assembly program produced by the CompCert C compiler falls into the class of assembly programs that have a hope of having their semantics preserved by an optimising assembler.
510
511In certain places in our formalisation (e.g. in proving \texttt{build\_maps} is correct) we made use of Matita's implementation of Russell~\cite{sozeau:subset:2006}.
512In Matita, Russell may be implemented using two coercions and some notational sugaring.
513% more
514
515\subsection{Related work}
516\label{subsect.related.work}
517
518% piton
519We are not the first to consider the total correctness of an assembler for a non-trivial assembly language.
520Perhaps the most impressive piece of work in this domain is the Piton stack~\cite{moore:piton:1996,moore:grand:2005}.
521This was a stack of verified components, written and verified in ACL2, ranging from a proprietary FM9001 microprocessor verified at the gate level, to assemblers and compilers for two high-level languages---a dialect of Lisp and $\mu$Gypsy~\cite{moore:grand:2005}.
522
523% jinja
524Klein and Nipkow consider a Java-like programming language, Jinja~\cite{klein:machine:2006,klein:machine:2010}.
525They provide a compiler, virtual machine and operational semantics for the programming language and virtual machine, and prove that their compiler is semantics and type preserving.
526
527We believe some other verified assemblers exist in the literature.
528However, what sets our work apart from that above is our attempt to optimise the machine code generated by our assembler.
529This complicates any formalisation effort, as the best possible selection of machine instructions must be made, especially important on a device such as the MCS-51 with a miniscule code memory.
530Further, care must be taken to ensure that the time properties of an assembly program are not modified by the assembly process lest we affect the semantics of any program employing the MCS-51's I/O facilities. This is only possible by
531inducing a cost model on the source code from the optimization strategy and
532input program. This will be a leit-motif of CerCo.
533
534Finally, mention of CerCo will invariably invite comparisons with CompCert~\cite{compcert:2011,leroy:formal:2009}, another verified compiler project closely related to CerCo.
535As previously mentioned, CompCert considers only extensional correctness of the compiler, and not intensional correctness, which CerCo focusses on.
536However, CerCo also extends CompCert in other ways.
537Namely, the CompCert verified compilation chain terminates at the PowerPC or ARM assembly level, and takes for granted the existence of a trustworthy assembler.
538CerCo chooses to go further, by considering a verified compilation chain all the way down to the machine code level.
539In essence, the work presented in this publication is one part of CerCo's extension over CompCert.
540
541\subsection{Source code}
542\label{subsect.source.code}
543
544All files relating to our formalisation effort can be found online at~\url{http://cerco.cs.unibo.it}.
545
546\bibliography{cpp-2011.bib}
547
548\end{document}\renewcommand{\verb}{\lstinline}
549\def\lstlanguagefiles{lst-grafite.tex}
550\lstset{language=Grafite}
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