[985] | 1 | include "ASM/BitVector.ma". |
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[1515] | 2 | include "common/Identifiers.ma". |
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| 3 | include "common/CostLabel.ma". |
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[1882] | 4 | include "common/LabelledObjects.ma". |
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[475] | 5 | |
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[1515] | 6 | axiom ASMTag : String. |
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| 7 | definition Identifier ≝ identifier ASMTag. |
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| 8 | definition toASM_ident : ∀tag. identifier tag → Identifier ≝ λt,i. match i with [ an_identifier id ⇒ an_identifier ASMTag id ]. |
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[985] | 9 | |
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[475] | 10 | inductive addressing_mode: Type[0] ≝ |
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| 11 | DIRECT: Byte → addressing_mode |
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| 12 | | INDIRECT: Bit → addressing_mode |
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| 13 | | EXT_INDIRECT: Bit → addressing_mode |
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[698] | 14 | | REGISTER: BitVector 3 → addressing_mode |
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[475] | 15 | | ACC_A: addressing_mode |
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| 16 | | ACC_B: addressing_mode |
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| 17 | | DPTR: addressing_mode |
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| 18 | | DATA: Byte → addressing_mode |
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| 19 | | DATA16: Word → addressing_mode |
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| 20 | | ACC_DPTR: addressing_mode |
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| 21 | | ACC_PC: addressing_mode |
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| 22 | | EXT_INDIRECT_DPTR: addressing_mode |
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| 23 | | INDIRECT_DPTR: addressing_mode |
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| 24 | | CARRY: addressing_mode |
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| 25 | | BIT_ADDR: Byte → addressing_mode |
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| 26 | | N_BIT_ADDR: Byte → addressing_mode |
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| 27 | | RELATIVE: Byte → addressing_mode |
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| 28 | | ADDR11: Word11 → addressing_mode |
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| 29 | | ADDR16: Word → addressing_mode. |
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| 30 | |
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[2124] | 31 | definition eq_addressing_mode: addressing_mode → addressing_mode → bool ≝ |
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| 32 | λa, b: addressing_mode. |
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| 33 | match a with |
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| 34 | [ DIRECT d ⇒ |
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| 35 | match b with |
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| 36 | [ DIRECT e ⇒ eq_bv ? d e |
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| 37 | | _ ⇒ false |
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| 38 | ] |
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| 39 | | INDIRECT b' ⇒ |
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| 40 | match b with |
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| 41 | [ INDIRECT e ⇒ eq_b b' e |
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| 42 | | _ ⇒ false |
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| 43 | ] |
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| 44 | | EXT_INDIRECT b' ⇒ |
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| 45 | match b with |
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| 46 | [ EXT_INDIRECT e ⇒ eq_b b' e |
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| 47 | | _ ⇒ false |
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| 48 | ] |
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| 49 | | REGISTER bv ⇒ |
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| 50 | match b with |
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| 51 | [ REGISTER bv' ⇒ eq_bv ? bv bv' |
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| 52 | | _ ⇒ false |
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| 53 | ] |
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| 54 | | ACC_A ⇒ match b with [ ACC_A ⇒ true | _ ⇒ false ] |
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| 55 | | ACC_B ⇒ match b with [ ACC_B ⇒ true | _ ⇒ false ] |
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| 56 | | DPTR ⇒ match b with [ DPTR ⇒ true | _ ⇒ false ] |
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| 57 | | DATA b' ⇒ |
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| 58 | match b with |
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| 59 | [ DATA e ⇒ eq_bv ? b' e |
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| 60 | | _ ⇒ false |
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| 61 | ] |
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| 62 | | DATA16 w ⇒ |
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| 63 | match b with |
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| 64 | [ DATA16 e ⇒ eq_bv ? w e |
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| 65 | | _ ⇒ false |
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| 66 | ] |
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| 67 | | ACC_DPTR ⇒ match b with [ ACC_DPTR ⇒ true | _ ⇒ false ] |
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| 68 | | ACC_PC ⇒ match b with [ ACC_PC ⇒ true | _ ⇒ false ] |
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| 69 | | EXT_INDIRECT_DPTR ⇒ match b with [ EXT_INDIRECT_DPTR ⇒ true | _ ⇒ false ] |
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| 70 | | INDIRECT_DPTR ⇒ match b with [ INDIRECT_DPTR ⇒ true | _ ⇒ false ] |
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| 71 | | CARRY ⇒ match b with [ CARRY ⇒ true | _ ⇒ false ] |
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| 72 | | BIT_ADDR b' ⇒ |
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| 73 | match b with |
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| 74 | [ BIT_ADDR e ⇒ eq_bv ? b' e |
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| 75 | | _ ⇒ false |
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| 76 | ] |
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| 77 | | N_BIT_ADDR b' ⇒ |
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| 78 | match b with |
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| 79 | [ N_BIT_ADDR e ⇒ eq_bv ? b' e |
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| 80 | | _ ⇒ false |
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| 81 | ] |
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| 82 | | RELATIVE n ⇒ |
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| 83 | match b with |
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| 84 | [ RELATIVE e ⇒ eq_bv ? n e |
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| 85 | | _ ⇒ false |
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| 86 | ] |
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| 87 | | ADDR11 w ⇒ |
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| 88 | match b with |
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| 89 | [ ADDR11 e ⇒ eq_bv ? w e |
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| 90 | | _ ⇒ false |
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| 91 | ] |
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| 92 | | ADDR16 w ⇒ |
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| 93 | match b with |
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| 94 | [ ADDR16 e ⇒ eq_bv ? w e |
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| 95 | | _ ⇒ false |
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| 96 | ] |
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| 97 | ]. |
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| 98 | |
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| 99 | lemma eq_addressing_mode_refl: |
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| 100 | ∀a. eq_addressing_mode a a = true. |
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| 101 | #a |
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| 102 | cases a try #arg1 try #arg2 |
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| 103 | try @eq_bv_refl try @eq_b_refl |
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| 104 | try normalize % |
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| 105 | qed. |
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| 106 | |
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[757] | 107 | (* dpm: renamed register to registr to avoid clash with brian's types *) |
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[475] | 108 | inductive addressing_mode_tag : Type[0] ≝ |
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| 109 | direct: addressing_mode_tag |
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| 110 | | indirect: addressing_mode_tag |
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| 111 | | ext_indirect: addressing_mode_tag |
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[757] | 112 | | registr: addressing_mode_tag |
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[475] | 113 | | acc_a: addressing_mode_tag |
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| 114 | | acc_b: addressing_mode_tag |
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| 115 | | dptr: addressing_mode_tag |
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| 116 | | data: addressing_mode_tag |
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| 117 | | data16: addressing_mode_tag |
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| 118 | | acc_dptr: addressing_mode_tag |
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| 119 | | acc_pc: addressing_mode_tag |
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| 120 | | ext_indirect_dptr: addressing_mode_tag |
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| 121 | | indirect_dptr: addressing_mode_tag |
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| 122 | | carry: addressing_mode_tag |
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| 123 | | bit_addr: addressing_mode_tag |
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| 124 | | n_bit_addr: addressing_mode_tag |
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| 125 | | relative: addressing_mode_tag |
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| 126 | | addr11: addressing_mode_tag |
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| 127 | | addr16: addressing_mode_tag. |
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| 128 | |
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| 129 | definition eq_a ≝ |
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| 130 | λa, b: addressing_mode_tag. |
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| 131 | match a with |
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| 132 | [ direct ⇒ match b with [ direct ⇒ true | _ ⇒ false ] |
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| 133 | | indirect ⇒ match b with [ indirect ⇒ true | _ ⇒ false ] |
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| 134 | | ext_indirect ⇒ match b with [ ext_indirect ⇒ true | _ ⇒ false ] |
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[757] | 135 | | registr ⇒ match b with [ registr ⇒ true | _ ⇒ false ] |
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[475] | 136 | | acc_a ⇒ match b with [ acc_a ⇒ true | _ ⇒ false ] |
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| 137 | | acc_b ⇒ match b with [ acc_b ⇒ true | _ ⇒ false ] |
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| 138 | | dptr ⇒ match b with [ dptr ⇒ true | _ ⇒ false ] |
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| 139 | | data ⇒ match b with [ data ⇒ true | _ ⇒ false ] |
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| 140 | | data16 ⇒ match b with [ data16 ⇒ true | _ ⇒ false ] |
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| 141 | | acc_dptr ⇒ match b with [ acc_dptr ⇒ true | _ ⇒ false ] |
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| 142 | | acc_pc ⇒ match b with [ acc_pc ⇒ true | _ ⇒ false ] |
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| 143 | | ext_indirect_dptr ⇒ match b with [ ext_indirect_dptr ⇒ true | _ ⇒ false ] |
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| 144 | | indirect_dptr ⇒ match b with [ indirect_dptr ⇒ true | _ ⇒ false ] |
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| 145 | | carry ⇒ match b with [ carry ⇒ true | _ ⇒ false ] |
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| 146 | | bit_addr ⇒ match b with [ bit_addr ⇒ true | _ ⇒ false ] |
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| 147 | | n_bit_addr ⇒ match b with [ n_bit_addr ⇒ true | _ ⇒ false ] |
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| 148 | | relative ⇒ match b with [ relative ⇒ true | _ ⇒ false ] |
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| 149 | | addr11 ⇒ match b with [ addr11 ⇒ true | _ ⇒ false ] |
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| 150 | | addr16 ⇒ match b with [ addr16 ⇒ true | _ ⇒ false ] |
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| 151 | ]. |
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| 152 | |
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[2032] | 153 | lemma eq_a_to_eq: |
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| 154 | ∀a,b. |
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| 155 | eq_a a b = true → a = b. |
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| 156 | #a #b |
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| 157 | cases a cases b |
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| 158 | #K |
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| 159 | try cases (eq_true_false K) |
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| 160 | % |
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| 161 | qed. |
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| 162 | |
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| 163 | lemma eq_a_reflexive: |
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| 164 | ∀a. eq_a a a = true. |
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| 165 | #a cases a % |
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| 166 | qed. |
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| 167 | |
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| 168 | let rec member_addressing_mode_tag |
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| 169 | (n: nat) (v: Vector addressing_mode_tag n) (a: addressing_mode_tag) |
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| 170 | on v: Prop ≝ |
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| 171 | match v with |
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| 172 | [ VEmpty ⇒ False |
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| 173 | | VCons n' hd tl ⇒ |
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| 174 | bool_to_Prop (eq_a hd a) ∨ member_addressing_mode_tag n' tl a |
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| 175 | ]. |
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| 176 | |
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| 177 | lemma mem_decidable: |
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| 178 | ∀n: nat. |
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| 179 | ∀v: Vector addressing_mode_tag n. |
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| 180 | ∀element: addressing_mode_tag. |
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| 181 | mem … eq_a n v element = true ∨ |
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| 182 | mem … eq_a … v element = false. |
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| 183 | #n #v #element // |
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| 184 | qed. |
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| 185 | |
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| 186 | lemma eq_a_elim: |
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| 187 | ∀tag. |
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| 188 | ∀hd. |
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| 189 | ∀P: bool → Prop. |
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| 190 | (tag = hd → P (true)) → |
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| 191 | (tag ≠ hd → P (false)) → |
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| 192 | P (eq_a tag hd). |
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| 193 | #tag #hd #P |
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| 194 | cases tag |
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| 195 | cases hd |
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| 196 | #true_hyp #false_hyp |
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| 197 | try @false_hyp |
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| 198 | try @true_hyp |
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| 199 | try % |
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| 200 | #absurd destruct(absurd) |
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| 201 | qed. |
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| 202 | |
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[475] | 203 | (* to avoid expansion... *) |
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| 204 | let rec is_a (d:addressing_mode_tag) (A:addressing_mode) on d ≝ |
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| 205 | match d with |
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| 206 | [ direct ⇒ match A with [ DIRECT _ ⇒ true | _ ⇒ false ] |
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| 207 | | indirect ⇒ match A with [ INDIRECT _ ⇒ true | _ ⇒ false ] |
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| 208 | | ext_indirect ⇒ match A with [ EXT_INDIRECT _ ⇒ true | _ ⇒ false ] |
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[757] | 209 | | registr ⇒ match A with [ REGISTER _ ⇒ true | _ ⇒ false ] |
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[475] | 210 | | acc_a ⇒ match A with [ ACC_A ⇒ true | _ ⇒ false ] |
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| 211 | | acc_b ⇒ match A with [ ACC_B ⇒ true | _ ⇒ false ] |
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| 212 | | dptr ⇒ match A with [ DPTR ⇒ true | _ ⇒ false ] |
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| 213 | | data ⇒ match A with [ DATA _ ⇒ true | _ ⇒ false ] |
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| 214 | | data16 ⇒ match A with [ DATA16 _ ⇒ true | _ ⇒ false ] |
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| 215 | | acc_dptr ⇒ match A with [ ACC_DPTR ⇒ true | _ ⇒ false ] |
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| 216 | | acc_pc ⇒ match A with [ ACC_PC ⇒ true | _ ⇒ false ] |
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| 217 | | ext_indirect_dptr ⇒ match A with [ EXT_INDIRECT_DPTR ⇒ true | _ ⇒ false ] |
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| 218 | | indirect_dptr ⇒ match A with [ INDIRECT_DPTR ⇒ true | _ ⇒ false ] |
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| 219 | | carry ⇒ match A with [ CARRY ⇒ true | _ ⇒ false ] |
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| 220 | | bit_addr ⇒ match A with [ BIT_ADDR _ ⇒ true | _ ⇒ false ] |
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| 221 | | n_bit_addr ⇒ match A with [ N_BIT_ADDR _ ⇒ true | _ ⇒ false ] |
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| 222 | | relative ⇒ match A with [ RELATIVE _ ⇒ true | _ ⇒ false ] |
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| 223 | | addr11 ⇒ match A with [ ADDR11 _ ⇒ true | _ ⇒ false ] |
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[1112] | 224 | | addr16 ⇒ match A with [ ADDR16 _ ⇒ true | _ ⇒ false ] |
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| 225 | ]. |
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[475] | 226 | |
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[2032] | 227 | lemma is_a_decidable: |
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| 228 | ∀hd. |
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| 229 | ∀element. |
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| 230 | is_a hd element = true ∨ is_a hd element = false. |
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| 231 | #hd #element // |
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| 232 | qed. |
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[475] | 233 | |
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| 234 | let rec is_in n (l: Vector addressing_mode_tag n) (A:addressing_mode) on l : bool ≝ |
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| 235 | match l return λm.λ_:Vector addressing_mode_tag m.bool with |
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| 236 | [ VEmpty ⇒ false |
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| 237 | | VCons m he (tl: Vector addressing_mode_tag m) ⇒ |
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| 238 | is_a he A ∨ is_in ? tl A ]. |
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| 239 | |
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[2124] | 240 | definition is_in_cons_elim: |
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| 241 | ∀len.∀hd,tl.∀m:addressing_mode |
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| 242 | .is_in (S len) (hd:::tl) m → |
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| 243 | (bool_to_Prop (is_a hd m)) ∨ (bool_to_Prop (is_in len tl m)). |
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| 244 | #len #hd #tl #am #ISIN whd in match (is_in ???) in ISIN; |
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| 245 | cases (is_a hd am) in ISIN; /2/ |
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| 246 | qed. |
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| 247 | |
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[2128] | 248 | lemma is_in_monotonic_wrt_append: |
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| 249 | ∀m, n: nat. |
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| 250 | ∀p: Vector addressing_mode_tag m. |
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| 251 | ∀q: Vector addressing_mode_tag n. |
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| 252 | ∀to_search: addressing_mode. |
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| 253 | bool_to_Prop (is_in ? p to_search) → bool_to_Prop (is_in ? (q @@ p) to_search). |
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| 254 | #m #n #p #q #to_search #assm |
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| 255 | elim q try assumption |
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| 256 | #n' #hd #tl #inductive_hypothesis |
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| 257 | normalize |
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| 258 | cases (is_a ??) try @I |
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| 259 | >inductive_hypothesis @I |
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| 260 | qed. |
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| 261 | |
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| 262 | corollary is_in_hd_tl: |
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| 263 | ∀to_search: addressing_mode. |
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| 264 | ∀hd: addressing_mode_tag. |
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| 265 | ∀n: nat. |
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| 266 | ∀v: Vector addressing_mode_tag n. |
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| 267 | bool_to_Prop (is_in ? v to_search) → bool_to_Prop (is_in ? (hd:::v) to_search). |
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| 268 | #to_search #hd #n #v |
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| 269 | elim v |
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| 270 | [1: |
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| 271 | #absurd |
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| 272 | normalize in absurd; cases absurd |
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| 273 | |2: |
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| 274 | #n' #hd' #tl #inductive_hypothesis #assm |
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| 275 | >vector_cons_append >(vector_cons_append … hd' tl) |
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| 276 | @(is_in_monotonic_wrt_append … ([[hd']]@@tl) [[hd]] to_search) |
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| 277 | assumption |
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| 278 | ] |
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| 279 | qed. |
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| 280 | |
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[2032] | 281 | lemma is_a_to_mem_to_is_in: |
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| 282 | ∀he,a,m,q. |
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| 283 | is_a he … a = true → mem … eq_a (S m) q he = true → is_in … q a = true. |
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| 284 | #he #a #m #q |
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| 285 | elim q |
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| 286 | [1: |
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| 287 | #_ #K assumption |
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| 288 | |2: |
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| 289 | #m' #t #q' #II #H1 #H2 |
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| 290 | normalize |
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| 291 | change with (orb ??) in H2:(??%?); |
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| 292 | cases (inclusive_disjunction_true … H2) |
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| 293 | [1: |
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| 294 | #K |
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| 295 | <(eq_a_to_eq … K) >H1 % |
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| 296 | |2: |
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| 297 | #K |
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| 298 | >II |
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| 299 | try assumption |
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| 300 | cases (is_a t a) |
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| 301 | normalize |
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| 302 | % |
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| 303 | ] |
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| 304 | ] |
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| 305 | qed. |
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| 306 | |
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| 307 | lemma is_a_true_to_is_in: |
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| 308 | ∀n: nat. |
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| 309 | ∀x: addressing_mode. |
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| 310 | ∀tag: addressing_mode_tag. |
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| 311 | ∀supervector: Vector addressing_mode_tag n. |
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| 312 | mem addressing_mode_tag eq_a n supervector tag → |
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| 313 | is_a tag x = true → |
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| 314 | is_in … supervector x. |
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| 315 | #n #x #tag #supervector |
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| 316 | elim supervector |
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| 317 | [1: |
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| 318 | #absurd cases absurd |
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| 319 | |2: |
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| 320 | #n' #hd #tl #inductive_hypothesis |
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| 321 | whd in match (mem … eq_a (S n') (hd:::tl) tag); |
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| 322 | @eq_a_elim normalize nodelta |
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| 323 | [1: |
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| 324 | #tag_hd_eq #irrelevant |
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| 325 | whd in match (is_in (S n') (hd:::tl) x); |
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| 326 | <tag_hd_eq #is_a_hyp >is_a_hyp normalize nodelta |
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| 327 | @I |
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| 328 | |2: |
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| 329 | #tag_hd_neq |
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| 330 | whd in match (is_in (S n') (hd:::tl) x); |
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| 331 | change with ( |
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| 332 | mem … eq_a n' tl tag) |
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| 333 | in match (fold_right … n' ? false tl); |
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| 334 | #mem_hyp #is_a_hyp |
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| 335 | cases(is_a hd x) |
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| 336 | [1: |
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| 337 | normalize nodelta // |
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| 338 | |2: |
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| 339 | normalize nodelta |
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| 340 | @inductive_hypothesis assumption |
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| 341 | ] |
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| 342 | ] |
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| 343 | ] |
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| 344 | qed. |
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| 345 | |
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[475] | 346 | record subaddressing_mode (n) (l: Vector addressing_mode_tag (S n)) : Type[0] ≝ |
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| 347 | { |
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| 348 | subaddressing_modeel:> addressing_mode; |
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| 349 | subaddressing_modein: bool_to_Prop (is_in ? l subaddressing_modeel) |
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| 350 | }. |
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| 351 | |
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| 352 | coercion subaddressing_mode : ∀n.∀l:Vector addressing_mode_tag (S n).Type[0] |
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| 353 | ≝ subaddressing_mode on _l: Vector addressing_mode_tag (S ?) to Type[0]. |
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| 354 | |
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| 355 | coercion mk_subaddressing_mode : |
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| 356 | ∀n.∀l:Vector addressing_mode_tag (S n).∀a:addressing_mode. |
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| 357 | ∀p:bool_to_Prop (is_in ? l a).subaddressing_mode n l |
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| 358 | ≝ mk_subaddressing_mode on a:addressing_mode to subaddressing_mode ? ?. |
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[2032] | 359 | |
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| 360 | lemma is_in_subvector_is_in_supervector: |
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| 361 | ∀m, n: nat. |
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| 362 | ∀subvector: Vector addressing_mode_tag m. |
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| 363 | ∀supervector: Vector addressing_mode_tag n. |
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| 364 | ∀element: addressing_mode. |
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| 365 | subvector_with … eq_a subvector supervector → |
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| 366 | is_in m subvector element → is_in n supervector element. |
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| 367 | #m #n #subvector #supervector #element |
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| 368 | elim subvector |
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| 369 | [1: |
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| 370 | #subvector_with_proof #is_in_proof |
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| 371 | cases is_in_proof |
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| 372 | |2: |
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| 373 | #n' #hd' #tl' #inductive_hypothesis #subvector_with_proof |
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| 374 | whd in match (is_in … (hd':::tl') element); |
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| 375 | cases (is_a_decidable hd' element) |
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| 376 | [1: |
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| 377 | #is_a_true >is_a_true |
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| 378 | #irrelevant |
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| 379 | whd in match (subvector_with … eq_a (hd':::tl') supervector) in subvector_with_proof; |
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| 380 | @(is_a_true_to_is_in … is_a_true) |
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| 381 | lapply(subvector_with_proof) |
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| 382 | cases(mem … eq_a n supervector hd') // |
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| 383 | |2: |
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| 384 | #is_a_false >is_a_false normalize nodelta |
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| 385 | #assm |
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| 386 | @inductive_hypothesis |
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| 387 | [1: |
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| 388 | generalize in match subvector_with_proof; |
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| 389 | whd in match (subvector_with … eq_a (hd':::tl') supervector); |
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| 390 | cases(mem_decidable n supervector hd') |
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| 391 | [1: |
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| 392 | #mem_true >mem_true normalize nodelta |
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| 393 | #assm assumption |
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| 394 | |2: |
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| 395 | #mem_false >mem_false #absurd |
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| 396 | cases absurd |
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| 397 | ] |
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| 398 | |2: |
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| 399 | assumption |
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| 400 | ] |
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| 401 | ] |
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| 402 | ] |
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| 403 | qed. |
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| 404 | |
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| 405 | |
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| 406 | let rec subaddressing_mode_elim_type |
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| 407 | (m: nat) (fixed_v: Vector addressing_mode_tag (S m)) (origaddr: fixed_v) |
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| 408 | (Q: fixed_v → Prop) |
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| 409 | (n: nat) (v: Vector addressing_mode_tag n) (proof: subvector_with … eq_a v fixed_v) |
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| 410 | on v: Prop ≝ |
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| 411 | match v return λo: nat. λv': Vector addressing_mode_tag o. o = n → v ≃ v' → ? with |
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| 412 | [ VEmpty ⇒ λm_refl. λv_refl. Q origaddr |
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| 413 | | VCons n' hd tl ⇒ λm_refl. λv_refl. |
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| 414 | let tail_call ≝ subaddressing_mode_elim_type m fixed_v origaddr Q n' tl ? |
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| 415 | in |
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| 416 | match hd return λa: addressing_mode_tag. a = hd → ? with |
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| 417 | [ addr11 ⇒ λhd_refl. (∀w: Word11. Q (ADDR11 w)) → tail_call |
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| 418 | | addr16 ⇒ λhd_refl. (∀w: Word. Q (ADDR16 w)) → tail_call |
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| 419 | | direct ⇒ λhd_refl. (∀w: Byte. Q (DIRECT w)) → tail_call |
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| 420 | | indirect ⇒ λhd_refl. (∀w: Bit. Q (INDIRECT w)) → tail_call |
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| 421 | | ext_indirect ⇒ λhd_refl. (∀w: Bit. Q (EXT_INDIRECT w)) → tail_call |
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| 422 | | acc_a ⇒ λhd_refl. Q ACC_A → tail_call |
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| 423 | | registr ⇒ λhd_refl. (∀w: BitVector 3. Q (REGISTER w)) → tail_call |
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| 424 | | acc_b ⇒ λhd_refl. Q ACC_B → tail_call |
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| 425 | | dptr ⇒ λhd_refl. Q DPTR → tail_call |
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| 426 | | data ⇒ λhd_refl. (∀w: Byte. Q (DATA w)) → tail_call |
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| 427 | | data16 ⇒ λhd_refl. (∀w: Word. Q (DATA16 w)) → tail_call |
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| 428 | | acc_dptr ⇒ λhd_refl. Q ACC_DPTR → tail_call |
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| 429 | | acc_pc ⇒ λhd_refl. Q ACC_PC → tail_call |
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| 430 | | ext_indirect_dptr ⇒ λhd_refl. Q EXT_INDIRECT_DPTR → tail_call |
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| 431 | | indirect_dptr ⇒ λhd_refl. Q INDIRECT_DPTR → tail_call |
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| 432 | | carry ⇒ λhd_refl. Q CARRY → tail_call |
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| 433 | | bit_addr ⇒ λhd_refl. (∀w: Byte. Q (BIT_ADDR w)) → tail_call |
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| 434 | | n_bit_addr ⇒ λhd_refl. (∀w: Byte. Q (N_BIT_ADDR w)) → tail_call |
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| 435 | | relative ⇒ λhd_refl. (∀w: Byte. Q (RELATIVE w)) → tail_call |
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| 436 | ] (refl … hd) |
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| 437 | ] (refl … n) (refl_jmeq … v). |
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| 438 | [20: |
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| 439 | generalize in match proof; destruct |
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| 440 | whd in match (subvector_with … eq_a (hd:::tl) fixed_v); |
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| 441 | cases (mem … eq_a ? fixed_v hd) normalize nodelta |
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| 442 | [1: |
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| 443 | whd in match (subvector_with … eq_a tl fixed_v); |
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| 444 | #assm assumption |
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| 445 | |2: |
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| 446 | normalize in ⊢ (% → ?); |
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| 447 | #absurd cases absurd |
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| 448 | ] |
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| 449 | ] |
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| 450 | @(is_in_subvector_is_in_supervector … proof) |
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| 451 | destruct @I |
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| 452 | qed. |
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| 453 | |
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| 454 | lemma subaddressing_mode_elim0: |
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| 455 | ∀n: nat. |
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| 456 | ∀v: Vector addressing_mode_tag (S n). |
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| 457 | ∀addr: v. |
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| 458 | ∀Q: v → Prop. |
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| 459 | ∀m,w,H. |
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| 460 | (∀xaddr: v. ¬ is_in … w xaddr → Q xaddr) → |
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| 461 | subaddressing_mode_elim_type n v addr Q m w H. |
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| 462 | #n #v #addr #Q #m #w elim w |
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| 463 | [ /2/ |
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| 464 | | #n' #hd #tl #IH cases hd #H |
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| 465 | #INV whd #PO @IH #xaddr cases xaddr * |
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| 466 | try (#b #IS_IN #ALREADYSEEN) try (#IS_IN #ALREADYSEEN) try @PO @INV |
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| 467 | @ALREADYSEEN ] |
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| 468 | qed. |
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| 469 | |
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| 470 | lemma subaddressing_mode_elim: |
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| 471 | ∀n: nat. |
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| 472 | ∀v: Vector addressing_mode_tag (S n). |
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| 473 | ∀addr: v. |
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| 474 | ∀Q: v → Prop. |
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| 475 | subaddressing_mode_elim_type n v addr Q (S n) v ?. |
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| 476 | [ #n #v #addr #Q @subaddressing_mode_elim0 * #el #H #NH @⊥ >H in NH; // |
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| 477 | | @subvector_with_refl @eq_a_reflexive |
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| 478 | ] |
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| 479 | qed. |
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[832] | 480 | |
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[475] | 481 | inductive preinstruction (A: Type[0]) : Type[0] ≝ |
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[757] | 482 | ADD: [[acc_a]] → [[ registr ; direct ; indirect ; data ]] → preinstruction A |
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| 483 | | ADDC: [[acc_a]] → [[ registr ; direct ; indirect ; data ]] → preinstruction A |
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| 484 | | SUBB: [[acc_a]] → [[ registr ; direct ; indirect ; data ]] → preinstruction A |
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| 485 | | INC: [[ acc_a ; registr ; direct ; indirect ; dptr ]] → preinstruction A |
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| 486 | | DEC: [[ acc_a ; registr ; direct ; indirect ]] → preinstruction A |
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[475] | 487 | | MUL: [[acc_a]] → [[acc_b]] → preinstruction A |
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| 488 | | DIV: [[acc_a]] → [[acc_b]] → preinstruction A |
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| 489 | | DA: [[acc_a]] → preinstruction A |
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| 490 | |
---|
[820] | 491 | (* conditional jumps *) |
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| 492 | | JC: A → preinstruction A |
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| 493 | | JNC: A → preinstruction A |
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| 494 | | JB: [[bit_addr]] → A → preinstruction A |
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| 495 | | JNB: [[bit_addr]] → A → preinstruction A |
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| 496 | | JBC: [[bit_addr]] → A → preinstruction A |
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| 497 | | JZ: A → preinstruction A |
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| 498 | | JNZ: A → preinstruction A |
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| 499 | | CJNE: |
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| 500 | [[acc_a]] × [[direct; data]] ⊎ [[registr; indirect]] × [[data]] → A → preinstruction A |
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| 501 | | DJNZ: [[registr ; direct]] → A → preinstruction A |
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[475] | 502 | (* logical operations *) |
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| 503 | | ANL: |
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[757] | 504 | [[acc_a]] × [[ registr ; direct ; indirect ; data ]] ⊎ |
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[475] | 505 | [[direct]] × [[ acc_a ; data ]] ⊎ |
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| 506 | [[carry]] × [[ bit_addr ; n_bit_addr]] → preinstruction A |
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| 507 | | ORL: |
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[757] | 508 | [[acc_a]] × [[ registr ; data ; direct ; indirect ]] ⊎ |
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[475] | 509 | [[direct]] × [[ acc_a ; data ]] ⊎ |
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| 510 | [[carry]] × [[ bit_addr ; n_bit_addr]] → preinstruction A |
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| 511 | | XRL: |
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[757] | 512 | [[acc_a]] × [[ data ; registr ; direct ; indirect ]] ⊎ |
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[475] | 513 | [[direct]] × [[ acc_a ; data ]] → preinstruction A |
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| 514 | | CLR: [[ acc_a ; carry ; bit_addr ]] → preinstruction A |
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| 515 | | CPL: [[ acc_a ; carry ; bit_addr ]] → preinstruction A |
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| 516 | | RL: [[acc_a]] → preinstruction A |
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| 517 | | RLC: [[acc_a]] → preinstruction A |
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| 518 | | RR: [[acc_a]] → preinstruction A |
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| 519 | | RRC: [[acc_a]] → preinstruction A |
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| 520 | | SWAP: [[acc_a]] → preinstruction A |
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| 521 | |
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| 522 | (* data transfer *) |
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| 523 | | MOV: |
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[757] | 524 | [[acc_a]] × [[ registr ; direct ; indirect ; data ]] ⊎ |
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| 525 | [[ registr ; indirect ]] × [[ acc_a ; direct ; data ]] ⊎ |
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| 526 | [[direct]] × [[ acc_a ; registr ; direct ; indirect ; data ]] ⊎ |
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[475] | 527 | [[dptr]] × [[data16]] ⊎ |
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| 528 | [[carry]] × [[bit_addr]] ⊎ |
---|
| 529 | [[bit_addr]] × [[carry]] → preinstruction A |
---|
| 530 | | MOVX: |
---|
| 531 | [[acc_a]] × [[ ext_indirect ; ext_indirect_dptr ]] ⊎ |
---|
| 532 | [[ ext_indirect ; ext_indirect_dptr ]] × [[acc_a]] → preinstruction A |
---|
| 533 | | SETB: [[ carry ; bit_addr ]] → preinstruction A |
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| 534 | | PUSH: [[direct]] → preinstruction A |
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| 535 | | POP: [[direct]] → preinstruction A |
---|
[757] | 536 | | XCH: [[acc_a]] → [[ registr ; direct ; indirect ]] → preinstruction A |
---|
[475] | 537 | | XCHD: [[acc_a]] → [[indirect]] → preinstruction A |
---|
| 538 | |
---|
| 539 | (* program branching *) |
---|
| 540 | | RET: preinstruction A |
---|
| 541 | | RETI: preinstruction A |
---|
| 542 | | NOP: preinstruction A. |
---|
| 543 | |
---|
[2124] | 544 | definition eq_preinstruction: preinstruction [[relative]] → preinstruction [[relative]] → bool ≝ |
---|
| 545 | λi, j. |
---|
| 546 | match i with |
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| 547 | [ ADD arg1 arg2 ⇒ |
---|
| 548 | match j with |
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| 549 | [ ADD arg1' arg2' ⇒ eq_addressing_mode arg1 arg1' ∧ eq_addressing_mode arg2 arg2' |
---|
| 550 | | _ ⇒ false |
---|
| 551 | ] |
---|
| 552 | | ADDC arg1 arg2 ⇒ |
---|
| 553 | match j with |
---|
| 554 | [ ADDC arg1' arg2' ⇒ eq_addressing_mode arg1 arg1' ∧ eq_addressing_mode arg2 arg2' |
---|
| 555 | | _ ⇒ false |
---|
| 556 | ] |
---|
| 557 | | SUBB arg1 arg2 ⇒ |
---|
| 558 | match j with |
---|
| 559 | [ SUBB arg1' arg2' ⇒ eq_addressing_mode arg1 arg1' ∧ eq_addressing_mode arg2 arg2' |
---|
| 560 | | _ ⇒ false |
---|
| 561 | ] |
---|
| 562 | | INC arg ⇒ |
---|
| 563 | match j with |
---|
| 564 | [ INC arg' ⇒ eq_addressing_mode arg arg' |
---|
| 565 | | _ ⇒ false |
---|
| 566 | ] |
---|
| 567 | | DEC arg ⇒ |
---|
| 568 | match j with |
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| 569 | [ DEC arg' ⇒ eq_addressing_mode arg arg' |
---|
| 570 | | _ ⇒ false |
---|
| 571 | ] |
---|
| 572 | | MUL arg1 arg2 ⇒ |
---|
| 573 | match j with |
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| 574 | [ MUL arg1' arg2' ⇒ eq_addressing_mode arg1 arg1' ∧ eq_addressing_mode arg2 arg2' |
---|
| 575 | | _ ⇒ false |
---|
| 576 | ] |
---|
| 577 | | DIV arg1 arg2 ⇒ |
---|
| 578 | match j with |
---|
| 579 | [ DIV arg1' arg2' ⇒ eq_addressing_mode arg1 arg1' ∧ eq_addressing_mode arg2 arg2' |
---|
| 580 | | _ ⇒ false |
---|
| 581 | ] |
---|
| 582 | | DA arg ⇒ |
---|
| 583 | match j with |
---|
| 584 | [ DA arg' ⇒ eq_addressing_mode arg arg' |
---|
| 585 | | _ ⇒ false |
---|
| 586 | ] |
---|
| 587 | | JC arg ⇒ |
---|
| 588 | match j with |
---|
| 589 | [ JC arg' ⇒ eq_addressing_mode arg arg' |
---|
| 590 | | _ ⇒ false |
---|
| 591 | ] |
---|
| 592 | | JNC arg ⇒ |
---|
| 593 | match j with |
---|
| 594 | [ JNC arg' ⇒ eq_addressing_mode arg arg' |
---|
| 595 | | _ ⇒ false |
---|
| 596 | ] |
---|
| 597 | | JB arg1 arg2 ⇒ |
---|
| 598 | match j with |
---|
| 599 | [ JB arg1' arg2' ⇒ eq_addressing_mode arg1 arg1' ∧ eq_addressing_mode arg2 arg2' |
---|
| 600 | | _ ⇒ false |
---|
| 601 | ] |
---|
| 602 | | JNB arg1 arg2 ⇒ |
---|
| 603 | match j with |
---|
| 604 | [ JNB arg1' arg2' ⇒ eq_addressing_mode arg1 arg1' ∧ eq_addressing_mode arg2 arg2' |
---|
| 605 | | _ ⇒ false |
---|
| 606 | ] |
---|
| 607 | | JBC arg1 arg2 ⇒ |
---|
| 608 | match j with |
---|
| 609 | [ JBC arg1' arg2' ⇒ eq_addressing_mode arg1 arg1' ∧ eq_addressing_mode arg2 arg2' |
---|
| 610 | | _ ⇒ false |
---|
| 611 | ] |
---|
| 612 | | JZ arg ⇒ |
---|
| 613 | match j with |
---|
| 614 | [ JZ arg' ⇒ eq_addressing_mode arg arg' |
---|
| 615 | | _ ⇒ false |
---|
| 616 | ] |
---|
| 617 | | JNZ arg ⇒ |
---|
| 618 | match j with |
---|
| 619 | [ JNZ arg' ⇒ eq_addressing_mode arg arg' |
---|
| 620 | | _ ⇒ false |
---|
| 621 | ] |
---|
| 622 | | CJNE arg1 arg2 ⇒ |
---|
| 623 | match j with |
---|
| 624 | [ CJNE arg1' arg2' ⇒ |
---|
| 625 | let prod_eq_left ≝ eq_prod [[acc_a]] [[direct; data]] eq_addressing_mode eq_addressing_mode in |
---|
| 626 | let prod_eq_right ≝ eq_prod [[registr; indirect]] [[data]] eq_addressing_mode eq_addressing_mode in |
---|
| 627 | let arg1_eq ≝ eq_sum ? ? prod_eq_left prod_eq_right in |
---|
| 628 | arg1_eq arg1 arg1' ∧ eq_addressing_mode arg2 arg2' |
---|
| 629 | | _ ⇒ false |
---|
| 630 | ] |
---|
| 631 | | DJNZ arg1 arg2 ⇒ |
---|
| 632 | match j with |
---|
| 633 | [ DJNZ arg1' arg2' ⇒ eq_addressing_mode arg1 arg1' ∧ eq_addressing_mode arg2 arg2' |
---|
| 634 | | _ ⇒ false |
---|
| 635 | ] |
---|
| 636 | | CLR arg ⇒ |
---|
| 637 | match j with |
---|
| 638 | [ CLR arg' ⇒ eq_addressing_mode arg arg' |
---|
| 639 | | _ ⇒ false |
---|
| 640 | ] |
---|
| 641 | | CPL arg ⇒ |
---|
| 642 | match j with |
---|
| 643 | [ CPL arg' ⇒ eq_addressing_mode arg arg' |
---|
| 644 | | _ ⇒ false |
---|
| 645 | ] |
---|
| 646 | | RL arg ⇒ |
---|
| 647 | match j with |
---|
| 648 | [ RL arg' ⇒ eq_addressing_mode arg arg' |
---|
| 649 | | _ ⇒ false |
---|
| 650 | ] |
---|
| 651 | | RLC arg ⇒ |
---|
| 652 | match j with |
---|
| 653 | [ RLC arg' ⇒ eq_addressing_mode arg arg' |
---|
| 654 | | _ ⇒ false |
---|
| 655 | ] |
---|
| 656 | | RR arg ⇒ |
---|
| 657 | match j with |
---|
| 658 | [ RR arg' ⇒ eq_addressing_mode arg arg' |
---|
| 659 | | _ ⇒ false |
---|
| 660 | ] |
---|
| 661 | | RRC arg ⇒ |
---|
| 662 | match j with |
---|
| 663 | [ RRC arg' ⇒ eq_addressing_mode arg arg' |
---|
| 664 | | _ ⇒ false |
---|
| 665 | ] |
---|
| 666 | | SWAP arg ⇒ |
---|
| 667 | match j with |
---|
| 668 | [ SWAP arg' ⇒ eq_addressing_mode arg arg' |
---|
| 669 | | _ ⇒ false |
---|
| 670 | ] |
---|
| 671 | | SETB arg ⇒ |
---|
| 672 | match j with |
---|
| 673 | [ SETB arg' ⇒ eq_addressing_mode arg arg' |
---|
| 674 | | _ ⇒ false |
---|
| 675 | ] |
---|
| 676 | | PUSH arg ⇒ |
---|
| 677 | match j with |
---|
| 678 | [ PUSH arg' ⇒ eq_addressing_mode arg arg' |
---|
| 679 | | _ ⇒ false |
---|
| 680 | ] |
---|
| 681 | | POP arg ⇒ |
---|
| 682 | match j with |
---|
| 683 | [ POP arg' ⇒ eq_addressing_mode arg arg' |
---|
| 684 | | _ ⇒ false |
---|
| 685 | ] |
---|
| 686 | | XCH arg1 arg2 ⇒ |
---|
| 687 | match j with |
---|
| 688 | [ XCH arg1' arg2' ⇒ eq_addressing_mode arg1 arg1' ∧ eq_addressing_mode arg2 arg2' |
---|
| 689 | | _ ⇒ false |
---|
| 690 | ] |
---|
| 691 | | XCHD arg1 arg2 ⇒ |
---|
| 692 | match j with |
---|
| 693 | [ XCHD arg1' arg2' ⇒ eq_addressing_mode arg1 arg1' ∧ eq_addressing_mode arg2 arg2' |
---|
| 694 | | _ ⇒ false |
---|
| 695 | ] |
---|
| 696 | | RET ⇒ match j with [ RET ⇒ true | _ ⇒ false ] |
---|
| 697 | | RETI ⇒ match j with [ RETI ⇒ true | _ ⇒ false ] |
---|
| 698 | | NOP ⇒ match j with [ NOP ⇒ true | _ ⇒ false ] |
---|
| 699 | | MOVX arg ⇒ |
---|
| 700 | match j with |
---|
| 701 | [ MOVX arg' ⇒ |
---|
| 702 | let prod_eq_left ≝ eq_prod [[acc_a]] [[ext_indirect; ext_indirect_dptr]] eq_addressing_mode eq_addressing_mode in |
---|
| 703 | let prod_eq_right ≝ eq_prod [[ext_indirect; ext_indirect_dptr]] [[acc_a]] eq_addressing_mode eq_addressing_mode in |
---|
| 704 | let sum_eq ≝ eq_sum ? ? prod_eq_left prod_eq_right in |
---|
| 705 | sum_eq arg arg' |
---|
| 706 | | _ ⇒ false |
---|
| 707 | ] |
---|
| 708 | | XRL arg ⇒ |
---|
| 709 | match j with |
---|
| 710 | [ XRL arg' ⇒ |
---|
| 711 | let prod_eq_left ≝ eq_prod [[acc_a]] [[ data ; registr ; direct ; indirect ]] eq_addressing_mode eq_addressing_mode in |
---|
| 712 | let prod_eq_right ≝ eq_prod [[direct]] [[ acc_a ; data ]] eq_addressing_mode eq_addressing_mode in |
---|
| 713 | let sum_eq ≝ eq_sum ? ? prod_eq_left prod_eq_right in |
---|
| 714 | sum_eq arg arg' |
---|
| 715 | | _ ⇒ false |
---|
| 716 | ] |
---|
| 717 | | ORL arg ⇒ |
---|
| 718 | match j with |
---|
| 719 | [ ORL arg' ⇒ |
---|
| 720 | let prod_eq_left1 ≝ eq_prod [[acc_a]] [[ registr ; data ; direct ; indirect ]] eq_addressing_mode eq_addressing_mode in |
---|
| 721 | let prod_eq_left2 ≝ eq_prod [[direct]] [[ acc_a; data ]] eq_addressing_mode eq_addressing_mode in |
---|
| 722 | let prod_eq_left ≝ eq_sum ? ? prod_eq_left1 prod_eq_left2 in |
---|
| 723 | let prod_eq_right ≝ eq_prod [[carry]] [[ bit_addr ; n_bit_addr]] eq_addressing_mode eq_addressing_mode in |
---|
| 724 | let sum_eq ≝ eq_sum ? ? prod_eq_left prod_eq_right in |
---|
| 725 | sum_eq arg arg' |
---|
| 726 | | _ ⇒ false |
---|
| 727 | ] |
---|
| 728 | | ANL arg ⇒ |
---|
| 729 | match j with |
---|
| 730 | [ ANL arg' ⇒ |
---|
| 731 | let prod_eq_left1 ≝ eq_prod [[acc_a]] [[ registr ; direct ; indirect ; data ]] eq_addressing_mode eq_addressing_mode in |
---|
| 732 | let prod_eq_left2 ≝ eq_prod [[direct]] [[ acc_a; data ]] eq_addressing_mode eq_addressing_mode in |
---|
| 733 | let prod_eq_left ≝ eq_sum ? ? prod_eq_left1 prod_eq_left2 in |
---|
| 734 | let prod_eq_right ≝ eq_prod [[carry]] [[ bit_addr ; n_bit_addr]] eq_addressing_mode eq_addressing_mode in |
---|
| 735 | let sum_eq ≝ eq_sum ? ? prod_eq_left prod_eq_right in |
---|
| 736 | sum_eq arg arg' |
---|
| 737 | | _ ⇒ false |
---|
| 738 | ] |
---|
| 739 | | MOV arg ⇒ |
---|
| 740 | match j with |
---|
| 741 | [ MOV arg' ⇒ |
---|
| 742 | let prod_eq_6 ≝ eq_prod [[acc_a]] [[registr; direct; indirect; data]] eq_addressing_mode eq_addressing_mode in |
---|
| 743 | let prod_eq_5 ≝ eq_prod [[registr; indirect]] [[acc_a; direct; data]] eq_addressing_mode eq_addressing_mode in |
---|
| 744 | let prod_eq_4 ≝ eq_prod [[direct]] [[acc_a; registr; direct; indirect; data]] eq_addressing_mode eq_addressing_mode in |
---|
| 745 | let prod_eq_3 ≝ eq_prod [[dptr]] [[data16]] eq_addressing_mode eq_addressing_mode in |
---|
| 746 | let prod_eq_2 ≝ eq_prod [[carry]] [[bit_addr]] eq_addressing_mode eq_addressing_mode in |
---|
| 747 | let prod_eq_1 ≝ eq_prod [[bit_addr]] [[carry]] eq_addressing_mode eq_addressing_mode in |
---|
| 748 | let sum_eq_1 ≝ eq_sum ? ? prod_eq_6 prod_eq_5 in |
---|
| 749 | let sum_eq_2 ≝ eq_sum ? ? sum_eq_1 prod_eq_4 in |
---|
| 750 | let sum_eq_3 ≝ eq_sum ? ? sum_eq_2 prod_eq_3 in |
---|
| 751 | let sum_eq_4 ≝ eq_sum ? ? sum_eq_3 prod_eq_2 in |
---|
| 752 | let sum_eq_5 ≝ eq_sum ? ? sum_eq_4 prod_eq_1 in |
---|
| 753 | sum_eq_5 arg arg' |
---|
| 754 | | _ ⇒ false |
---|
| 755 | ] |
---|
| 756 | ]. |
---|
| 757 | |
---|
| 758 | lemma eq_preinstruction_refl: |
---|
| 759 | ∀i. |
---|
| 760 | eq_preinstruction i i = true. |
---|
| 761 | #i cases i try #arg1 try #arg2 |
---|
| 762 | try @eq_addressing_mode_refl |
---|
| 763 | [1,2,3,4,5,6,7,8,10,16,17,18,19,20: |
---|
| 764 | whd in ⊢ (??%?); try % |
---|
| 765 | >eq_addressing_mode_refl |
---|
| 766 | >eq_addressing_mode_refl % |
---|
| 767 | |13,15: |
---|
| 768 | whd in ⊢ (??%?); |
---|
| 769 | cases arg1 |
---|
| 770 | [*: |
---|
| 771 | #arg1_left normalize nodelta |
---|
| 772 | >eq_prod_refl [*: try % #argr @eq_addressing_mode_refl] |
---|
| 773 | ] |
---|
| 774 | |11,12: |
---|
| 775 | whd in ⊢ (??%?); |
---|
| 776 | cases arg1 |
---|
| 777 | [1: |
---|
| 778 | #arg1_left normalize nodelta |
---|
| 779 | >(eq_sum_refl …) |
---|
| 780 | [1: % | 2,3: #arg @eq_prod_refl ] |
---|
| 781 | @eq_addressing_mode_refl |
---|
| 782 | |2: |
---|
| 783 | #arg1_left normalize nodelta |
---|
| 784 | @eq_prod_refl [*: @eq_addressing_mode_refl ] |
---|
| 785 | |3: |
---|
| 786 | #arg1_left normalize nodelta |
---|
| 787 | >(eq_sum_refl …) |
---|
| 788 | [1: |
---|
| 789 | % |
---|
| 790 | |2,3: |
---|
| 791 | #arg @eq_prod_refl #arg @eq_addressing_mode_refl |
---|
| 792 | ] |
---|
| 793 | |4: |
---|
| 794 | #arg1_left normalize nodelta |
---|
| 795 | @eq_prod_refl [*: #arg @eq_addressing_mode_refl ] |
---|
| 796 | ] |
---|
| 797 | |14: |
---|
| 798 | whd in ⊢ (??%?); |
---|
| 799 | cases arg1 |
---|
| 800 | [1: |
---|
| 801 | #arg1_left normalize nodelta |
---|
| 802 | @eq_sum_refl |
---|
| 803 | [1: |
---|
| 804 | #arg @eq_sum_refl |
---|
| 805 | [1: |
---|
| 806 | #arg @eq_sum_refl |
---|
| 807 | [1: |
---|
| 808 | #arg @eq_sum_refl |
---|
| 809 | [1: |
---|
| 810 | #arg @eq_prod_refl |
---|
| 811 | [*: |
---|
| 812 | @eq_addressing_mode_refl |
---|
| 813 | ] |
---|
| 814 | |2: |
---|
| 815 | #arg @eq_prod_refl |
---|
| 816 | [*: |
---|
| 817 | #arg @eq_addressing_mode_refl |
---|
| 818 | ] |
---|
| 819 | ] |
---|
| 820 | |2: |
---|
| 821 | #arg @eq_prod_refl |
---|
| 822 | [*: |
---|
| 823 | #arg @eq_addressing_mode_refl |
---|
| 824 | ] |
---|
| 825 | ] |
---|
| 826 | |2: |
---|
| 827 | #arg @eq_prod_refl |
---|
| 828 | [*: |
---|
| 829 | #arg @eq_addressing_mode_refl |
---|
| 830 | ] |
---|
| 831 | ] |
---|
| 832 | |2: |
---|
| 833 | #arg @eq_prod_refl |
---|
| 834 | [*: |
---|
| 835 | #arg @eq_addressing_mode_refl |
---|
| 836 | ] |
---|
| 837 | ] |
---|
| 838 | |2: |
---|
| 839 | #arg1_right normalize nodelta |
---|
| 840 | @eq_prod_refl |
---|
| 841 | [*: |
---|
| 842 | #arg @eq_addressing_mode_refl |
---|
| 843 | ] |
---|
| 844 | ] |
---|
| 845 | |*: |
---|
| 846 | whd in ⊢ (??%?); |
---|
| 847 | cases arg1 |
---|
| 848 | [*: |
---|
| 849 | #arg1 >eq_sum_refl |
---|
| 850 | [1,4: |
---|
| 851 | @eq_addressing_mode_refl |
---|
| 852 | |2,3,5,6: |
---|
| 853 | #arg @eq_prod_refl |
---|
| 854 | [*: |
---|
| 855 | #arg @eq_addressing_mode_refl |
---|
| 856 | ] |
---|
| 857 | ] |
---|
| 858 | ] |
---|
| 859 | ] |
---|
| 860 | qed. |
---|
| 861 | |
---|
[820] | 862 | inductive instruction: Type[0] ≝ |
---|
| 863 | | ACALL: [[addr11]] → instruction |
---|
| 864 | | LCALL: [[addr16]] → instruction |
---|
| 865 | | AJMP: [[addr11]] → instruction |
---|
| 866 | | LJMP: [[addr16]] → instruction |
---|
| 867 | | SJMP: [[relative]] → instruction |
---|
| 868 | | JMP: [[indirect_dptr]] → instruction |
---|
| 869 | | MOVC: [[acc_a]] → [[ acc_dptr ; acc_pc ]] → instruction |
---|
| 870 | | RealInstruction: preinstruction [[ relative ]] → instruction. |
---|
| 871 | |
---|
| 872 | coercion RealInstruction: ∀p: preinstruction [[ relative ]]. instruction ≝ |
---|
| 873 | RealInstruction on _p: preinstruction ? to instruction. |
---|
[475] | 874 | |
---|
[2124] | 875 | definition eq_instruction: instruction → instruction → bool ≝ |
---|
| 876 | λi, j. |
---|
| 877 | match i with |
---|
| 878 | [ ACALL arg ⇒ |
---|
| 879 | match j with |
---|
| 880 | [ ACALL arg' ⇒ eq_addressing_mode arg arg' |
---|
| 881 | | _ ⇒ false |
---|
| 882 | ] |
---|
| 883 | | LCALL arg ⇒ |
---|
| 884 | match j with |
---|
| 885 | [ LCALL arg' ⇒ eq_addressing_mode arg arg' |
---|
| 886 | | _ ⇒ false |
---|
| 887 | ] |
---|
| 888 | | AJMP arg ⇒ |
---|
| 889 | match j with |
---|
| 890 | [ AJMP arg' ⇒ eq_addressing_mode arg arg' |
---|
| 891 | | _ ⇒ false |
---|
| 892 | ] |
---|
| 893 | | LJMP arg ⇒ |
---|
| 894 | match j with |
---|
| 895 | [ LJMP arg' ⇒ eq_addressing_mode arg arg' |
---|
| 896 | | _ ⇒ false |
---|
| 897 | ] |
---|
| 898 | | SJMP arg ⇒ |
---|
| 899 | match j with |
---|
| 900 | [ SJMP arg' ⇒ eq_addressing_mode arg arg' |
---|
| 901 | | _ ⇒ false |
---|
| 902 | ] |
---|
| 903 | | JMP arg ⇒ |
---|
| 904 | match j with |
---|
| 905 | [ JMP arg' ⇒ eq_addressing_mode arg arg' |
---|
| 906 | | _ ⇒ false |
---|
| 907 | ] |
---|
| 908 | | MOVC arg1 arg2 ⇒ |
---|
| 909 | match j with |
---|
| 910 | [ MOVC arg1' arg2' ⇒ eq_addressing_mode arg1 arg1' ∧ eq_addressing_mode arg2 arg2' |
---|
| 911 | | _ ⇒ false |
---|
| 912 | ] |
---|
| 913 | | RealInstruction instr ⇒ |
---|
| 914 | match j with |
---|
| 915 | [ RealInstruction instr' ⇒ eq_preinstruction instr instr' |
---|
| 916 | | _ ⇒ false |
---|
| 917 | ] |
---|
| 918 | ]. |
---|
| 919 | |
---|
| 920 | lemma eq_instruction_refl: |
---|
| 921 | ∀i. eq_instruction i i = true. |
---|
| 922 | #i cases i [*: #arg1 ] |
---|
| 923 | try @eq_addressing_mode_refl |
---|
| 924 | try @eq_preinstruction_refl |
---|
| 925 | #arg2 whd in ⊢ (??%?); |
---|
| 926 | >eq_addressing_mode_refl >eq_addressing_mode_refl % |
---|
| 927 | qed. |
---|
| 928 | |
---|
| 929 | lemma eq_instruction_to_eq: |
---|
| 930 | ∀i1, i2: instruction. |
---|
| 931 | eq_instruction i1 i2 = true → i1 ≃ i2. |
---|
| 932 | #i1 #i2 |
---|
| 933 | cases i1 cases i2 cases daemon (* easy but tedious |
---|
| 934 | [1,10,19,28,37,46: |
---|
| 935 | #arg1 #arg2 |
---|
| 936 | whd in match (eq_instruction ??); |
---|
| 937 | cases arg1 #subaddressing_mode |
---|
| 938 | cases subaddressing_mode |
---|
| 939 | try (#arg1' #arg2' normalize in ⊢ (% → ?); #absurd cases absurd @I) |
---|
| 940 | try (#arg1' normalize in ⊢ (% → ?); #absurd cases absurd @I) |
---|
| 941 | try (normalize in ⊢ (% → ?); #absurd cases absurd @I) |
---|
| 942 | #word11 #irrelevant |
---|
| 943 | cases arg2 #subaddressing_mode |
---|
| 944 | cases subaddressing_mode |
---|
| 945 | try (#arg1' #arg2' normalize in ⊢ (% → ?); #absurd cases absurd @I) |
---|
| 946 | try (#arg1' normalize in ⊢ (% → ?); #absurd cases absurd @I) |
---|
| 947 | try (normalize in ⊢ (% → ?); #absurd cases absurd @I) |
---|
| 948 | #word11' #irrelevant normalize nodelta |
---|
| 949 | #eq_bv_assm cases (eq_bv_eq … eq_bv_assm) % *) |
---|
| 950 | qed. |
---|
| 951 | |
---|
[722] | 952 | inductive pseudo_instruction: Type[0] ≝ |
---|
[820] | 953 | | Instruction: preinstruction Identifier → pseudo_instruction |
---|
| 954 | | Comment: String → pseudo_instruction |
---|
[1515] | 955 | | Cost: costlabel → pseudo_instruction |
---|
[820] | 956 | | Jmp: Identifier → pseudo_instruction |
---|
| 957 | | Call: Identifier → pseudo_instruction |
---|
| 958 | | Mov: [[dptr]] → Identifier → pseudo_instruction. |
---|
[475] | 959 | |
---|
[1882] | 960 | definition labelled_instruction ≝ labelled_obj ASMTag pseudo_instruction. |
---|
[1522] | 961 | definition preamble ≝ (identifier_map SymbolTag nat) × (list (Identifier × Word)). |
---|
[820] | 962 | definition assembly_program ≝ list instruction. |
---|
| 963 | definition pseudo_assembly_program ≝ preamble × (list labelled_instruction). |
---|
[2123] | 964 | |
---|
| 965 | (* labels & instructions *) |
---|
| 966 | definition instruction_has_label ≝ |
---|
| 967 | λid: Identifier. |
---|
| 968 | λi. |
---|
| 969 | match i with |
---|
| 970 | [ Jmp j ⇒ j = id |
---|
| 971 | | Call j ⇒ j = id |
---|
| 972 | | Instruction instr ⇒ |
---|
| 973 | match instr with |
---|
| 974 | [ JC j ⇒ j = id |
---|
| 975 | | JNC j ⇒ j = id |
---|
| 976 | | JZ j ⇒ j = id |
---|
| 977 | | JNZ j ⇒ j = id |
---|
| 978 | | JB _ j ⇒ j = id |
---|
| 979 | | JBC _ j ⇒ j = id |
---|
| 980 | | DJNZ _ j ⇒ j = id |
---|
| 981 | | CJNE _ j ⇒ j = id |
---|
| 982 | | _ ⇒ False |
---|
| 983 | ] |
---|
| 984 | | _ ⇒ False |
---|
[2128] | 985 | ]. |
---|