source: extracted/rTL.ml @ 2717

Last change on this file since 2717 was 2717, checked in by sacerdot, 7 years ago

Extracted code for the whole compiler.
The space cost model is not there yet.

I have fixed by hand the few extraction problems
(i.e. composed coercions not extracted and type
definitions with wrong syntax).

I have also changed all axioms to be implemented
so that they do not fail at initialization time.

File size: 3.9 KB
Line 
1open Preamble
2
3open String
4
5open Sets
6
7open Listb
8
9open LabelledObjects
10
11open Graphs
12
13open I8051
14
15open Order
16
17open Registers
18
19open BitVectorTrie
20
21open CostLabel
22
23open Hide
24
25open Proper
26
27open PositiveMap
28
29open Deqsets
30
31open ErrorMessages
32
33open PreIdentifiers
34
35open Errors
36
37open Extralib
38
39open Setoids
40
41open Monad
42
43open Option
44
45open Lists
46
47open Identifiers
48
49open Integers
50
51open AST
52
53open Division
54
55open Exp
56
57open Arithmetic
58
59open Extranat
60
61open Vector
62
63open Div_and_mod
64
65open Jmeq
66
67open Russell
68
69open List
70
71open Util
72
73open FoldStuff
74
75open BitVector
76
77open Types
78
79open Bool
80
81open Relations
82
83open Nat
84
85open Hints_declaration
86
87open Core_notation
88
89open Pts
90
91open Logic
92
93open Positive
94
95open Z
96
97open BitVectorZ
98
99open Pointers
100
101open ByteValues
102
103open BackEndOps
104
105open Joint
106
107type rtl_seq =
108| Rtl_stack_address of Registers.register * Registers.register
109
110(** val rtl_seq_rect_Type4 :
111    (Registers.register -> Registers.register -> 'a1) -> rtl_seq -> 'a1 **)
112let rec rtl_seq_rect_Type4 h_rtl_stack_address = function
113| Rtl_stack_address (x_17489, x_17488) -> h_rtl_stack_address x_17489 x_17488
114
115(** val rtl_seq_rect_Type5 :
116    (Registers.register -> Registers.register -> 'a1) -> rtl_seq -> 'a1 **)
117let rec rtl_seq_rect_Type5 h_rtl_stack_address = function
118| Rtl_stack_address (x_17493, x_17492) -> h_rtl_stack_address x_17493 x_17492
119
120(** val rtl_seq_rect_Type3 :
121    (Registers.register -> Registers.register -> 'a1) -> rtl_seq -> 'a1 **)
122let rec rtl_seq_rect_Type3 h_rtl_stack_address = function
123| Rtl_stack_address (x_17497, x_17496) -> h_rtl_stack_address x_17497 x_17496
124
125(** val rtl_seq_rect_Type2 :
126    (Registers.register -> Registers.register -> 'a1) -> rtl_seq -> 'a1 **)
127let rec rtl_seq_rect_Type2 h_rtl_stack_address = function
128| Rtl_stack_address (x_17501, x_17500) -> h_rtl_stack_address x_17501 x_17500
129
130(** val rtl_seq_rect_Type1 :
131    (Registers.register -> Registers.register -> 'a1) -> rtl_seq -> 'a1 **)
132let rec rtl_seq_rect_Type1 h_rtl_stack_address = function
133| Rtl_stack_address (x_17505, x_17504) -> h_rtl_stack_address x_17505 x_17504
134
135(** val rtl_seq_rect_Type0 :
136    (Registers.register -> Registers.register -> 'a1) -> rtl_seq -> 'a1 **)
137let rec rtl_seq_rect_Type0 h_rtl_stack_address = function
138| Rtl_stack_address (x_17509, x_17508) -> h_rtl_stack_address x_17509 x_17508
139
140(** val rtl_seq_inv_rect_Type4 :
141    rtl_seq -> (Registers.register -> Registers.register -> __ -> 'a1) -> 'a1 **)
142let rtl_seq_inv_rect_Type4 hterm h1 =
143  let hcut = rtl_seq_rect_Type4 h1 hterm in hcut __
144
145(** val rtl_seq_inv_rect_Type3 :
146    rtl_seq -> (Registers.register -> Registers.register -> __ -> 'a1) -> 'a1 **)
147let rtl_seq_inv_rect_Type3 hterm h1 =
148  let hcut = rtl_seq_rect_Type3 h1 hterm in hcut __
149
150(** val rtl_seq_inv_rect_Type2 :
151    rtl_seq -> (Registers.register -> Registers.register -> __ -> 'a1) -> 'a1 **)
152let rtl_seq_inv_rect_Type2 hterm h1 =
153  let hcut = rtl_seq_rect_Type2 h1 hterm in hcut __
154
155(** val rtl_seq_inv_rect_Type1 :
156    rtl_seq -> (Registers.register -> Registers.register -> __ -> 'a1) -> 'a1 **)
157let rtl_seq_inv_rect_Type1 hterm h1 =
158  let hcut = rtl_seq_rect_Type1 h1 hterm in hcut __
159
160(** val rtl_seq_inv_rect_Type0 :
161    rtl_seq -> (Registers.register -> Registers.register -> __ -> 'a1) -> 'a1 **)
162let rtl_seq_inv_rect_Type0 hterm h1 =
163  let hcut = rtl_seq_rect_Type0 h1 hterm in hcut __
164
165(** val rtl_seq_discr : rtl_seq -> rtl_seq -> __ **)
166let rtl_seq_discr x y =
167  Logic.eq_rect_Type2 x
168    (let Rtl_stack_address (a0, a1) = x in Obj.magic (fun _ dH -> dH __ __))
169    y
170
171(** val rtl_seq_jmdiscr : rtl_seq -> rtl_seq -> __ **)
172let rtl_seq_jmdiscr x y =
173  Logic.eq_rect_Type2 x
174    (let Rtl_stack_address (a0, a1) = x in Obj.magic (fun _ dH -> dH __ __))
175    y
176
177(** val rTL_uns : Joint.unserialized_params **)
178let rTL_uns =
179  { Joint.ext_seq_labels = (fun x -> List.Nil); Joint.has_tailcalls =
180    Bool.False }
181
182(** val rTL : Joint.graph_params **)
183let rTL =
184  rTL_uns
185
186type rtl_program = Joint.joint_program
187
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