[2717] | 1 | open Preamble |
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| 2 | |
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| 3 | open String |
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| 4 | |
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| 5 | open Sets |
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| 6 | |
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| 7 | open Listb |
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| 8 | |
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| 9 | open LabelledObjects |
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| 10 | |
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[2773] | 11 | open BitVectorTrie |
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| 12 | |
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[2717] | 13 | open Graphs |
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| 14 | |
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| 15 | open I8051 |
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| 16 | |
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| 17 | open Order |
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| 18 | |
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| 19 | open Registers |
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| 20 | |
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| 21 | open CostLabel |
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| 22 | |
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| 23 | open Hide |
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| 24 | |
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| 25 | open Proper |
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| 26 | |
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| 27 | open PositiveMap |
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| 28 | |
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| 29 | open Deqsets |
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| 30 | |
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| 31 | open ErrorMessages |
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| 32 | |
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| 33 | open PreIdentifiers |
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| 34 | |
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| 35 | open Errors |
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| 36 | |
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| 37 | open Extralib |
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| 38 | |
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| 39 | open Lists |
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| 40 | |
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| 41 | open Identifiers |
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| 42 | |
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| 43 | open Integers |
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| 44 | |
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| 45 | open AST |
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| 46 | |
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| 47 | open Division |
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| 48 | |
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| 49 | open Exp |
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| 50 | |
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| 51 | open Arithmetic |
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| 52 | |
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[2773] | 53 | open Setoids |
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| 54 | |
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| 55 | open Monad |
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| 56 | |
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| 57 | open Option |
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| 58 | |
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[2717] | 59 | open Extranat |
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| 60 | |
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| 61 | open Vector |
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| 62 | |
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| 63 | open Div_and_mod |
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| 64 | |
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| 65 | open Jmeq |
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| 66 | |
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| 67 | open Russell |
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| 68 | |
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| 69 | open List |
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| 70 | |
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| 71 | open Util |
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| 72 | |
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| 73 | open FoldStuff |
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| 74 | |
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| 75 | open BitVector |
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| 76 | |
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| 77 | open Types |
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| 78 | |
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| 79 | open Bool |
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| 80 | |
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| 81 | open Relations |
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| 82 | |
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| 83 | open Nat |
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| 84 | |
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| 85 | open Hints_declaration |
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| 86 | |
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| 87 | open Core_notation |
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| 88 | |
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| 89 | open Pts |
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| 90 | |
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| 91 | open Logic |
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| 92 | |
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| 93 | open Positive |
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| 94 | |
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| 95 | open Z |
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| 96 | |
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| 97 | open BitVectorZ |
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| 98 | |
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| 99 | open Pointers |
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| 100 | |
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| 101 | open ByteValues |
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| 102 | |
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| 103 | open BackEndOps |
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| 104 | |
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| 105 | open Joint |
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| 106 | |
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| 107 | type registers_move = |
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| 108 | | From_acc of I8051.register * Types.unit0 |
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| 109 | | To_acc of Types.unit0 * I8051.register |
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| 110 | | Int_to_reg of I8051.register * BitVector.byte |
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| 111 | | Int_to_acc of Types.unit0 * BitVector.byte |
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| 112 | |
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| 113 | (** val registers_move_rect_Type4 : |
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| 114 | (I8051.register -> Types.unit0 -> 'a1) -> (Types.unit0 -> I8051.register |
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| 115 | -> 'a1) -> (I8051.register -> BitVector.byte -> 'a1) -> (Types.unit0 -> |
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| 116 | BitVector.byte -> 'a1) -> registers_move -> 'a1 **) |
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| 117 | let rec registers_move_rect_Type4 h_from_acc h_to_acc h_int_to_reg h_int_to_acc = function |
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[2775] | 118 | | From_acc (x_21298, x_21297) -> h_from_acc x_21298 x_21297 |
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| 119 | | To_acc (x_21300, x_21299) -> h_to_acc x_21300 x_21299 |
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| 120 | | Int_to_reg (x_21302, x_21301) -> h_int_to_reg x_21302 x_21301 |
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| 121 | | Int_to_acc (x_21304, x_21303) -> h_int_to_acc x_21304 x_21303 |
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[2717] | 122 | |
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| 123 | (** val registers_move_rect_Type5 : |
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| 124 | (I8051.register -> Types.unit0 -> 'a1) -> (Types.unit0 -> I8051.register |
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| 125 | -> 'a1) -> (I8051.register -> BitVector.byte -> 'a1) -> (Types.unit0 -> |
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| 126 | BitVector.byte -> 'a1) -> registers_move -> 'a1 **) |
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| 127 | let rec registers_move_rect_Type5 h_from_acc h_to_acc h_int_to_reg h_int_to_acc = function |
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[2775] | 128 | | From_acc (x_21311, x_21310) -> h_from_acc x_21311 x_21310 |
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| 129 | | To_acc (x_21313, x_21312) -> h_to_acc x_21313 x_21312 |
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| 130 | | Int_to_reg (x_21315, x_21314) -> h_int_to_reg x_21315 x_21314 |
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| 131 | | Int_to_acc (x_21317, x_21316) -> h_int_to_acc x_21317 x_21316 |
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[2717] | 132 | |
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| 133 | (** val registers_move_rect_Type3 : |
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| 134 | (I8051.register -> Types.unit0 -> 'a1) -> (Types.unit0 -> I8051.register |
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| 135 | -> 'a1) -> (I8051.register -> BitVector.byte -> 'a1) -> (Types.unit0 -> |
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| 136 | BitVector.byte -> 'a1) -> registers_move -> 'a1 **) |
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| 137 | let rec registers_move_rect_Type3 h_from_acc h_to_acc h_int_to_reg h_int_to_acc = function |
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[2775] | 138 | | From_acc (x_21324, x_21323) -> h_from_acc x_21324 x_21323 |
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| 139 | | To_acc (x_21326, x_21325) -> h_to_acc x_21326 x_21325 |
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| 140 | | Int_to_reg (x_21328, x_21327) -> h_int_to_reg x_21328 x_21327 |
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| 141 | | Int_to_acc (x_21330, x_21329) -> h_int_to_acc x_21330 x_21329 |
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[2717] | 142 | |
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| 143 | (** val registers_move_rect_Type2 : |
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| 144 | (I8051.register -> Types.unit0 -> 'a1) -> (Types.unit0 -> I8051.register |
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| 145 | -> 'a1) -> (I8051.register -> BitVector.byte -> 'a1) -> (Types.unit0 -> |
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| 146 | BitVector.byte -> 'a1) -> registers_move -> 'a1 **) |
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| 147 | let rec registers_move_rect_Type2 h_from_acc h_to_acc h_int_to_reg h_int_to_acc = function |
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[2775] | 148 | | From_acc (x_21337, x_21336) -> h_from_acc x_21337 x_21336 |
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| 149 | | To_acc (x_21339, x_21338) -> h_to_acc x_21339 x_21338 |
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| 150 | | Int_to_reg (x_21341, x_21340) -> h_int_to_reg x_21341 x_21340 |
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| 151 | | Int_to_acc (x_21343, x_21342) -> h_int_to_acc x_21343 x_21342 |
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[2717] | 152 | |
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| 153 | (** val registers_move_rect_Type1 : |
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| 154 | (I8051.register -> Types.unit0 -> 'a1) -> (Types.unit0 -> I8051.register |
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| 155 | -> 'a1) -> (I8051.register -> BitVector.byte -> 'a1) -> (Types.unit0 -> |
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| 156 | BitVector.byte -> 'a1) -> registers_move -> 'a1 **) |
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| 157 | let rec registers_move_rect_Type1 h_from_acc h_to_acc h_int_to_reg h_int_to_acc = function |
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[2775] | 158 | | From_acc (x_21350, x_21349) -> h_from_acc x_21350 x_21349 |
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| 159 | | To_acc (x_21352, x_21351) -> h_to_acc x_21352 x_21351 |
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| 160 | | Int_to_reg (x_21354, x_21353) -> h_int_to_reg x_21354 x_21353 |
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| 161 | | Int_to_acc (x_21356, x_21355) -> h_int_to_acc x_21356 x_21355 |
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[2717] | 162 | |
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| 163 | (** val registers_move_rect_Type0 : |
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| 164 | (I8051.register -> Types.unit0 -> 'a1) -> (Types.unit0 -> I8051.register |
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| 165 | -> 'a1) -> (I8051.register -> BitVector.byte -> 'a1) -> (Types.unit0 -> |
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| 166 | BitVector.byte -> 'a1) -> registers_move -> 'a1 **) |
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| 167 | let rec registers_move_rect_Type0 h_from_acc h_to_acc h_int_to_reg h_int_to_acc = function |
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[2775] | 168 | | From_acc (x_21363, x_21362) -> h_from_acc x_21363 x_21362 |
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| 169 | | To_acc (x_21365, x_21364) -> h_to_acc x_21365 x_21364 |
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| 170 | | Int_to_reg (x_21367, x_21366) -> h_int_to_reg x_21367 x_21366 |
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| 171 | | Int_to_acc (x_21369, x_21368) -> h_int_to_acc x_21369 x_21368 |
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[2717] | 172 | |
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| 173 | (** val registers_move_inv_rect_Type4 : |
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| 174 | registers_move -> (I8051.register -> Types.unit0 -> __ -> 'a1) -> |
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| 175 | (Types.unit0 -> I8051.register -> __ -> 'a1) -> (I8051.register -> |
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| 176 | BitVector.byte -> __ -> 'a1) -> (Types.unit0 -> BitVector.byte -> __ -> |
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| 177 | 'a1) -> 'a1 **) |
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| 178 | let registers_move_inv_rect_Type4 hterm h1 h2 h3 h4 = |
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| 179 | let hcut = registers_move_rect_Type4 h1 h2 h3 h4 hterm in hcut __ |
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| 180 | |
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| 181 | (** val registers_move_inv_rect_Type3 : |
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| 182 | registers_move -> (I8051.register -> Types.unit0 -> __ -> 'a1) -> |
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| 183 | (Types.unit0 -> I8051.register -> __ -> 'a1) -> (I8051.register -> |
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| 184 | BitVector.byte -> __ -> 'a1) -> (Types.unit0 -> BitVector.byte -> __ -> |
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| 185 | 'a1) -> 'a1 **) |
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| 186 | let registers_move_inv_rect_Type3 hterm h1 h2 h3 h4 = |
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| 187 | let hcut = registers_move_rect_Type3 h1 h2 h3 h4 hterm in hcut __ |
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| 188 | |
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| 189 | (** val registers_move_inv_rect_Type2 : |
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| 190 | registers_move -> (I8051.register -> Types.unit0 -> __ -> 'a1) -> |
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| 191 | (Types.unit0 -> I8051.register -> __ -> 'a1) -> (I8051.register -> |
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| 192 | BitVector.byte -> __ -> 'a1) -> (Types.unit0 -> BitVector.byte -> __ -> |
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| 193 | 'a1) -> 'a1 **) |
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| 194 | let registers_move_inv_rect_Type2 hterm h1 h2 h3 h4 = |
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| 195 | let hcut = registers_move_rect_Type2 h1 h2 h3 h4 hterm in hcut __ |
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| 196 | |
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| 197 | (** val registers_move_inv_rect_Type1 : |
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| 198 | registers_move -> (I8051.register -> Types.unit0 -> __ -> 'a1) -> |
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| 199 | (Types.unit0 -> I8051.register -> __ -> 'a1) -> (I8051.register -> |
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| 200 | BitVector.byte -> __ -> 'a1) -> (Types.unit0 -> BitVector.byte -> __ -> |
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| 201 | 'a1) -> 'a1 **) |
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| 202 | let registers_move_inv_rect_Type1 hterm h1 h2 h3 h4 = |
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| 203 | let hcut = registers_move_rect_Type1 h1 h2 h3 h4 hterm in hcut __ |
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| 204 | |
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| 205 | (** val registers_move_inv_rect_Type0 : |
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| 206 | registers_move -> (I8051.register -> Types.unit0 -> __ -> 'a1) -> |
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| 207 | (Types.unit0 -> I8051.register -> __ -> 'a1) -> (I8051.register -> |
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| 208 | BitVector.byte -> __ -> 'a1) -> (Types.unit0 -> BitVector.byte -> __ -> |
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| 209 | 'a1) -> 'a1 **) |
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| 210 | let registers_move_inv_rect_Type0 hterm h1 h2 h3 h4 = |
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| 211 | let hcut = registers_move_rect_Type0 h1 h2 h3 h4 hterm in hcut __ |
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| 212 | |
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| 213 | (** val registers_move_discr : registers_move -> registers_move -> __ **) |
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| 214 | let registers_move_discr x y = |
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| 215 | Logic.eq_rect_Type2 x |
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| 216 | (match x with |
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| 217 | | From_acc (a0, a1) -> Obj.magic (fun _ dH -> dH __ __) |
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| 218 | | To_acc (a0, a1) -> Obj.magic (fun _ dH -> dH __ __) |
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| 219 | | Int_to_reg (a0, a1) -> Obj.magic (fun _ dH -> dH __ __) |
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| 220 | | Int_to_acc (a0, a1) -> Obj.magic (fun _ dH -> dH __ __)) y |
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| 221 | |
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| 222 | (** val registers_move_jmdiscr : registers_move -> registers_move -> __ **) |
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| 223 | let registers_move_jmdiscr x y = |
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| 224 | Logic.eq_rect_Type2 x |
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| 225 | (match x with |
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| 226 | | From_acc (a0, a1) -> Obj.magic (fun _ dH -> dH __ __) |
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| 227 | | To_acc (a0, a1) -> Obj.magic (fun _ dH -> dH __ __) |
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| 228 | | Int_to_reg (a0, a1) -> Obj.magic (fun _ dH -> dH __ __) |
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| 229 | | Int_to_acc (a0, a1) -> Obj.magic (fun _ dH -> dH __ __)) y |
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| 230 | |
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| 231 | type ltl_lin_seq = |
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| 232 | | SAVE_CARRY |
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| 233 | | RESTORE_CARRY |
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| 234 | | LOW_ADDRESS of I8051.register * Graphs.label |
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| 235 | | HIGH_ADDRESS of I8051.register * Graphs.label |
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| 236 | |
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| 237 | (** val ltl_lin_seq_rect_Type4 : |
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| 238 | 'a1 -> 'a1 -> (I8051.register -> Graphs.label -> 'a1) -> (I8051.register |
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| 239 | -> Graphs.label -> 'a1) -> ltl_lin_seq -> 'a1 **) |
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| 240 | let rec ltl_lin_seq_rect_Type4 h_SAVE_CARRY h_RESTORE_CARRY h_LOW_ADDRESS h_HIGH_ADDRESS = function |
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| 241 | | SAVE_CARRY -> h_SAVE_CARRY |
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| 242 | | RESTORE_CARRY -> h_RESTORE_CARRY |
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[2775] | 243 | | LOW_ADDRESS (x_21463, x_21462) -> h_LOW_ADDRESS x_21463 x_21462 |
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| 244 | | HIGH_ADDRESS (x_21465, x_21464) -> h_HIGH_ADDRESS x_21465 x_21464 |
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[2717] | 245 | |
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| 246 | (** val ltl_lin_seq_rect_Type5 : |
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| 247 | 'a1 -> 'a1 -> (I8051.register -> Graphs.label -> 'a1) -> (I8051.register |
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| 248 | -> Graphs.label -> 'a1) -> ltl_lin_seq -> 'a1 **) |
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| 249 | let rec ltl_lin_seq_rect_Type5 h_SAVE_CARRY h_RESTORE_CARRY h_LOW_ADDRESS h_HIGH_ADDRESS = function |
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| 250 | | SAVE_CARRY -> h_SAVE_CARRY |
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| 251 | | RESTORE_CARRY -> h_RESTORE_CARRY |
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[2775] | 252 | | LOW_ADDRESS (x_21472, x_21471) -> h_LOW_ADDRESS x_21472 x_21471 |
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| 253 | | HIGH_ADDRESS (x_21474, x_21473) -> h_HIGH_ADDRESS x_21474 x_21473 |
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[2717] | 254 | |
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| 255 | (** val ltl_lin_seq_rect_Type3 : |
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| 256 | 'a1 -> 'a1 -> (I8051.register -> Graphs.label -> 'a1) -> (I8051.register |
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| 257 | -> Graphs.label -> 'a1) -> ltl_lin_seq -> 'a1 **) |
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| 258 | let rec ltl_lin_seq_rect_Type3 h_SAVE_CARRY h_RESTORE_CARRY h_LOW_ADDRESS h_HIGH_ADDRESS = function |
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| 259 | | SAVE_CARRY -> h_SAVE_CARRY |
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| 260 | | RESTORE_CARRY -> h_RESTORE_CARRY |
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[2775] | 261 | | LOW_ADDRESS (x_21481, x_21480) -> h_LOW_ADDRESS x_21481 x_21480 |
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| 262 | | HIGH_ADDRESS (x_21483, x_21482) -> h_HIGH_ADDRESS x_21483 x_21482 |
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[2717] | 263 | |
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| 264 | (** val ltl_lin_seq_rect_Type2 : |
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| 265 | 'a1 -> 'a1 -> (I8051.register -> Graphs.label -> 'a1) -> (I8051.register |
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| 266 | -> Graphs.label -> 'a1) -> ltl_lin_seq -> 'a1 **) |
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| 267 | let rec ltl_lin_seq_rect_Type2 h_SAVE_CARRY h_RESTORE_CARRY h_LOW_ADDRESS h_HIGH_ADDRESS = function |
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| 268 | | SAVE_CARRY -> h_SAVE_CARRY |
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| 269 | | RESTORE_CARRY -> h_RESTORE_CARRY |
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[2775] | 270 | | LOW_ADDRESS (x_21490, x_21489) -> h_LOW_ADDRESS x_21490 x_21489 |
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| 271 | | HIGH_ADDRESS (x_21492, x_21491) -> h_HIGH_ADDRESS x_21492 x_21491 |
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[2717] | 272 | |
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| 273 | (** val ltl_lin_seq_rect_Type1 : |
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| 274 | 'a1 -> 'a1 -> (I8051.register -> Graphs.label -> 'a1) -> (I8051.register |
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| 275 | -> Graphs.label -> 'a1) -> ltl_lin_seq -> 'a1 **) |
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| 276 | let rec ltl_lin_seq_rect_Type1 h_SAVE_CARRY h_RESTORE_CARRY h_LOW_ADDRESS h_HIGH_ADDRESS = function |
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| 277 | | SAVE_CARRY -> h_SAVE_CARRY |
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| 278 | | RESTORE_CARRY -> h_RESTORE_CARRY |
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[2775] | 279 | | LOW_ADDRESS (x_21499, x_21498) -> h_LOW_ADDRESS x_21499 x_21498 |
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| 280 | | HIGH_ADDRESS (x_21501, x_21500) -> h_HIGH_ADDRESS x_21501 x_21500 |
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[2717] | 281 | |
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| 282 | (** val ltl_lin_seq_rect_Type0 : |
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| 283 | 'a1 -> 'a1 -> (I8051.register -> Graphs.label -> 'a1) -> (I8051.register |
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| 284 | -> Graphs.label -> 'a1) -> ltl_lin_seq -> 'a1 **) |
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| 285 | let rec ltl_lin_seq_rect_Type0 h_SAVE_CARRY h_RESTORE_CARRY h_LOW_ADDRESS h_HIGH_ADDRESS = function |
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| 286 | | SAVE_CARRY -> h_SAVE_CARRY |
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| 287 | | RESTORE_CARRY -> h_RESTORE_CARRY |
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[2775] | 288 | | LOW_ADDRESS (x_21508, x_21507) -> h_LOW_ADDRESS x_21508 x_21507 |
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| 289 | | HIGH_ADDRESS (x_21510, x_21509) -> h_HIGH_ADDRESS x_21510 x_21509 |
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[2717] | 290 | |
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| 291 | (** val ltl_lin_seq_inv_rect_Type4 : |
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| 292 | ltl_lin_seq -> (__ -> 'a1) -> (__ -> 'a1) -> (I8051.register -> |
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| 293 | Graphs.label -> __ -> 'a1) -> (I8051.register -> Graphs.label -> __ -> |
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| 294 | 'a1) -> 'a1 **) |
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| 295 | let ltl_lin_seq_inv_rect_Type4 hterm h1 h2 h3 h4 = |
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| 296 | let hcut = ltl_lin_seq_rect_Type4 h1 h2 h3 h4 hterm in hcut __ |
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| 297 | |
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| 298 | (** val ltl_lin_seq_inv_rect_Type3 : |
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| 299 | ltl_lin_seq -> (__ -> 'a1) -> (__ -> 'a1) -> (I8051.register -> |
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| 300 | Graphs.label -> __ -> 'a1) -> (I8051.register -> Graphs.label -> __ -> |
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| 301 | 'a1) -> 'a1 **) |
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| 302 | let ltl_lin_seq_inv_rect_Type3 hterm h1 h2 h3 h4 = |
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| 303 | let hcut = ltl_lin_seq_rect_Type3 h1 h2 h3 h4 hterm in hcut __ |
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| 304 | |
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| 305 | (** val ltl_lin_seq_inv_rect_Type2 : |
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| 306 | ltl_lin_seq -> (__ -> 'a1) -> (__ -> 'a1) -> (I8051.register -> |
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| 307 | Graphs.label -> __ -> 'a1) -> (I8051.register -> Graphs.label -> __ -> |
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| 308 | 'a1) -> 'a1 **) |
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| 309 | let ltl_lin_seq_inv_rect_Type2 hterm h1 h2 h3 h4 = |
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| 310 | let hcut = ltl_lin_seq_rect_Type2 h1 h2 h3 h4 hterm in hcut __ |
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| 311 | |
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| 312 | (** val ltl_lin_seq_inv_rect_Type1 : |
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| 313 | ltl_lin_seq -> (__ -> 'a1) -> (__ -> 'a1) -> (I8051.register -> |
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| 314 | Graphs.label -> __ -> 'a1) -> (I8051.register -> Graphs.label -> __ -> |
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| 315 | 'a1) -> 'a1 **) |
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| 316 | let ltl_lin_seq_inv_rect_Type1 hterm h1 h2 h3 h4 = |
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| 317 | let hcut = ltl_lin_seq_rect_Type1 h1 h2 h3 h4 hterm in hcut __ |
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| 318 | |
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| 319 | (** val ltl_lin_seq_inv_rect_Type0 : |
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| 320 | ltl_lin_seq -> (__ -> 'a1) -> (__ -> 'a1) -> (I8051.register -> |
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| 321 | Graphs.label -> __ -> 'a1) -> (I8051.register -> Graphs.label -> __ -> |
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| 322 | 'a1) -> 'a1 **) |
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| 323 | let ltl_lin_seq_inv_rect_Type0 hterm h1 h2 h3 h4 = |
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| 324 | let hcut = ltl_lin_seq_rect_Type0 h1 h2 h3 h4 hterm in hcut __ |
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| 325 | |
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| 326 | (** val ltl_lin_seq_discr : ltl_lin_seq -> ltl_lin_seq -> __ **) |
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| 327 | let ltl_lin_seq_discr x y = |
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| 328 | Logic.eq_rect_Type2 x |
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| 329 | (match x with |
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| 330 | | SAVE_CARRY -> Obj.magic (fun _ dH -> dH) |
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| 331 | | RESTORE_CARRY -> Obj.magic (fun _ dH -> dH) |
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| 332 | | LOW_ADDRESS (a0, a1) -> Obj.magic (fun _ dH -> dH __ __) |
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| 333 | | HIGH_ADDRESS (a0, a1) -> Obj.magic (fun _ dH -> dH __ __)) y |
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| 334 | |
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| 335 | (** val ltl_lin_seq_jmdiscr : ltl_lin_seq -> ltl_lin_seq -> __ **) |
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| 336 | let ltl_lin_seq_jmdiscr x y = |
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| 337 | Logic.eq_rect_Type2 x |
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| 338 | (match x with |
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| 339 | | SAVE_CARRY -> Obj.magic (fun _ dH -> dH) |
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| 340 | | RESTORE_CARRY -> Obj.magic (fun _ dH -> dH) |
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| 341 | | LOW_ADDRESS (a0, a1) -> Obj.magic (fun _ dH -> dH __ __) |
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| 342 | | HIGH_ADDRESS (a0, a1) -> Obj.magic (fun _ dH -> dH __ __)) y |
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| 343 | |
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| 344 | (** val ltl_lin_seq_labels : ltl_lin_seq -> Graphs.label List.list **) |
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| 345 | let ltl_lin_seq_labels = function |
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| 346 | | SAVE_CARRY -> List.Nil |
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| 347 | | RESTORE_CARRY -> List.Nil |
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| 348 | | LOW_ADDRESS (x, lbl) -> List.Cons (lbl, List.Nil) |
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| 349 | | HIGH_ADDRESS (x, lbl) -> List.Cons (lbl, List.Nil) |
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| 350 | |
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| 351 | (** val lTL_LIN : Joint.unserialized_params **) |
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| 352 | let lTL_LIN = |
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| 353 | { Joint.ext_seq_labels = (Obj.magic ltl_lin_seq_labels); |
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| 354 | Joint.has_tailcalls = Bool.False } |
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| 355 | |
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