source: Deliverables/D4.1/test.ml @ 144

Last change on this file since 144 was 142, checked in by sacerdot, 9 years ago

Rough implementation of direct (i.e. no BIT) SFR access.
Note: I/O is not handled properly. Thus the current implementation only
makes sense for real registers like SP, PSW, etc.

File size: 442 bytes
Line 
1let hex = IntelHex.intel_hex_of_file Sys.argv.(1) in
2let mem = IntelHex.process_intel_hex hex in
3let status = ASMInterpret.load_mem mem ASMInterpret.initialize in
4let observe status =
5 let pc = status.ASMInterpret.pc in
6 let instr,_,_ = ASMInterpret.fetch status.ASMInterpret.code_memory pc in
7  prerr_string (BitVectors.hex_string_of_vect pc) ;
8  prerr_endline (": " ^ Pretty.pp_instruction instr)
9in
10 ASMInterpret.execute observe status
11;;
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