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1\documentclass[11pt, epsf, a4wide]{article}
2
3\usepackage{../../style/cerco}
4
5\usepackage{amsfonts}
6\usepackage{amsmath}
7\usepackage{amssymb} 
8\usepackage[english]{babel}
9\usepackage{graphicx}
10\usepackage[utf8x]{inputenc}
11\usepackage{listings}
12\usepackage{stmaryrd}
13\usepackage{url}
14
15\title{
16INFORMATION AND COMMUNICATION TECHNOLOGIES\\
17(ICT)\\
18PROGRAMME\\
19\vspace*{1cm}Project FP7-ICT-2009-C-243881 \cerco{}}
20
21\lstdefinelanguage{matita-ocaml}
22  {keywords={ndefinition,ncoercion,nlemma,ntheorem,nremark,ninductive,nrecord,nqed,nlet,let,in,rec,match,return,with,Type},
23   morekeywords={[2]nwhd,nnormalize,nelim,ncases,ndestruct},
24   morekeywords={[3]type,of},
25   mathescape=true,
26  }
27
28\lstset{language=matita-ocaml,basicstyle=\small\tt,columns=flexible,breaklines=false,
29        keywordstyle=\color{red}\bfseries,
30        keywordstyle=[2]\color{blue},
31        keywordstyle=[3]\color{blue}\bfseries,
32        commentstyle=\color{green},
33        stringstyle=\color{blue},
34        showspaces=false,showstringspaces=false}
35
36\lstset{extendedchars=false}
37\lstset{inputencoding=utf8x}
38\DeclareUnicodeCharacter{8797}{:=}
39\DeclareUnicodeCharacter{10746}{++}
40\DeclareUnicodeCharacter{9001}{\ensuremath{\langle}}
41\DeclareUnicodeCharacter{9002}{\ensuremath{\rangle}}
42
43\date{}
44\author{}
45
46\begin{document}
47
48\thispagestyle{empty}
49
50\vspace*{-1cm}
51\begin{center}
52\includegraphics[width=0.6\textwidth]{../../style/cerco_logo.png}
53\end{center}
54
55\begin{minipage}{\textwidth}
56\maketitle
57\end{minipage}
58
59\vspace*{0.5cm}
60\begin{center}
61\begin{LARGE}
62\textbf{
63Report n. D4.1\\
64Verified Compiler---Back End}
65\end{LARGE} 
66\end{center}
67
68\vspace*{2cm}
69\begin{center}
70\begin{large}
71Version 1.0
72\end{large}
73\end{center}
74
75\vspace*{0.5cm}
76\begin{center}
77\begin{large}
78Main Authors:\\
79Dominic P. Mulligan and Claudio Sacerdoti Coen
80\end{large}
81\end{center}
82
83\vspace*{\fill}
84
85\noindent
86Project Acronym: \cerco{}\\
87Project full title: Certified Complexity\\
88Proposal/Contract no.: FP7-ICT-2009-C-243881 \cerco{}\\
89
90\clearpage
91\pagestyle{myheadings}
92\markright{\cerco{}, FP7-ICT-2009-C-243881}
93
94\newpage
95
96\vspace*{7cm}
97\paragraph{Abstract}
98We discuss the implementation of a prototype O'Caml emulator for the Intel 8051/8052 eight bit processor, and its subsequent formalisation in the dependently typed proof assistant Matita.
99In particular, we focus on the decisions made during the design of both emulators, and how the design of the O'Caml emulator had to be modified in order to fit into the more stringent type system of Matita.
100\newpage
101
102\tableofcontents
103
104\newpage
105
106\section{Task}
107\label{sect.task}
108
109The Grant Agreement states the D4.1/D4.2 deliverables consist of the following tasks:
110
111\begin{quotation}
112\textbf{Executable Formal Semantics of Machine Code}: Formal definition of the semantics of the target language.
113The semantics will be given in a functional (and hence executable) form, useful for testing, validation and project assessment.
114\end{quotation}
115
116\begin{quotation}
117\textbf{CIC encoding: Back-end}: Functional Specification in the internal language of the Proof Assistant (the Calculus of Inductive Construction) of the back end of the compiler.
118This unit is meant to be composable with the front-end of deliverable D3.2, to obtain a full working compiler for Milestone M2.
119A first validation of the design principles and implementation choices for the Untrusted Cost-annotating OCaml Compiler D2.2 is achieved and reported in the deliverable, possibly triggering updates of the Untrusted Cost-annotating OCaml Compiler sources.
120\end{quotation}
121We now report on our implementation of these deliverables.
122
123\section{A brief overview of the target processor}
124\label{sect.brief.overview.target.processor}
125
126The MCS-51 is an eight bit microprocessor introduced by Intel in the late 1970s.
127Commonly called the 8051, in the three decades since its introduction the processor has become a highly popular target for embedded systems engineers.
128Further, the processor and its immediate successor, the 8052, is still manufactured by a host of semiconductor suppliers---many of them European---including Atmel, Siemens Semiconductor, NXP (formerly Phillips Semiconductor), Texas Instruments, and Maxim (formerly Dallas Semiconductor).
129
130The 8051 is a well documented processor, and has the additional support of numerous open source and commercial tools, such as compilers for high-level languages and emulators.
131For instance, the open source Small Device C Compiler (SDCC) recognises a dialect of C, and other compilers targeting the 8051 for BASIC, Forth and Modula-2 are also extant.
132An open source emulator for the processor, MCU8051 IDE, is also available.
133
134The 8051 has a relatively straightforward architecture, unencumbered by advanced features of modern processors, making it an ideal target for formalisation.
135A high-level overview of the processor's memory layout is provided in Figure~\ref{fig.memory.layout}.
136
137Processor RAM is divided into numerous segments, with the most prominent division being between internal and (optional) external memory.
138Internal memory, commonly provided on the die itself with fast access, is further divided into 128 bytes of internal RAM and numerous Special Function Registers (SFRs) which control the operation of the processor.
139Internal RAM (IRAM) is further divided into a eight general purpose bit-addressable registers (R0--R7).
140These sit in the first eight bytes of IRAM, though can be programmatically `shifted up' as needed.
141Bit memory, followed by a small amount of stack space resides in the memory space immediately after the register banks.
142What remains of the IRAM may be treated as general purpose memory.
143A schematic view of IRAM layout is provided in Figure~\ref{fig.iram.layout}.
144
145External RAM (XRAM), limited to 64 kilobytes, is optional, and may be provided on or off chip, depending on the manufacturer.
146XRAM is accessed using a dedicated instruction.
147External code memory (XCODE) is often stored in the form of an EPROM, and limited to 64 kilobytes in size.
148However, depending on the particular manufacturer and processor model, a dedicated on-die read-only memory area for program code (ICODE) may also be supplied.
149
150Memory may be addressed in numerous ways: immediate, direct, indirect, external direct and code indirect.
151As the latter two addressing modes hint, there are some restrictions enforced by the 8051 and its derivatives on which addressing modes may be used with specific types of memory.
152For instance, the 128 bytes of extra internal RAM that the 8052 features cannot be addressed using indirect addressing; rather, external (in)direct addressing must be used.
153
154The 8051 series possesses an eight bit Arithmetic and Logic Unit (ALU), with a wide variety of instructions for performing arithmetic and logical operations on bits and integers.
155Further, the processor possesses two eight bit general purpose accumulators, A and B.
156
157Communication with the device is facilitated by an onboard UART serial port, and associated serial controller, which can operate in numerous modes.
158Serial baud rate is determined by one of two sixteen bit timers included with the 8051, which can be set to multiple modes of operation.
159(The 8052 provides an additional sixteen bit timer.)
160As an additional method of communication, the 8051 also provides a four byte bit-addressable input-output port.
161
162The programmer may take advantage of the interrupt mechanism that the processor provides.
163This is especially useful when dealing with input or output involving the serial device, as an interrupt can be set when a whole character is sent or received via the serial port.
164
165Interrupts immediately halt the flow of execution of the processor, and cause the program counter to jump to a fixed address, where the requisite interrupt handler is stored.
166However, interrupts may be set to one of two priorities: low and high.
167The interrupt handler of an interrupt with high priority is executed ahead of the interrupt handler of an interrupt of lower priority, interrupting a currently executing handler of lower priority, if necessary.
168
169The 8051 has interrupts disabled by default.
170The programmer is free to handle serial input and output manually, by poking serial flags in the SFRs.
171Similarly, `exceptional circumstances' that would otherwise trigger an interrupt on more modern processors, for example, division by zero, are also signalled by setting flags.
172
173\begin{figure}[t]
174\begin{center}
175\includegraphics[scale=0.5]{memorylayout.png}
176\end{center}
177\caption{High level overview of the 8051 memory layout}
178\label{fig.memory.layout}
179\end{figure}
180
181\begin{figure}[t]
182\begin{center}
183\includegraphics[scale=0.5]{iramlayout.png}
184\end{center}
185\caption{Schematic view of 8051 IRAM layout}
186\label{fig.iram.layout}
187\end{figure}
188
189\section{The emulator in O'Caml}
190\label{sect.emulator.in.ocaml}
191
192We discuss decisions made during the design of the prototype O'Caml emulator.
193
194\subsection{Lack of orthogonality in instruction set}
195\label{subsect.lack.orthogonality.instruction.set}
196
197The instruction set of 8051 assembly is highly irregular.
198For instance, consider the MOV instruction, which implements a data transfer between two memory locations, which takes eighteen possible combinations of addressing modes.
199
200We handle this problem by introducing `unions' of types, using O'Caml's polymorphic variants feature:
201\begin{quote}
202\begin{lstlisting}
203type ('a, 'b) union2 = [ `U1 of 'a | `U2 of 'b ]
204\end{lstlisting}
205\end{quote}
206(We also introduce \texttt{union3} and \texttt{union6}, which suffice for our purposes.)
207
208Using these union types, we can rationalise the inductive type encoding the assembly instruction set.
209For instance:
210\begin{quote}
211\begin{lstlisting}
212type 'addr preinstruction =
213...
214  | `XRL of (acc * [ data | reg | direct | indirect ],
215             direct * [ acc | data ]) union2
216...
217\end{lstlisting}
218\end{quote}
219That is, the \texttt{XRL} instruction\footnote{Exclusive disjunction.} take either the accumulator A as its first argument, followed by data with one of data, register, direct or indirect addressing modes, or takes data with a direct addressing mode as its first argument, with either the accumulator A or data with the data addressing mode as its second argument.
220
221Further, all functions that must pattern match against the \texttt{(pre)instruction} inductive type are also simplified using this technique.
222Using O'Caml's ability to perform `deep pattern' matches, we may pattern match against \texttt{`XRL(`U1(arg1, arg2))} and have the guarantee that \texttt{arg1} takes the form \texttt{`ACC\_A}.
223
224\subsection{Pseudo-instructions and labels}
225\label{subsect.pseudo-instructions.labels}
226
227Per the description of Deliverable D4.1 in the Grant Agreement above, the 8051 emulator must eventually interface with the C compiler frontend of Deliverable D3.2, produced in Paris.
228After consultation, it was found that the design of the compiler frontend could be simplified considerably with the introduction of \emph{pseudoinstructions} and labels.
229
230We introduce three new pseudoinstructions---\texttt{Jump}, \texttt{Call}, and \texttt{Mov}---corresponding to unconditional jumps, procedure calls and data transfers respectively.
231We also `promote' all unlabeled conditional jumps in 8051 assembly to labeled pseudojumps; one can now jump to a label conditionally, as opposed to jumping to a fixed relative offset.
232Further, we introduce labels for jumping to, and cost annotations, used by the Paris team.
233
234The three new pseudoinstructions, along with the promoted conditional jumps, allow the Paris team to abstract away from the differences between different types of unconditional jump (the 8051 has three different sorts, depending on the length of the jump), as well as abstract away the differences between memory transfers and calls.
235However, the emulator must perform an expansion stage, during which pseudoinstructions are translated to `real' 8051 assembly instructions.
236
237The introduction of labeled conditional jumps slightly complicates our type of abstract syntax for 8051 assembly.
238We define an inductive type representing conditional jumps in 8051 assembly code, parameterised by a type representing relative offsets:s
239\begin{quote}
240\begin{lstlisting}
241type 'addr jump =
242  [ `JC of 'addr
243  | `JNC of 'addr
244...
245\end{lstlisting}
246\end{quote}
247An inductive type of preinstructions is defined, which is also parameterised by a type representing relative offsets in assembly code, and incorporates the inductive type of conditional jumps:
248\begin{quote}
249\begin{lstlisting}
250type 'addr preinstruction =
251  [ `ADD of acc * [ reg | direct | indirect | data ]
252...
253  | 'addr jump
254...
255\end{lstlisting}
256\end{quote}
257A type representing instructions is defined, choosing a concrete type for relative offsets:
258\begin{quote}
259\begin{lstlisting}
260type instruction = rel preinstruction
261\end{lstlisting}
262\end{quote}
263Here, \texttt{rel} is a type which `wraps up' a byte.
264Finally, this type of instructions is incorporated into a type of labelled instructions:
265\begin{quote}
266\begin{lstlisting}
267type labelled_instruction =
268  [ instruction
269  | `Cost of string
270  | `Label of string
271  | `Jmp of string
272  | `Call of string
273  | `Mov of dptr * string
274  | `WithLabel of [`Label of string] jump
275]
276\end{lstlisting}
277\end{quote}
278Throughout, we make heavy use of polymorphic variants to deal with issues relating to subtyping.
279
280As mentioned, the emulator must now handle an additional expansion stage, removing pseudoinstructions in favour of real, 8051 assembly instructions.
281This is relatively straightforward, and is done in two stages.
282
283The first stage consists of iterating over an assembly program, building a dictionary of all labels and their position in the program.
284The second stage consists of iterating over the same program and replacing all pseudojumps (both conditional and unconditional) with an 8051 jump to the requisite computed offset.
285One subtletly persists, however.
286
287The 8051 has three different types of unconditional jump, depending on the length of the jump to be used: \texttt{AJMP}, \texttt{JMP} and \texttt{LJMP}.
288The instructions \texttt{AJMP} and \texttt{JMP} are short jumps, whereas \texttt{LJMP} is a long jump, capable of reaching anywhere in the program.
289At the moment, the second pass of the expansion stage replaces all unconditional pseudojumps with a \texttt{LJMP} for simplicity.
290We do, however, plan to improve this process for efficiency reasons, expanding to shorter jumps where feasible.
291
292\subsection{Validation}
293\label{subsect.validation}
294
295In validating the design and implementation of the O'Caml emulator we used two tactics:
296\begin{enumerate}
297\item
298Use of multiple manufacturer's data sheets (both the Siemens Semiconductor and Phillips Semiconductor specifications for the 8051, as well as online sources such as the Keil website).
299We found typographic errors in manufacturer's data sheets which were resolved by consulting an alternative sheet.
300\item
301Use of reference compilers and emulators.
302The operation of the emulator was manually tested by reference to \textsc{mcu 8051 ide}, an emulator for the 8051 series processor.
303A number of small C programs were compiled in SDCC\footnote{See the \texttt{GCC} directory for a selection of them.}.
304The resulting IHX files were disassembled by \textsc{mcu 8051 ide}.
305(IHX files are a standard format for transferring compiled assembly code onto an 8051 series processor, produced by SDCC and all other compilers that target that 8051.)
306The status changes in both emulators were then compared.
307
308For further validation, the output of the compiled C programs from SDCC was compared with the output of the same programs in GCC, in order to pre-empt the introduction of bugs in the emulator inherited from a faulty C compiler.
309\end{enumerate}
310
311As a further check, the design and operation of the emulator was compared with the textual description of online tutorials on 8051 programming, such as those found at \url{http://www.8052.com}.
312
313\section{The emulator in Matita}
314\label{sect.emulator.in.matita}
315
316The O'Caml emulator served as a testbed and prototype for an emulator written in the internal language of the Matita proof assistant.
317We describe our work porting the emulator to Matita, especially where the design of the Matita emulator differs from that of the O'Caml version.
318
319\subsection{What we do not implement}
320\label{subsect.what.we.do.not.implement}
321
322Our O'Caml 8051 emulator provides functions for reading and parsing Intel IHX format files.
323We do not implement these functions in the Matita emulator, as Matita provides no means of input or output.
324
325\subsection{Auxilliary data structures and libraries}
326\label{subsect.auxilliary.data.structures.and.libraries}
327
328A small library of data structures was written, along with basic functions operating over them.
329Implemented data structures include: Booleans, option types, lists, Cartesian products, Natural numbers, fixed-length vectors, and sparse tries.
330
331Our type of vectors, in particular, makes heavy use of dependent types.
332Probing vectors is `type safe' for instance: we cannot index into a vector beyond the vector's length.
333
334We represent bits as Boolean values.
335Nibbles, bytes, words, and so on, are represented as fixed length (bit)vectors of the requisite length.
336
337\subsection{The emulator state}
338\label{subsect.emulator.state}
339
340We represent all processor memory in the Matita emulator as a sparse (bitvector)trie:
341
342\begin{quote}
343\begin{lstlisting}
344ninductive BitVectorTrie (A: Type[0]): Nat $\rightarrow$ Type[0] ≝
345  Leaf: A $\rightarrow$ BitVectorTrie A Z
346| Node: ∀n: Nat. BitVectorTrie A n $\rightarrow$ BitVectorTrie A n $\rightarrow$ BitVectorTrie A (S n)
347| Stub: ∀n: Nat. BitVectorTrie A n.
348\end{lstlisting}
349\end{quote}
350
351Nodes are addressed by a bitvector index, representing a path through the tree.
352At any point in the tree, a \texttt{Stub} may be inserted, representing a `hole' in the tree.
353All functions operating on tries use dependent types to enforce the invariant that the height of the tree and the length of the bitvector representing a path through the tree are the same.
354
355We probe a trie with the \texttt{lookup} function.
356This takes an additional argument representing the value to be returned should a stub, representing uninitialised data, be encountered during traversal.
357
358Like the O'Caml emulator, we use a record to represent processor state:
359
360\begin{quote}
361\begin{lstlisting}
362nrecord Status: Type[0] ≝
363{
364  code_memory: BitVectorTrie Byte sixteen;
365  low_internal_ram: BitVectorTrie Byte seven;
366  high_internal_ram: BitVectorTrie Byte seven;
367  external_ram: BitVectorTrie Byte sixteen;
368 
369  program_counter: Word;
370 
371  special_function_registers_8051: Vector Byte nineteen;
372  special_function_registers_8052: Vector Byte five;
373 
374  ...
375}.
376\end{lstlisting}
377\end{quote}
378
379However, we `squash' the \texttt{Status} record in the Matita emulator by grouping all 8051 SFRs (respectively, 8052 SFRs) into a single vector of bytes, as opposed to representing them as explicit fields in the record itself.
380We then provide functions that index into the respective vector to `get' and `set' the respective SFRs.
381This is due to record typechecking in Matita being slow for large records.
382
383\subsection{Dealing with partiality}
384\label{subsect.dealing.with.partiality}
385
386The O'Caml 8051 emulator makes use of a number of partial functions.
387These functions either \texttt{assert false}\footnote{O'Caml idiom: immediately halts execution of the running program.} or do not perform a comprehensive pattern analysis over their inputs.
388There are a number of possible reasons for this:
389\begin{enumerate}
390\item
391\textbf{Incomplete pattern analyses} are used where we are confident that the particular pattern match in question should never occur, for instance if the calling function performs a test beforehand, or where the emulator should fail anyway if a particular unchecked pattern is used as input.
392An example of a function which exhibits the latter behaviour is \texttt{set\_arg\_16} from \texttt{ASMInterpret.ml}, which fails with a pattern match exception if called on an input representing an eight bit argument.
393\item
394\textbf{Assert false} may be called if the emulator finds itself in an `impossible situation', such as encountering an empty list where a list containing one element is expected.
395In this respect, we used \texttt{assert false} in a similar way to the previously described use of incomplete pattern analysis.
396\item
397\textbf{Assert false} may be called is some feature of the physical 8051 processor is not implemented in the O'Caml emulator and an executing program is attempting to use it.
398\end{enumerate}
399
400The three manifestations of partiality above can be split into two types: partiality that manifests itself due to O'Caml's type system not being strong enough to rule the cause out, and partiality that signals a `real' crash in the processor due to the user attempting to use an unimplemented feature.
401Items 1 and 2 belong to the former class, Item 3 to the latter.
402
403Clearly Items 1 and 2 above must be addressed in the Matita formalisation.
404Item 2 is solved through extensive use of dependent types.
405Indexing into lists and vectors, for instance, is always `type safe', as we provide probing functions with strong dependent types.
406
407Item 1 is perhaps the most problematic of the three problems, as we either have to provide an exhaustive case analysis, use pattern wildcards, or find a clever way of encoding the possible patterns that are expected as input in the type of a function.
408We employ a technique that implements the latter idea.
409This is discussed in Subsection~\ref{subsect.addressing.modes.use.of.dependent.types}.
410
411To solve Item 3 above in the Matita formalisation of the emulator, we introduce an axiom \texttt{not\_implemented} of type \texttt{False}.
412When the emulator attempts to use an unimplemented feature, we introduce a metavariable, corresponding to an open proof obligation.
413These obligations are closed by performing a case analysis over \texttt{not\_implemented}.
414
415\subsection{Addressing modes: use of dependent types}
416\label{subsect.addressing.modes.use.of.dependent.types}
417
418We provide an inductive data type representing all possible addressing modes of 8051 assembly.
419This is the type that functions will pattern match against.
420
421\begin{quote}
422\begin{lstlisting}
423ninductive addressing_mode: Type[0] ≝
424  DIRECT: Byte $\rightarrow$ addressing_mode
425| INDIRECT: Bit $\rightarrow$ addressing_mode
426...
427\end{lstlisting}
428\end{quote}
429However, we also wish to express in the type of our functions the \emph{impossibility} of pattern matching against certain constructors.
430In order to do this, we introduce an inductive type of addressing mode `tags'.
431The constructors of \texttt{addressing\_mode\_tag} are in one-one correspondence with the constructors of \texttt{addressing\_mode}:
432\begin{quote}
433\begin{lstlisting}
434ninductive addressing_mode_tag : Type[0] ≝
435  direct: addressing_mode_tag
436| indirect: addressing_mode_tag
437...
438\end{lstlisting}
439\end{quote}
440We then provide a function that checks whether an \texttt{addressing\_mode} is `morally' an \texttt{addressing\_mode\_tag}, as follows:
441\begin{quote}
442\begin{lstlisting}
443nlet rec is_a (d:addressing_mode_tag) (A:addressing_mode) on d ≝
444  match d with
445   [ direct $\Rightarrow$ match A with [ DIRECT _ $\Rightarrow$ true | _ $\Rightarrow$ false ]
446   | indirect $\Rightarrow$ match A with [ INDIRECT _ $\Rightarrow$ true | _ $\Rightarrow$ false ]
447...
448\end{lstlisting}
449\end{quote}
450We also extend this check to vectors of \texttt{addressing\_mode\_tag}'s in the obvious manner:
451\begin{quote}
452\begin{lstlisting}
453nlet rec is_in (n: Nat) (l: Vector addressing_mode_tag n) (A:addressing_mode) on l ≝
454 match l return $\lambda$m.$\lambda$_ :Vector addressing_mode_tag m.Bool with
455  [ VEmpty $\Rightarrow$ false
456  | VCons m he (tl: Vector addressing_mode_tag m) $\Rightarrow$
457     is_a he A $\vee$ is_in ? tl A ].
458\end{lstlisting}
459\end{quote}
460Here \texttt{VEmpty} and \texttt{VCons} are the two constructors of the \texttt{Vector} data type, and $\mathtt{\vee}$ is inclusive disjunction on Booleans.
461\begin{quote}
462\begin{lstlisting}
463nrecord subaddressing_mode (n: Nat) (l: Vector addressing_mode_tag (S n)) : Type[0] ≝
464{
465  subaddressing_modeel :> addressing_mode;
466  subaddressing_modein: bool_to_Prop (is_in ? l subaddressing_modeel)
467}.
468\end{lstlisting}
469\end{quote}
470We can now provide an inductive type of preinstructions with precise typings:
471\begin{quote}
472\begin{lstlisting}
473ninductive preinstruction (A: Type[0]): Type[0] ≝
474   ADD: $\llbracket$ acc_a $\rrbracket$ $\rightarrow$ $\llbracket$ register; direct; indirect; data $\rrbracket$ $\rightarrow$ preinstruction A
475 | ADDC: $\llbracket$ acc_a $\rrbracket$ $\rightarrow$ $\llbracket$ register; direct; indirect; data $\rrbracket$ $\rightarrow$ preinstruction A
476...
477\end{lstlisting}
478\end{quote}
479Here $\llbracket - \rrbracket$ is syntax denoting a vector.
480We see that the constructor \texttt{ADD} expects two parameters, the first being the accumulator A (\texttt{acc\_a}), and the second being one of a register, direct, indirect or data addressing mode.
481
482The final, missing component is a pair of type coercions from \texttt{addressing\_mode} to \texttt{subaddressing\_mode} and from \texttt{subaddressing\_mode} to \texttt{Type$\lbrack0\rbrack$}, respectively.
483The previous machinery allows us to state in the type of a function what addressing modes that function expects.
484For instance, consider \texttt{set\_arg\_16}, which expects only a \texttt{DPTR}:
485\begin{quote}
486\begin{lstlisting}
487ndefinition set_arg_16: Status $\rightarrow$ Word $\rightarrow$ $\llbracket$ dptr $\rrbracket$ $\rightarrow$ Status ≝
488  $\lambda$s, v, a.
489   match a return $\lambda$x. bool_to_Prop (is_in ? $\llbracket$ dptr $\rrbracket$ x) $\rightarrow$ ? with
490     [ DPTR $\Rightarrow$ $\lambda$_: True.
491       let 〈 bu, bl 〉 := split $\ldots$ eight eight v in
492       let status := set_8051_sfr s SFR_DPH bu in
493       let status := set_8051_sfr status SFR_DPL bl in
494         status
495     | _ $\Rightarrow$ $\lambda$_: False.
496       match K in False with
497       [
498       ]
499     ] (subaddressing_modein $\ldots$ a).
500\end{lstlisting}
501\end{quote}
502All other cases are discharged by the catch-all at the bottom of the match expression.
503Attempting to match against another addressing mode not indicated in the type (for example, \texttt{REGISTER}) will produce a type-error.
504
505\subsection{Validation}
506\label{subsect.matita.validation}
507
508The Matita emulator is executable from within Matita (naturally, the speed of execution is only a fraction of the speed of the O'Caml emulator).
509
510\subsection{Future work}
511\label{subsect.future.work}
512
513The Matita emulator is written in the latest public Subversion repository version of Matita.
514However, this version is in an intermediate stage between the `old' Matita, and a new, more streamlined version of the proof assistant.
515As a result, some key features of the system are currently missing in the repository version of Matita, most notably program code extraction from a Matita theory file.
516
517The new, rewritten version of Matita reinstates the missing functionality.
518We plan, once the newer version is released, to port the Matita emulator to the most up-to-date version of the proof assistant.
519This will allow us to extract a verified O'Caml emulator from the Matita theory files.
520
521\newpage
522
523\section{Listing of O'Caml files}
524\label{sect.listing.ocaml.files}
525
526\newpage
527
528\section{Listing of Matita files}
529\label{sect.listing.matita.files}
530
531\end{document}
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