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1\documentclass[serif]{beamer}
2
3\author{Dominic Mulligan \and \alert{Claudio Sacerdoti Coen}}
4\title{A brief introduction to the 8051 processor \\\vspace{\baselineskip} \small{CerCo project meeting, Paris, September 2010}}
5\date{\today}
6
7\begin{document}
8
9\begin{frame}
10\maketitle
11\end{frame}
12
13\begin{frame}
14\frametitle{Vital statistics I}
15The 8051 (a.k.a. 8052, 80C51, MCS51) is:
16\begin{itemize}
17\item
188 bit microprocessor introduced in 1980 by Intel, very popular, still manufactured by a host of companies (many European!)
19\item
20Three different types of memory: on-chip memory (code, RAM, or other) that physically resides on processor die, external code memory and external RAM
21\item
22128 bytes of internal RAM, subdivided into different sections (the register banks, bit memory, stack space and general RAM)
23\item
24At most, stack space is 80 bytes, but often less (very small!)\\
25But ways of having the stack in external RAM\ldots
26\end{itemize}
27\end{frame}
28
29\begin{frame}
30\frametitle{Vital statistics II}
31\begin{itemize}
32\item
33Two timers with multiple modes of operation (8052 adds a third timer with more modes)
34\item
35Serial (UART) port and 32 input/output lines
36\item Interrupts only for I/O, could be entirely replaced by polling
37\item Two levels of priority for interrupts (cfr. four register banks)
38\item All instructions take a fixed, known-in-advance number of clock-cycles
39\end{itemize}
40\end{frame}
41
42\begin{frame}
43\frametitle{Memory model}
44Several distinct (not disjoint) memory areas and addressing mode (hence
45pointer type):
46\begin{itemize}
47 \item Code memory; ad-hoc access, read-only, may be partially on-die
48 \item Low internal RAM (128 bytes); direct + indirect address
49 \item High internal RAM (128 bytes); indirect access only
50 \item External RAM; ad-hoc access only via DPTR (16 bits SFR)
51 \item Low External RAM; ad-hoc indirect access, overlaps with External RAM
52 \item Memory-mapped I/O + Special Function Registers (SFRs); direct access only
53 \item Bit memory (256 addresses); ad-hoc access, 1/2 overlaps with
54       Low Internal RAM, 1/2 overlaps with Special Function Registers
55 \item Four register banks, 8 registers each; direct + indirect + ad-hoc
56       access, fully overlaps with Low Internal RAM
57\end{itemize}
58\end{frame}
59
60\begin{frame}
61\frametitle{Addressing modes and address spaces}
62Let's recapitulate the main addressing modes and pointer types:
63\begin{itemize}
64\item direct mode (\_\_data / \_\_near modifiers in SDCC syntax),
65      to access Low Internal RAM
66\item direct mode (fixed address in SDCC syntax), to access SFRs
67\item indirect mode (\_\_idata modifier in SDCC syntax),
68      to access (Low +) High Internal RAM
69\item external mode (\_\_xdata / \_\_far modifier in SDCC syntax)
70      to access External RAM
71\item indirect external mode a.k.a. paged data (\_\_pdata modifier in SDCC
72      syntax) to access the first 256 bytex of External RAM
73\item code mode (\_\_code modifier in SDCC syntax) to access Code Memory
74\item bit mode (\_\_bit modifier in SDCC syntax) to access Bit Memory
75\end{itemize}
76\end{frame}
77
78\begin{frame}
79\frametitle{SDCC and addressing modes}
80Memory model + ad-hoc modifiers
81\begin{itemize}
82\item the memory model (Small/Medium/Large) determines where un-modified
83      variable declarations are put (e.g. \texttt{int foo;})
84\item modified variables are put where the user wants them to be
85      (e.g. \texttt \_\_xdata int foo;)
86\item the \texttt{\_\_using} modifier is used to switch memory bank for
87      registers (see next slide), e.g. in interrupt routines
88\item pointers and pointers passing in SDCC:
89 \begin{itemize}
90  \item generic pointers (e.g. \texttt{int *foo;}); three bytes long
91        (1 selector + 16 bits at most)
92  \item labelled pointers (e.g. \texttt{int * \_\_idata foo;}); one/two bytes
93        long
94 \end{itemize}
95\end{itemize}
96\end{frame}
97
98\begin{frame}
99\frametitle{calling convention (SDCC)}
100\begin{itemize}
101\item all Rx register are caller-saved
102\item DPL/DPH, B and ACC are used for first parameter/return value passing:
103 \begin{itemize}
104  \item 1 byte: DPL
105  \item 2 bytes: DPL + DPH
106  \item 3 bytes: DPH + DPL + B (generic pointers: B=0x00 xdata, B=0xe0 idata,
107        B=0x60 pdata, B=0x80 code)
108  \item 4 bytes: DPH + DPL + B + ACC
109 \end{itemize}
110\item first bit argument is passed in a pre-defined bit address
111\item remaining arguments passed on the stack
112\end{itemize}
113\end{frame}
114
115\begin{frame}
116\frametitle{The `R' registers}
117\begin{itemize}
118\item
119The `R' registers are the 8051's general purpose registers, numbered R0--R7.
120\item
121The `R' registers are really part of internal RAM.  Thus memory address $04h$ is really register R4.
122\item
123\textbf{However!}  The 8051 has four distinct register banks, occupying the first 32 bytes of internal RAM.
124\item
125Bank 0 (addresses 00h--07h) is used by default, but this can be changed.
126\item
127If we decide to use bank 3, R4 is no longer identified with memory location 04h, but instead shifted to 1CH.
128\item Note: most operands work on the accumulator register A that is a SFR
129 and not an Rx register
130\end{itemize}
131\end{frame}
132
133\begin{frame}
134\frametitle{Bit memory}
135\begin{itemize}
136\item
137The 8051 provides 128 bit variables to the user, numbered 00h--7Fh.
138\item
139Like the `R' registers, bit memory is really a part of internal RAM.
140\item
141Bit memory is located at internal RAM addresses 20h--2Fh, therefore writing FFh to internal RAM address 20h effectively sets bits 00h through 07h.
142\item
143Though part of internal RAM, the 8051 provides specific instructions for setting and clearing bits in bit memory.
144\end{itemize}
145\end{frame}
146
147\begin{frame}
148\frametitle{A note on the stack pointer (SP)}
149\begin{itemize}
150\item
151At powerup, the 8051 initialises the SP to address 07h.
152\item
153The stack therefore starts at 08h and expands upwards.
154\item
155Care must be taken if we decide to use the alternative register banks to initialise the stack pointer above the chosen bank.
156\item
157Further, if using bit variables, it's a good idea to initialise the stack point above address 2Fh, to ensure bit variables are not overwritten by the growing stack.
158\end{itemize}
159\end{frame}
160
161\begin{frame}
162\frametitle{Special function registers (SFRs)}
163\begin{itemize}
164\item
165The special function registers (SFRs) are areas of memory dedicated to controlling specific functionality of the 8051.
166\item
167The 8051 maintains the illusion that SFRs are a part of internal memory: writing 1 to the serial port is achieved by moving 01h to memory location 99h (an SFR controlling serial port activity).
168\item
169However, SFRs are \emph{not} part of internal memory: any modification to memory addresses 00h--7Fh modifies internal RAM, whereas 80h--7Fh modifies the SFRs.
170\item
171On the standard 8051, there are 21 SFRs, falling into three basic classes: those related to I/O, those related to controlling the operation of the processor, and auxiliary SFRs.
172\item
173Derivative processors are also free to add bespoke SFRs that control additional functionality of their chips.
174\end{itemize}
175\end{frame}
176
177\begin{frame}
178\frametitle{I/O SFRs}
179\begin{itemize}
180\item
181The 32 I/O lines of the 8051 are controlled by four SFRs: P0--P4.
182\item
183Individual I/O lines are controlled by setting bits of the requisite SFR.
184\item
185Bit 0 of port 0 is pin P0.0, for instance.  Writing 1 to this bit will send a `high' level on the corresponding output line, whereas 0 corresponds to a `low' level.
186\end{itemize}
187\end{frame}
188
189\begin{frame}
190\frametitle{Control SFRs (I)}
191\begin{itemize}
192\item
193There are seven control SFRs: PCON, TCON, TMOD, SCON, IE, IP and PSW.
194\item
195Setting PCON places the processor into a power saving mode.
196\item
197TCON is a control flag for the processor's timers, and signals when they overflow.  Further, some non-timer related functionality is included, related to how external interrupts are activated.
198\item
199TMOD sets the operating mode of the timer: an 8 bit timer that autoreloads, one 16 bit timer, a 13 bit timer, or two separate 8 bit timers.
200\item
201IE is the `interrupt enable' flag, used to enable and disable specific interrupts.
202\end{itemize}
203\end{frame}
204
205\begin{frame}
206\frametitle{Control SFRs (II)}
207\begin{itemize}
208\item
209IP is the `interrupt priority' flag.  The 8051 has two interrupt priority modes: low and high.
210\item
211An interrupt with a high priority can always interrupt another interrupt of lower priority.  An interrupt with high priority can never be interrupted (even by another with high priority).
212\item
213PSW is the `program status word'.  This contains a number of important flags, for instance, Carry, Overflow, Parity, etc.  This SFR also contains the flag used to select the active register bank.
214\end{itemize}
215\end{frame}
216
217\begin{frame}
218\frametitle{Auxiliary SFRs}
219\begin{itemize}
220\item
221There are 10 auxiliary SFRs: SP, DPL, DPH, TL0, TL1, TH0, TH1, SBUF, ACC and B.
222\item
223SP is the stack pointer.
224\item
225DPL and DPH are the `data pointer high' and `data pointer low' SFRs.  These act together to give a 16 bit data pointer used in operations regarding external RAM and code memory.
226\item
227Oddity: though there's an explicit instruction to increment the DPTR, there's no instruction to decrement it.
228\item
229TL0--TH1 are the timers.
230\item
231SBUF is the 8051's serial buffer.
232\item
233ACC and B are two accumulator registers, with ACC being the primary accumulator.
234\item
235Only a small number of operations involve the B register, so this can optionally be used as an additional general purpose register.
236\end{itemize}
237\end{frame}
238
239\begin{frame}
240\frametitle{Addressing modes}
241\begin{itemize}
242\item
243The 8051 has three modes for addressing memory: immediate, direct and indirect.
244\item
245When using direct addressing, any location between addresses 00h and 7Fh is internal RAM, whereas addresses between 80h and FFh are SFRs.
246\item
247Oddity: the 8052 provides 128 bit extra internal RAM, and this cannot be accessed through direct addressing (address clash with the SFRs), use indirect addressing instead.
248\item
249Indirect addressing \emph{always} refers to internal RAM, never to an SFR.
250\end{itemize}
251\end{frame}
252
253\begin{frame}
254\frametitle{Interrupts}
255\begin{itemize}
256\item
257There are three classes of events that can trigger an interrupt: timer overflow, reception and transmission of a serial character, and external events.
258\item
259By default, all interrupts are disabled.  They must be enabled by modifying the IE SFR.
260\item
261Interrupt handlers are assigned a fixed address, within the range 0003h--0023h.
262\item
263There is a fixed polling sequence for interrupts: with external and timing interrupts being polled before serial interrupts.
264\item
265If two interrupts occur at the same time, and both are assigned the same interrupt priority, then whichever has precedence in the polling sequence is handled first.
266\end{itemize}
267\end{frame}
268
269\begin{frame}
270\frametitle{Topics not covered}
271\begin{itemize}
272\item
273Timers, and using timers to set serial baud rates
274\item
275Serial port access and settings
276\end{itemize}
277\end{frame}
278
279\begin{frame}
280\frametitle{Executable semantics issues}
281Assembly executable semantics vs real code executable semantics
282\begin{itemize}
283\item Labels and jumps/calls: several opcodes according to the target distance.\\
284      Introduce pseudo-instructions?
285\item Labels for data: labels in different memory areas require totally
286      different opcodes
287\item What to model? (I/O? timers? interrupts?)
288\item How to model I/O, timers and interrupts?
289\end{itemize}
290Right now, only the real code executable semantics is (partially) implemented
291together with fetching and assemblying (but no pseudo-instructions and no labels).
292\end{frame}
293
294\end{document}
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