source: Deliverables/D4.1/Presentation/Paris-September-2010.tex @ 38

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First draft Claudio's talk finished.

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1\documentclass[serif]{beamer}
2
3\author{Claudio Sacerdoti Coen}
4\title{A brief introduction to the 8051 processor \\\vspace{\baselineskip} \small{CerCo project meeting, Paris, September 2010}}
5\date{\today}
6
7\begin{document}
8
9\begin{frame}
10\maketitle
11\end{frame}
12
13\begin{frame}
14\frametitle{Vital statistics I}
15The 8051 is:
16\begin{itemize}
17\item
188 bit microprocessor introduced in 1980 by Intel, very popular, still manufactured by a host of companies (many European!)
19\item
20Three different types of memory: on-chip memory (code, RAM, or other) that physically resides on processor die, external code memory and external RAM
21\item
22128 bytes of internal RAM, subdivided into different sections (the register banks, bit memory, stack space and general RAM)
23\item
24At most, stack space is 80 bytes, but often less (very small!)
25\end{itemize}
26\end{frame}
27
28\begin{frame}
29\frametitle{Vital statistics II}
30\begin{itemize}
31\item
32Two timers with multiple modes of operation (8052 adds a third timer with more modes)
33\item
34Serial (UART) port and 32 input/output lines
35\item
36Two-levels of priority for interrupts
37\end{itemize}
38\end{frame}
39
40\begin{frame}
41\frametitle{The `R' registers}
42\begin{itemize}
43\item
44The `R' registers are the 8051's general purpose registers, numbered R0--R7.
45\item
46The `R' registers are really part of internal RAM.  Thus memory address $04h$ is really register R4.
47\item
48\textbf{However!}  The 8051 has four distinct register banks, occupying the first 32 bytes of internal RAM.
49\item
50Bank 0 (addresses 00h--07h) is used by default, but this can be changed.
51\item
52If we decide to use bank 3, R4 is no longer identified with memory location 04h, but instead shifted to 1CH.
53\end{itemize}
54\end{frame}
55
56\begin{frame}
57\frametitle{Bit memory}
58\begin{itemize}
59\item
60The 8051 provides 128 bit variables to the user, numbered 00h--7Fh.
61\item
62Like the `R' registers, bit memory is really a part of internal RAM.
63\item
64Bit memory is located at internal RAM addresses 20h--2Fh, therefore writing FFh to internal RAM address 20h effectively sets bits 00h through 07h.
65\item
66Though part of internal RAM, the 8051 provides specific instructions for setting and clearing bits in bit memory.
67\end{itemize}
68\end{frame}
69
70\begin{frame}
71\frametitle{A note on the stack pointer (SP)}
72\begin{itemize}
73\item
74At powerup, the 8051 initialises the SP to address 07h.
75\item
76The stack therefore starts at 08h and expands upwards.
77\item
78Care must be taken if we decide to use the alternative register banks to initialise the stack pointer above the chosen bank.
79\item
80Further, if using bit variables, it's a good idea to initialise the stack point above address 2Fh, to ensure bit variables are not overwritten by the growing stack.
81\end{itemize}
82\end{frame}
83
84\begin{frame}
85\frametitle{Special function registers (SFRs)}
86\begin{itemize}
87\item
88The special function registers (SFRs) are areas of memory dedicated to controlling specific functionality of the 8051.
89\item
90The 8051 maintains the illusion that SFRs are a part of internal memory: writing 1 to the serial port is achieved by moving 01h to memory location 99h (an SFR controlling serial port activity).
91\item
92However, SFRs are \emph{not} part of internal memory: any modification to memory addresses 00h--7Fh modifies internal RAM, whereas 80h--7Fh modifies the SFRs.
93\item
94On the standard 8051, there are 21 SFRs, falling into three basic classes: those related to I/O, those related to controlling the operation of the processor, and auxiliary SFRs.
95\item
96Derivative processors are also free to add bespoke SFRs that control additional functionality of their chips.
97\end{itemize}
98\end{frame}
99
100\begin{frame}
101\frametitle{I/O SFRs}
102\begin{itemize}
103\item
104The 32 I/O lines of the 8051 are controlled by four SFRs: P0--P4.
105\item
106Individual I/O lines are controlled by setting bits of the requisite SFR.
107\item
108Bit 0 of port 0 is pin P0.0, for instance.  Writing 1 to this bit will send a `high' level on the corresponding output line, whereas 0 corresponds to a `low' level.
109\end{itemize}
110\end{frame}
111
112\begin{frame}
113\frametitle{Control SFRs (I)}
114\begin{itemize}
115\item
116There are seven control SFRs: PCON, TCON, TMOD, SCON, IE, IP and PSW.
117\item
118Setting PCON places the processor into a power saving mode.
119\item
120TCON is a control flag for the processor's timers, and signals when they overflow.  Further, some non-timer related functionality is included, related to how external interrupts are activated.
121\item
122TMOD sets the operating mode of the timer: an 8 bit timer that autoreloads, one 16 bit timer, a 13 bit timer, or two separate 8 bit timers.
123\item
124IE is the `interrupt enable' flag, used to enable and disable specific interrupts.
125\end{itemize}
126\end{frame}
127
128\begin{frame}
129\frametitle{Control SFRs (II)}
130\begin{itemize}
131\item
132IP is the `interrupt priority' flag.  The 8051 has two interrupt priority modes: low and high.
133\item
134An interrupt with a high priority can always interrupt another interrupt of lower priority.  An interrupt with high priority can never be interrupted (even by another with high priority).
135\item
136PSW is the `program status word'.  This contains a number of important flags, for instance, Carry, Overflow, Parity, etc.  This SFR also contains the flag used to select the active register bank.
137\end{itemize}
138\end{frame}
139
140\begin{frame}
141\frametitle{Auxiliary SFRs}
142\begin{itemize}
143\item
144There are 10 auxiliary SFRs: SP, DPL, DPH, TL0, TL1, TH0, TH1, SBUF, ACC and B.
145\item
146SP is the stack pointer.
147\item
148DPL and DPH are the `data pointer high' and `data pointer low' SFRs.  These act together to give a 16 bit data pointer used in operations regarding external RAM and code memory.
149\item
150Oddity: though there's an explicit instruction to increment the DPTR, there's no instruction to decrement it.
151\item
152TL0--TH1 are the timers.
153\item
154SBUF is the 8051's serial buffer.
155\item
156ACC and B are two accumulator registers, with ACC being the primary accumulator.
157\item
158Only a small number of operations involve the B register, so this can optionally be used as an additional general purpose register.
159\end{itemize}
160\end{frame}
161
162\begin{frame}
163\frametitle{Addressing modes}
164\begin{itemize}
165\item
166The 8051 has three modes for addressing memory: immediate, direct and indirect.
167\item
168When using direct addressing, any location between addresses 00h and 7Fh is internal RAM, whereas addresses between 80h and FFh are SFRs.
169\item
170Oddity: the 8052 provides 128 bit extra internal RAM, and this cannot be accessed through direct addressing (address clash with the SFRs), use indirect addressing instead.
171\item
172Indirect addressing \emph{always} refers to internal RAM, never to an SFR.
173\end{itemize}
174\end{frame}
175
176\begin{frame}
177\frametitle{Interrupts}
178\begin{itemize}
179\item
180There are three classes of events that can trigger an interrupt: timer overflow, reception and transmission of a serial character, and external events.
181\item
182By default, all interrupts are disabled.  They must be enabled by modifying the IE SFR.
183\item
184Interrupt handlers are assigned a fixed address, within the range 0003h--0023h.
185\item
186There is a fixed polling sequence for interrupts: with external and timing interrupts being polled before serial interrupts.
187\item
188If two interrupts occur at the same time, and both are assigned the same interrupt priority, then whichever has precedence in the polling sequence is handled first.
189\end{itemize}
190\end{frame}
191
192\begin{frame}
193\frametitle{Topics not covered}
194\begin{itemize}
195\item
196Timers, and using timers to set serial baud rates
197\item
198Serial port access and settings
199\end{itemize}
200\end{frame}
201
202\end{document}
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