1 | \documentclass[serif]{beamer} |
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2 | |
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3 | \author{Claudio Sacerdoti Coen} |
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4 | \title{A brief introduction to the 8051 processor \\\vspace{\baselineskip} \small{CerCo project meeting, Paris, September 2010}} |
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5 | \date{\today} |
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6 | |
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7 | \begin{document} |
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8 | |
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9 | \begin{frame} |
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10 | \maketitle |
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11 | \end{frame} |
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12 | |
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13 | \begin{frame} |
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14 | \frametitle{Vital statistics I} |
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15 | The 8051 is: |
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16 | \begin{itemize} |
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17 | \item |
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18 | 8 bit microprocessor introduced in 1980 by Intel, very popular, still manufactured by a host of companies (many European!) |
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19 | \item |
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20 | Three different types of memory: on-chip memory (code, RAM, or other) that physically resides on processor die, external code memory and external RAM |
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21 | \item |
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22 | 128 bytes of internal RAM, subdivided into different sections (the register banks, bit memory, stack space and general RAM) |
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23 | \item |
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24 | At most, stack space is 80 bytes, but often less (very small!) |
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25 | \end{itemize} |
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26 | \end{frame} |
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27 | |
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28 | \begin{frame} |
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29 | \frametitle{Vital statistics II} |
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30 | \begin{itemize} |
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31 | \item |
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32 | Two timers with multiple modes of operation (8052 adds a third timer with more modes) |
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33 | \item |
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34 | Serial (UART) port and 32 input/output lines |
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35 | \item |
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36 | Two-levels of priority for interrupts |
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37 | \end{itemize} |
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38 | \end{frame} |
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39 | |
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40 | \begin{frame} |
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41 | \frametitle{The `R' registers} |
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42 | \begin{itemize} |
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43 | \item |
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44 | The `R' registers are the 8051's general purpose registers, numbered R0--R7. |
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45 | \item |
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46 | The `R' registers are really part of internal RAM. Thus memory address $04h$ is really register R4. |
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47 | \item |
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48 | \textbf{However!} The 8051 has four distinct register banks, occupying the first 32 bytes of internal RAM. |
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49 | \item |
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50 | Bank 0 (addresses 00h--07h) is used by default, but this can be changed. |
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51 | \item |
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52 | If we decide to use bank 3, R4 is no longer identified with memory location 04h, but instead shifted to 1CH. |
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53 | \end{itemize} |
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54 | \end{frame} |
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55 | |
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56 | \begin{frame} |
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57 | \frametitle{Bit memory} |
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58 | \begin{itemize} |
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59 | \item |
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60 | The 8051 provides 128 bit variables to the user, numbered 00h--7Fh. |
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61 | \item |
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62 | Like the `R' registers, bit memory is really a part of internal RAM. |
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63 | \item |
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64 | Bit memory is located at internal RAM addresses 20h--2Fh, therefore writing FFh to internal RAM address 20h effectively sets bits 00h through 07h. |
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65 | \item |
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66 | Though part of internal RAM, the 8051 provides specific instructions for setting and clearing bits in bit memory. |
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67 | \end{itemize} |
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68 | \end{frame} |
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69 | |
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70 | \begin{frame} |
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71 | \frametitle{A note on the stack pointer (SP)} |
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72 | \begin{itemize} |
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73 | \item |
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74 | At powerup, the 8051 initialises the SP to address 07h. |
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75 | \item |
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76 | The stack therefore starts at 08h and expands upwards. |
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77 | \item |
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78 | Care must be taken if we decide to use the alternative register banks to initialise the stack pointer above the chosen bank. |
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79 | \item |
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80 | Further, if using bit variables, it's a good idea to initialise the stack point above address 2Fh, to ensure bit variables are not overwritten by the growing stack. |
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81 | \end{itemize} |
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82 | \end{frame} |
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83 | |
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84 | \begin{frame} |
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85 | \frametitle{Special function registers (SFRs)} |
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86 | \begin{itemize} |
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87 | \item |
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88 | The special function registers (SFRs) are areas of memory dedicated to controlling specific functionality of the 8051. |
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89 | \item |
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90 | The 8051 maintains the illusion that SFRs are a part of internal memory: writing 1 to the serial port is achieved by moving 01h to memory location 99h (an SFR controlling serial port activity). |
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91 | \item |
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92 | However, SFRs are \emph{not} part of internal memory: any modification to memory addresses 00h--7Fh modifies internal RAM, whereas 80h--7Fh modifies the SFRs. |
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93 | \item |
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94 | On the standard 8051, there are 21 SFRs, falling into three basic classes: those related to I/O, those related to controlling the operation of the processor, and auxiliary SFRs. |
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95 | \item |
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96 | Derivative processors are also free to add bespoke SFRs that control additional functionality of their chips. |
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97 | \end{itemize} |
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98 | \end{frame} |
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99 | |
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100 | \begin{frame} |
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101 | \frametitle{I/O SFRs} |
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102 | \begin{itemize} |
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103 | \item |
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104 | The 32 I/O lines of the 8051 are controlled by four SFRs: P0--P4. |
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105 | \item |
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106 | Individual I/O lines are controlled by setting bits of the requisite SFR. |
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107 | \item |
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108 | Bit 0 of port 0 is pin P0.0, for instance. Writing 1 to this bit will send a `high' level on the corresponding output line, whereas 0 corresponds to a `low' level. |
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109 | \end{itemize} |
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110 | \end{frame} |
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111 | |
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112 | \begin{frame} |
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113 | \frametitle{Control SFRs (I)} |
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114 | \begin{itemize} |
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115 | \item |
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116 | There are seven control SFRs: PCON, TCON, TMOD, SCON, IE, IP and PSW. |
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117 | \item |
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118 | Setting PCON places the processor into a power saving mode. |
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119 | \item |
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120 | TCON is a control flag for the processor's timers, and signals when they overflow. Further, some non-timer related functionality is included, related to how external interrupts are activated. |
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121 | \item |
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122 | TMOD sets the operating mode of the timer: an 8 bit timer that autoreloads, one 16 bit timer, a 13 bit timer, or two separate 8 bit timers. |
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123 | \item |
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124 | IE is the `interrupt enable' flag, used to enable and disable specific interrupts. |
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125 | \end{itemize} |
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126 | \end{frame} |
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127 | |
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128 | \begin{frame} |
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129 | \frametitle{Control SFRs (II)} |
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130 | \begin{itemize} |
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131 | \item |
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132 | IP is the `interrupt priority' flag. The 8051 has two interrupt priority modes: low and high. |
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133 | \item |
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134 | An interrupt with a high priority can always interrupt another interrupt of lower priority. An interrupt with high priority can never be interrupted (even by another with high priority). |
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135 | \item |
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136 | PSW is the `program status word'. This contains a number of important flags, for instance, Carry, Overflow, Parity, etc. This SFR also contains the flag used to select the active register bank. |
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137 | \end{itemize} |
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138 | \end{frame} |
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139 | |
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140 | \begin{frame} |
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141 | \frametitle{Auxiliary SFRs} |
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142 | \begin{itemize} |
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143 | \item |
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144 | There are 10 auxiliary SFRs: SP, DPL, DPH, TL0, TL1, TH0, TH1, SBUF, ACC and B. |
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145 | \item |
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146 | SP is the stack pointer. |
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147 | \item |
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148 | DPL and DPH are the `data pointer high' and `data pointer low' SFRs. These act together to give a 16 bit data pointer used in operations regarding external RAM and code memory. |
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149 | \item |
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150 | Oddity: though there's an explicit instruction to increment the DPTR, there's no instruction to decrement it. |
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151 | \item |
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152 | TL0--TH1 are the timers. |
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153 | \item |
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154 | SBUF is the 8051's serial buffer. |
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155 | \item |
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156 | ACC and B are two accumulator registers, with ACC being the primary accumulator. |
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157 | \item |
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158 | Only a small number of operations involve the B register, so this can optionally be used as an additional general purpose register. |
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159 | \end{itemize} |
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160 | \end{frame} |
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161 | |
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162 | \begin{frame} |
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163 | \frametitle{Addressing modes} |
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164 | \begin{itemize} |
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165 | \item |
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166 | The 8051 has three modes for addressing memory: immediate, direct and indirect. |
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167 | \item |
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168 | When using direct addressing, any location between addresses 00h and 7Fh is internal RAM, whereas addresses between 80h and FFh are SFRs. |
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169 | \item |
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170 | Oddity: the 8052 provides 128 bit extra internal RAM, and this cannot be accessed through direct addressing (address clash with the SFRs), use indirect addressing instead. |
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171 | \item |
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172 | Indirect addressing \emph{always} refers to internal RAM, never to an SFR. |
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173 | \end{itemize} |
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174 | \end{frame} |
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175 | |
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176 | \begin{frame} |
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177 | \frametitle{Interrupts} |
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178 | \end{frame} |
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179 | |
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180 | \end{document} |
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