source: Deliverables/D4.1/Presentation/Paris-September-2010.tex @ 36

\documentclass[serif]{beamer}

\author{Claudio Sacerdoti Coen}
\title{A brief introduction to the 8051 processor \\\vspace{\baselineskip} \small{CerCo project meeting, Paris, September 2010}}
\date{\today}

\begin{document}

\begin{frame}
\maketitle
\end{frame}

\begin{frame}
\frametitle{Vital statistics I}
The 8051 is:
\begin{itemize}
\item
8 bit microprocessor introduced in 1980 by Intel, very popular, still manufactured by a host of companies (many European!)
\item
Three different types of memory: on-chip memory (code, RAM, or other) that physically resides on processor die, external code memory and external RAM
\item
128 bytes of internal RAM, subdivided into different sections (the register banks, bit memory, stack space and general RAM)
\item
At most, stack space is 80 bytes, but often less (very small!)
\end{itemize}
\end{frame}

\begin{frame}
\frametitle{Vital statistics II}
\begin{itemize}
\item
Two timers with multiple modes of operation (8052 adds a third timer with more modes)
\item
Serial (UART) port and 32 input/output lines
\item
Two-levels of priority for interrupts
\end{itemize}
\end{frame}

\begin{frame}
\frametitle{The `R' registers}
\begin{itemize}
\item
The `R' registers are the 8051's general purpose registers, numbered R0--R7.
\item
The `R' registers are really part of internal RAM.  Thus memory address $04h$ is really register R4.
\item
\textbf{However!}  The 8051 has four distinct register banks, occupying the first 32 bytes of internal RAM.
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Bank 0 (addresses 00h--07h) is used by default, but this can be changed.
\item
If we decide to use bank 3, R4 is no longer identified with memory location 04h, but instead shifted to 1CH.
\end{itemize}
\end{frame}

\begin{frame}
\frametitle{Bit memory}
\begin{itemize}
\item
The 8051 provides 128 bit variables to the user, numbered 00h--7Fh.
\item
Like the `R' registers, bit memory is really a part of internal RAM.
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Bit memory is located at internal RAM addresses 20h--2Fh, therefore writing FFh to internal RAM address 20h effectively sets bits 00h through 07h.
\item
Though part of internal RAM, the 8051 provides specific instructions for setting and clearing bits in bit memory.
\end{itemize}
\end{frame}

\begin{frame}
\frametitle{A note on the stack pointer (SP)}
\begin{itemize}
\item
At powerup, the 8051 initialises the SP to address 07h.
\item
The stack therefore starts at 08h and expands upwards.
\item
Care must be taken if we decide to use the alternative register banks to initialise the stack pointer above the chosen bank.
\item
Further, if using bit variables, it's a good idea to initialise the stack point above address 2Fh, to ensure bit variables are not overwritten by the growing stack.
\end{itemize}
\end{frame}

\begin{frame}
\frametitle{Special function registers (SFRs)}
\begin{itemize}
\item
The special function registers (SFRs) are areas of memory dedicated to controlling specific functionality of the 8051.
\item
The 8051 maintains the illusion that SFRs are a part of internal memory: writing 1 to the serial port is achieved by moving 01h to memory location 99h (an SFR controlling serial port activity).
\item
However, SFRs are \emph{not} part of internal memory: any modification to memory addresses 00h--7Fh modifies internal RAM, whereas 80h--7Fh modifies the SFRs.
\item
On the standard 8051, there are 21 SFRs, falling into three basic classes: those related to I/O, those related to controlling the operation of the processor, and auxiliary SFRs.
\item
Derivative processors are also free to add bespoke SFRs that control additional functionality of their chips.
\end{itemize}
\end{frame}

\begin{frame}
\frametitle{I/O SFRs}
\begin{itemize}
\item
The 32 I/O lines of the 8051 are controlled by four SFRs: P0--P4.
\item
Individual I/O lines are controlled by setting bits of the requisite SFR.
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Bit 0 of port 0 is pin P0.0, for instance.  Writing 1 to this bit will send a `high' level on the corresponding output line, whereas 0 corresponds to a `low' level.
\end{itemize}
\end{frame}

\begin{frame}
\frametitle{Control SFRs (I)}
\begin{itemize}
\item
There are seven control SFRs: PCON, TCON, TMOD, SCON, IE, IP and PSW.
\item
Setting PCON places the processor into a power saving mode.
\item
TCON is a control flag for the processor's timers, and signals when they overflow.  Further, some non-timer related functionality is included, related to how external interrupts are activated.
\item
TMOD sets the operating mode of the timer: an 8 bit timer that autoreloads, one 16 bit timer, a 13 bit timer, or two separate 8 bit timers.
\item
IE is the `interrupt enable' flag, used to enable and disable specific interrupts.
\end{itemize}
\end{frame}

\begin{frame}
\frametitle{Control SFRs (II)}
\begin{itemize}
\item
IP is the `interrupt priority' flag.  The 8051 has two interrupt priority modes: low and high.
\item
An interrupt with a high priority can always interrupt another interrupt of lower priority.  An interrupt with high priority can never be interrupted (even by another with high priority).
\item
PSW is the `program status word'.  This contains a number of important flags, for instance, Carry, Overflow, Parity, etc.  This SFR also contains the flag used to select the active register bank.
\end{itemize}
\end{frame}

\begin{frame}
\frametitle{Auxiliary SFRs}
\begin{itemize}
\item
There are 10 auxiliary SFRs: SP, DPL, DPH, TL0, TL1, TH0, TH1, SBUF, ACC and B.
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SP is the stack pointer.
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DPL and DPH are the `data pointer high' and `data pointer low' SFRs.  These act together to give a 16 bit data pointer used in operations regarding external RAM and code memory.
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Oddity: though there's an explicit instruction to increment the DPTR, there's no instruction to decrement it.
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TL0--TH1 are the timers.
\item
SBUF is the 8051's serial buffer.
\item
ACC and B are two accumulator registers, with ACC being the primary accumulator.
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Only a small number of operations involve the B register, so this can optionally be used as an additional general purpose register.
\end{itemize}
\end{frame}

\begin{frame}
\frametitle{Addressing modes}
\begin{itemize}
\item
The 8051 has three modes for addressing memory: immediate, direct and indirect.
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When using direct addressing, any location between addresses 00h and 7Fh is internal RAM, whereas addresses between 80h and FFh are SFRs.
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Oddity: the 8052 provides 128 bit extra internal RAM, and this cannot be accessed through direct addressing (address clash with the SFRs), use indirect addressing instead.
\item
Indirect addressing \emph{always} refers to internal RAM, never to an SFR.
\end{itemize}
\end{frame}

\begin{frame}
\frametitle{Interrupts}
\end{frame}

\end{document}