source: Deliverables/D4.1/Presentation/Paris-September-2010.tex @ 164

\documentclass[serif]{beamer}

\author{Dominic Mulligan \and \alert{Claudio Sacerdoti Coen}}
\title{A brief introduction to the 8051 processor \\\vspace{\baselineskip} \small{CerCo project meeting, Paris, September 2010}}
\date{\today}

\begin{document}

\begin{frame}
\maketitle
\end{frame}

\begin{frame}
\frametitle{Vital statistics I}
The 8051 (a.k.a. 8052, 80C51, MCS51) is:
\begin{itemize}
\item
8 bit microprocessor introduced in 1980 by Intel, very popular, still manufactured by a host of companies (many European!)
\item
Three different types of memory: on-chip memory (code, RAM, or other) that physically resides on processor die, external code memory and external RAM
\item
128 bytes of internal RAM, subdivided into different sections (the register banks, bit memory, stack space and general RAM)
\item
At most, stack space is 80 bytes, but often less (very small!)\\
But ways of having the stack in external RAM\ldots
\end{itemize}
\end{frame}

\begin{frame}
\frametitle{Vital statistics II}
\begin{itemize}
\item
Two timers with multiple modes of operation (8052 adds a third timer with more modes)
\item
Serial (UART) port and 32 input/output lines
\item Interrupts only for I/O, could be entirely replaced by polling
\item Two levels of priority for interrupts (cfr. four register banks)
\item All instructions take a fixed, known-in-advance number of clock-cycles
\end{itemize}
\end{frame}

\begin{frame}
\frametitle{Memory model}
Several distinct (not disjoint) memory areas and addressing mode (hence
pointer type):
\begin{itemize}
 \item Code memory; ad-hoc access, read-only, may be partially on-die
 \item Low internal RAM (128 bytes); direct + indirect address
 \item High internal RAM (128 bytes); indirect access only
 \item External RAM; ad-hoc access only via DPTR (16 bits SFR)
 \item Low External RAM; ad-hoc indirect access, overlaps with External RAM
 \item Memory-mapped I/O + Special Function Registers (SFRs); direct access only
 \item Bit memory (256 addresses); ad-hoc access, 1/2 overlaps with
       Low Internal RAM, 1/2 overlaps with Special Function Registers
 \item Four register banks, 8 registers each; direct + indirect + ad-hoc
       access, fully overlaps with Low Internal RAM
\end{itemize}
\end{frame}

\begin{frame}
\frametitle{Addressing modes and address spaces}
Let's recapitulate the main addressing modes and pointer types:
\begin{itemize}
\item direct mode (\_\_data / \_\_near modifiers in SDCC syntax),
      to access Low Internal RAM
\item direct mode (fixed address in SDCC syntax), to access SFRs
\item indirect mode (\_\_idata modifier in SDCC syntax),
      to access (Low +) High Internal RAM
\item external mode (\_\_xdata / \_\_far modifier in SDCC syntax)
      to access External RAM
\item indirect external mode a.k.a. paged data (\_\_pdata modifier in SDCC
      syntax) to access the first 256 bytex of External RAM
\item code mode (\_\_code modifier in SDCC syntax) to access Code Memory
\item bit mode (\_\_bit modifier in SDCC syntax) to access Bit Memory
\end{itemize}
\end{frame}

\begin{frame}
\frametitle{SDCC and addressing modes}
Memory model + ad-hoc modifiers
\begin{itemize}
\item the memory model (Small/Medium/Large) determines where un-modified
      variable declarations are put (e.g. \texttt{int foo;})
\item modified variables are put where the user wants them to be
      (e.g. \texttt \_\_xdata int foo;)
\item the \texttt{\_\_using} modifier is used to switch memory bank for
      registers (see next slide), e.g. in interrupt routines
\item pointers and pointers passing in SDCC:
 \begin{itemize}
  \item generic pointers (e.g. \texttt{int *foo;}); three bytes long
        (1 selector + 16 bits at most)
  \item labelled pointers (e.g. \texttt{int * \_\_idata foo;}); one/two bytes
        long
 \end{itemize}
\end{itemize}
\end{frame}

\begin{frame}
\frametitle{calling convention (SDCC)}
\begin{itemize}
\item all Rx register are caller-saved
\item DPL/DPH, B and ACC are used for first parameter/return value passing:
 \begin{itemize}
  \item 1 byte: DPL
  \item 2 bytes: DPL + DPH
  \item 3 bytes: DPH + DPL + B (generic pointers: B=0x00 xdata, B=0xe0 idata,
        B=0x60 pdata, B=0x80 code)
  \item 4 bytes: DPH + DPL + B + ACC
 \end{itemize}
\item first bit argument is passed in a pre-defined bit address
\item remaining arguments passed on the stack
\end{itemize}
\end{frame}

\begin{frame}
\frametitle{The `R' registers}
\begin{itemize}
\item
The `R' registers are the 8051's general purpose registers, numbered R0--R7.
\item
The `R' registers are really part of internal RAM.  Thus memory address $04h$ is really register R4.
\item
\textbf{However!}  The 8051 has four distinct register banks, occupying the first 32 bytes of internal RAM.
\item
Bank 0 (addresses 00h--07h) is used by default, but this can be changed.
\item
If we decide to use bank 3, R4 is no longer identified with memory location 04h, but instead shifted to 1CH.
\item Note: most operands work on the accumulator register A that is a SFR
 and not an Rx register
\end{itemize}
\end{frame}

\begin{frame}
\frametitle{Bit memory}
\begin{itemize}
\item
The 8051 provides 128 bit variables to the user, numbered 00h--7Fh.
\item
Like the `R' registers, bit memory is really a part of internal RAM.
\item
Bit memory is located at internal RAM addresses 20h--2Fh, therefore writing FFh to internal RAM address 20h effectively sets bits 00h through 07h.
\item
Though part of internal RAM, the 8051 provides specific instructions for setting and clearing bits in bit memory.
\end{itemize}
\end{frame}

\begin{frame}
\frametitle{A note on the stack pointer (SP)}
\begin{itemize}
\item
At powerup, the 8051 initialises the SP to address 07h.
\item
The stack therefore starts at 08h and expands upwards.
\item
Care must be taken if we decide to use the alternative register banks to initialise the stack pointer above the chosen bank.
\item
Further, if using bit variables, it's a good idea to initialise the stack point above address 2Fh, to ensure bit variables are not overwritten by the growing stack.
\end{itemize}
\end{frame}

\begin{frame}
\frametitle{Special function registers (SFRs)}
\begin{itemize}
\item
The special function registers (SFRs) are areas of memory dedicated to controlling specific functionality of the 8051.
\item
The 8051 maintains the illusion that SFRs are a part of internal memory: writing 1 to the serial port is achieved by moving 01h to memory location 99h (an SFR controlling serial port activity).
\item
However, SFRs are \emph{not} part of internal memory: any modification to memory addresses 00h--7Fh modifies internal RAM, whereas 80h--7Fh modifies the SFRs.
\item
On the standard 8051, there are 21 SFRs, falling into three basic classes: those related to I/O, those related to controlling the operation of the processor, and auxiliary SFRs.
\item
Derivative processors are also free to add bespoke SFRs that control additional functionality of their chips.
\end{itemize}
\end{frame}

\begin{frame}
\frametitle{I/O SFRs}
\begin{itemize}
\item
The 32 I/O lines of the 8051 are controlled by four SFRs: P0--P4.
\item
Individual I/O lines are controlled by setting bits of the requisite SFR.
\item
Bit 0 of port 0 is pin P0.0, for instance.  Writing 1 to this bit will send a `high' level on the corresponding output line, whereas 0 corresponds to a `low' level.
\end{itemize}
\end{frame}

\begin{frame}
\frametitle{Control SFRs (I)}
\begin{itemize}
\item
There are seven control SFRs: PCON, TCON, TMOD, SCON, IE, IP and PSW.
\item
Setting PCON places the processor into a power saving mode.
\item
TCON is a control flag for the processor's timers, and signals when they overflow.  Further, some non-timer related functionality is included, related to how external interrupts are activated.
\item
TMOD sets the operating mode of the timer: an 8 bit timer that autoreloads, one 16 bit timer, a 13 bit timer, or two separate 8 bit timers.
\item
IE is the `interrupt enable' flag, used to enable and disable specific interrupts.
\end{itemize}
\end{frame}

\begin{frame}
\frametitle{Control SFRs (II)}
\begin{itemize}
\item
IP is the `interrupt priority' flag.  The 8051 has two interrupt priority modes: low and high.
\item
An interrupt with a high priority can always interrupt another interrupt of lower priority.  An interrupt with high priority can never be interrupted (even by another with high priority).
\item
PSW is the `program status word'.  This contains a number of important flags, for instance, Carry, Overflow, Parity, etc.  This SFR also contains the flag used to select the active register bank.
\end{itemize}
\end{frame}

\begin{frame}
\frametitle{Auxiliary SFRs}
\begin{itemize}
\item
There are 10 auxiliary SFRs: SP, DPL, DPH, TL0, TL1, TH0, TH1, SBUF, ACC and B.
\item
SP is the stack pointer.
\item
DPL and DPH are the `data pointer high' and `data pointer low' SFRs.  These act together to give a 16 bit data pointer used in operations regarding external RAM and code memory.
\item
Oddity: though there's an explicit instruction to increment the DPTR, there's no instruction to decrement it.
\item
TL0--TH1 are the timers.
\item
SBUF is the 8051's serial buffer.
\item
ACC and B are two accumulator registers, with ACC being the primary accumulator.
\item
Only a small number of operations involve the B register, so this can optionally be used as an additional general purpose register.
\end{itemize}
\end{frame}

\begin{frame}
\frametitle{Addressing modes}
\begin{itemize}
\item
The 8051 has three modes for addressing memory: immediate, direct and indirect.
\item
When using direct addressing, any location between addresses 00h and 7Fh is internal RAM, whereas addresses between 80h and FFh are SFRs.
\item
Oddity: the 8052 provides 128 bit extra internal RAM, and this cannot be accessed through direct addressing (address clash with the SFRs), use indirect addressing instead.
\item
Indirect addressing \emph{always} refers to internal RAM, never to an SFR.
\end{itemize}
\end{frame}

\begin{frame}
\frametitle{Interrupts}
\begin{itemize}
\item
There are three classes of events that can trigger an interrupt: timer overflow, reception and transmission of a serial character, and external events.
\item
By default, all interrupts are disabled.  They must be enabled by modifying the IE SFR.
\item
Interrupt handlers are assigned a fixed address, within the range 0003h--0023h.
\item
There is a fixed polling sequence for interrupts: with external and timing interrupts being polled before serial interrupts.
\item
If two interrupts occur at the same time, and both are assigned the same interrupt priority, then whichever has precedence in the polling sequence is handled first.
\end{itemize}
\end{frame}

\begin{frame}
\frametitle{Topics not covered}
\begin{itemize}
\item
Timers, and using timers to set serial baud rates
\item
Serial port access and settings
\end{itemize}
\end{frame}

\begin{frame}
\frametitle{Executable semantics issues}
Assembly executable semantics vs real code executable semantics
\begin{itemize}
\item Labels and jumps/calls: several opcodes according to the target distance.\\
      Introduce pseudo-instructions?
\item Labels for data: labels in different memory areas require totally
      different opcodes
\item What to model? (I/O? timers? interrupts?)
\item How to model I/O, timers and interrupts?
\end{itemize}
Right now, only the real code executable semantics is (partially) implemented
together with fetching and assemblying (but no pseudo-instructions and no labels).
\end{frame}

\end{document}