source: Deliverables/D4.1/Matita/ASM.ma @ 289

Last change on this file since 289 was 283, checked in by sacerdot, 9 years ago

Bug fixed in type declaration of BIT/N_BIT.

File size: 7.3 KB
Line 
1include "Either.ma".
2include "BitVectorTrie.ma".
3include "String.ma".
4
5ninductive addressing_mode: Type[0] ≝
6  DIRECT: Byte → addressing_mode
7| INDIRECT: Bit → addressing_mode
8| EXT_INDIRECT: Bit → addressing_mode
9| REGISTER: Bit → Bit → Bit → addressing_mode
10| ACC_A: addressing_mode
11| ACC_B: addressing_mode
12| DPTR: addressing_mode
13| DATA: Byte → addressing_mode
14| DATA16: Word → addressing_mode
15| ACC_DPTR: addressing_mode
16| ACC_PC: addressing_mode
17| EXT_INDIRECT_DPTR: addressing_mode
18| INDIRECT_DPTR: addressing_mode
19| CARRY: addressing_mode
20| BIT_ADDR: Byte → addressing_mode
21| N_BIT_ADDR: Byte → addressing_mode
22| RELATIVE: Byte → addressing_mode
23| ADDR11: Word11 → addressing_mode
24| ADDR16: Word → addressing_mode.
25
26ninductive addressing_mode_tag : Type[0] ≝
27  direct: addressing_mode_tag
28| indirect: addressing_mode_tag
29| ext_indirect: addressing_mode_tag
30| register: addressing_mode_tag
31| acc_a: addressing_mode_tag
32| acc_b: addressing_mode_tag
33| dptr: addressing_mode_tag
34| data: addressing_mode_tag
35| data16: addressing_mode_tag
36| acc_dptr: addressing_mode_tag
37| acc_pc: addressing_mode_tag
38| ext_indirect_dptr: addressing_mode_tag
39| indirect_dptr: addressing_mode_tag
40| carry: addressing_mode_tag
41| bit_addr: addressing_mode_tag
42| n_bit_addr: addressing_mode_tag
43| relative: addressing_mode_tag
44| addr11: addressing_mode_tag
45| addr16: addressing_mode_tag.
46
47(* to avoid expansion... *)
48nlet rec is_a (d:addressing_mode_tag) (A:addressing_mode) on d ≝
49  match d with
50   [ direct ⇒ match A with [ DIRECT _ ⇒ true | _ ⇒ false ]
51   | indirect ⇒ match A with [ INDIRECT _ ⇒ true | _ ⇒ false ]
52   | ext_indirect ⇒ match A with [ EXT_INDIRECT _ ⇒ true | _ ⇒ false ]
53   | register ⇒ match A with [ REGISTER _ _ _ ⇒ true | _ ⇒ false ]
54   | acc_a ⇒ match A with [ ACC_A ⇒ true | _ ⇒ false ]
55   | acc_b ⇒ match A with [ ACC_B ⇒ true | _ ⇒ false ]
56   | dptr ⇒ match A with [ DPTR ⇒ true | _ ⇒ false ]
57   | data ⇒ match A with [ DATA _ ⇒ true | _ ⇒ false ]
58   | data16 ⇒ match A with [ DATA16 _ ⇒ true | _ ⇒ false ]
59   | acc_dptr ⇒ match A with [ ACC_DPTR ⇒ true | _ ⇒ false ]
60   | acc_pc ⇒ match A with [ ACC_PC ⇒ true | _ ⇒ false ]
61   | ext_indirect_dptr ⇒ match A with [ EXT_INDIRECT_DPTR ⇒ true | _ ⇒ false ]
62   | indirect_dptr ⇒ match A with [ INDIRECT_DPTR ⇒ true | _ ⇒ false ]
63   | carry ⇒ match A with [ CARRY ⇒ true | _ ⇒ false ]
64   | bit_addr ⇒ match A with [ BIT_ADDR _ ⇒ true | _ ⇒ false ]
65   | n_bit_addr ⇒ match A with [ N_BIT_ADDR _ ⇒ true | _ ⇒ false ]
66   | relative ⇒ match A with [ RELATIVE _ ⇒ true | _ ⇒ false ]
67   | addr11 ⇒ match A with [ ADDR11 _ ⇒ true | _ ⇒ false ]
68   | addr16 ⇒ match A with [ ADDR16 _ ⇒ true | _ ⇒ false ]].
69
70nlet rec is_in n (l: Vector addressing_mode_tag (S n)) (A:addressing_mode) on l : Bool ≝
71 match l return λm.λ_:Vector addressing_mode_tag m .∀K:m=S n.Bool with
72  [ Empty ⇒ λK.⊥
73  | Cons m he (tl: Vector addressing_mode_tag m) ⇒ λ_.
74     match m return λz.m = z → Bool with
75      [ Z ⇒ λ_.is_a he A
76      | S p ⇒ λK.is_a he A ∨ is_in p (? tl) A] (?: m=m)] (?: S n = S n).
77(* CSC: cast not working here: why? *)
78##[##4: #x; ncases K; napply x ]
79//; ndestruct.
80nqed.
81
82ndefinition bool_to_Prop ≝
83 λb. match b with [ true ⇒ True | false ⇒ False ].
84
85nrecord subaddressing_mode (n) (l: Vector addressing_mode_tag (S n)) : Type[0] ≝
86 { subaddressing_modeel:> addressing_mode;
87   subaddressing_modein: bool_to_Prop (is_in ? l subaddressing_modeel)
88 }.
89
90ncoercion subaddressing_mode : ∀n.∀l:Vector addressing_mode_tag (S n).Type[0]
91 ≝ subaddressing_mode on _l: Vector addressing_mode_tag (S ?) to Type[0].
92
93ncoercion mk_subaddressing_mode :
94 ∀n.∀l:Vector addressing_mode_tag (S n).∀a:addressing_mode.
95  ∀p:bool_to_Prop (is_in ? l a).subaddressing_mode n l
96 ≝ mk_subaddressing_mode on a:addressing_mode to subaddressing_mode ? ?.
97
98ninductive jump (A: Type[0]): Type[0] ≝
99  JC: A → jump A
100| JNC: A → jump A
101| JB: Bit → A → jump A
102| JNB: Bit → A → jump A
103| JBC: Bit → A → jump A
104| JZ: A → jump A
105| JNZ: A → jump A
106| CJNE:
107   [[acc_a]] × [[direct; data]] ⊎
108   [[register; indirect]] × [[data]] → A → jump A
109| DJNZ: [[register ; direct]] → A → jump A.
110
111ninductive preinstruction (A: Type[0]) : Type[0] ≝
112   ADD: [[acc_a]] → [[ register ; direct ; indirect ; data ]] → preinstruction A
113 | ADDC: [[acc_a]] → [[ register ; direct ; indirect ; data ]] → preinstruction A
114 | SUBB: [[acc_a]] → [[ register ; direct ; indirect ; data ]] → preinstruction A
115 | INC: [[ acc_a ; register ; direct ; indirect ; dptr ]] → preinstruction A
116 | DEC: [[ acc_a ; register ; direct ; indirect ]] → preinstruction A
117 | MUL: [[acc_a]] → [[acc_b]] → preinstruction A
118 | DIV: [[acc_a]] → [[acc_b]] → preinstruction A
119 | DA: [[acc_a]] → preinstruction A
120
121 (* logical operations *)
122 | ANL:
123   [[acc_a]] × [[ register ; direct ; indirect ; data ]] ⊎
124   [[direct]] × [[ acc_a ; data ]] ⊎
125   [[carry]] × [[ bit_addr ; n_bit_addr]] → preinstruction A
126 | ORL:
127   [[acc_a]] × [[ register ; data ; direct ; indirect ]] ⊎
128   [[direct]] × [[ acc_a ; data ]] ⊎
129   [[carry]] × [[ bit_addr ; n_bit_addr]] → preinstruction A
130 | XRL:
131   [[acc_a]] × [[ data ; register ; direct ; indirect ]] ⊎
132   [[direct]] × [[ acc_a ; data ]] → preinstruction A
133 | CLR: [[ acc_a ; carry ; bit_addr ]] → preinstruction A
134 | CPL: [[ acc_a ; carry ; bit_addr ]] → preinstruction A
135 | RL: [[acc_a]] → preinstruction A
136 | RLC: [[acc_a]] → preinstruction A
137 | RR: [[acc_a]] → preinstruction A
138 | RRC: [[acc_a]] → preinstruction A
139 | SWAP: [[acc_a]] → preinstruction A
140
141 (* data transfer *)
142 | MOV:
143    [[acc_a]] × [[ register ; direct ; indirect ; data ]] ⊎
144    [[ register ; indirect ]] × [[ acc_a ; direct ; data ]] ⊎
145    [[direct]] × [[ acc_a ; register ; direct ; indirect ; data ]] ⊎
146    [[dptr]] × [[data16]] ⊎
147    [[carry]] × [[bit_addr]] ⊎
148    [[bit_addr]] × [[carry]] → preinstruction A
149 | MOVC: [[acc_a]] × [[ acc_dptr ; acc_pc ]] → preinstruction A
150 | MOVX:
151    [[acc_a]] × [[ ext_indirect ; ext_indirect_dptr ]] ⊎
152    [[ ext_indirect ; ext_indirect_dptr ]] × [[acc_a]] → preinstruction A
153 | SETB: [[ carry ; bit_addr ]] → preinstruction A
154 | PUSH: [[direct]] → preinstruction A
155 | POP: [[direct]] → preinstruction A
156 | XCH: [[acc_a]] → [[ register ; direct ; indirect ]] → preinstruction A
157 | XCHD: [[acc_a]] → [[indirect]] → preinstruction A
158
159 (* program branching *)
160 | Jump: jump A → preinstruction A
161 | ACALL: [[addr11]] → preinstruction A
162 | LCALL: [[addr16]] → preinstruction A
163 | RET: preinstruction A
164 | RETI: preinstruction A
165 | AJMP: [[addr11]] → preinstruction A
166 | LJMP: [[addr16]] → preinstruction A
167 | SJMP: [[relative]] → preinstruction A
168 | JMP: [[indirect_dptr]] → preinstruction A
169 | NOP: preinstruction A.
170
171ndefinition instruction ≝ preinstruction [[relative]].
172
173ninductive labelled_instruction: Type[0] ≝
174   Instruction: instruction → labelled_instruction
175 | Cost: String → labelled_instruction
176 | Jmp: String → labelled_instruction
177 | Call: String → labelled_instruction
178 | Mov: [[dptr]] → String → labelled_instruction
179 | WithLabel: preinstruction String → labelled_instruction.
180
181ndefinition preamble ≝ List (String × Nat).
182
183ndefinition assembly_program ≝ preamble × (List labelled_instruction).
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