1 | include "Universes.ma". |
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2 | include "Plogic/equality.ma". |
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3 | include "Either.ma". |
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4 | include "BitVector.ma". |
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5 | include "BitVectorTrie.ma". |
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6 | |
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7 | ninductive all_types : Type[0] ≝ |
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8 | reg: all_types | direct: all_types | indirect:all_types | data:all_types |
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9 | | acc: all_types | rel: all_types. |
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10 | |
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11 | interpretation "Cartesian" 'product A B = (Cartesian A B). |
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12 | interpretation "Either" 'plus A B = (Either A B). |
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13 | |
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14 | ninductive addressing_mode: Type[0] ≝ |
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15 | DIRECT: Byte → addressing_mode |
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16 | | INDIRECT: Bit → addressing_mode |
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17 | | EXTINDIRECT: Bit → addressing_mode |
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18 | | REGISTER: Bit → Bit → Bit → addressing_mode |
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19 | | ACCUMULATORA: addressing_mode |
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20 | | ACCUMULATORB: addressing_mode |
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21 | | DPOINTER: addressing_mode |
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22 | | DATA: Byte → addressing_mode |
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23 | | DATA16: Word → addressing_mode |
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24 | | ACCUMULATORDPOINTER: addressing_mode |
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25 | | ACCUMULATORPROGRAMCOUNTER: addressing_mode |
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26 | | EXTERNALINDIRECTDPOINTER: addressing_mode |
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27 | | INDIRECTDPOINTER: addressing_mode |
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28 | | CARRY: addressing_mode |
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29 | | BIT: Bit → addressing_mode |
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30 | | COMPLEMENTBITADDRESS: Bit → addressing_mode |
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31 | | RELATIVE: Byte → addressing_mode |
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32 | | ADDRESS11: Word11 → addressing_mode |
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33 | | ADDRESS16: Word → addressing_mode. |
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34 | |
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35 | (* to avoid expansion... *) |
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36 | nlet rec is_a (d:all_types) (A:addressing_mode) on d ≝ |
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37 | match d with |
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38 | [ reg ⇒ match A with [ REGISTER _ _ _ ⇒ true | _ ⇒ false ] |
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39 | | data ⇒ match A with [ DATA _ ⇒ true | _ ⇒ false ] |
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40 | | rel ⇒ match A with [ RELATIVE _ ⇒ true | _ ⇒ false ] |
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41 | | acc ⇒ match A with [ ACCUMULATORA ⇒ true | _ ⇒ false ] |
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42 | | direct ⇒ match A with [ DIRECT _ ⇒ true | _ ⇒ false ] |
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43 | | indirect ⇒ match A with [ INDIRECT _ ⇒ true | _ ⇒ false ]]. |
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44 | |
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45 | interpretation "Bool" 'or a b = (inclusive_disjunction a b). |
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46 | |
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47 | nlet rec is_in n (l: Vector all_types (S n)) (A:addressing_mode) on l : Bool ≝ |
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48 | match l return λm.λ_:Vector all_types m .∀K:m=S n.Bool with |
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49 | [ Empty ⇒ λK.⊥ |
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50 | | Cons m he (tl: Vector all_types m) ⇒ λ_. |
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51 | match m return λz.m = z → Bool with |
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52 | [ Z ⇒ λ_.is_a he A |
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53 | | S p ⇒ λK.is_a he A ∨ is_in p (? tl) A] (?: m=m)] (?: S n = S n). |
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54 | ##[##4: #x; ncases K; napply x ] |
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55 | //; ndestruct. |
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56 | nqed. |
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57 | |
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58 | nrecord subaddressing_mode (n) (l: Vector all_types (S n)) : Type[0] ≝ |
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59 | { subaddressing_modeel:> addressing_mode; |
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60 | subaddressing_modein: |
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61 | match is_in ? l subaddressing_modeel with [ true ⇒ (? : Prop) | false ⇒ (? : Prop) ] |
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62 | }. |
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63 | ##[ napply True | napply False ] |
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64 | nqed. |
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65 | |
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66 | ncoercion subaddressing_mode : ∀n.∀l:Vector all_types (S n).Type[0] |
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67 | ≝ subaddressing_mode on _l: Vector all_types (S ?) to Type[0]. |
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68 | |
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69 | (* |
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70 | ncoercion mk_subaddressing_mode : |
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71 | ∀n.∀l:Vector all_types (S n).∀a:addressing_mode. |
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72 | ∀p:?(*match is_in ? l a return λ_.Prop with [True ⇒ True | False ⇒ False]*).subaddressing_mode n l |
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73 | ≝ mk_subaddressing_mode on _a:addressing_mode to subaddressing_mode ? ?. |
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74 | *) |
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75 | |
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76 | ninductive Jump (A: Type[0]): Type[0] ≝ |
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77 | JC: A → Jump A |
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78 | | JNC: A → Jump A |
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79 | | JB: Bit → A → Jump A |
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80 | | JNB: Bit → A → Jump A |
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81 | | JBC: Bit → A → Jump A |
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82 | | JZ: A → Jump A |
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83 | | JNZ: A → Jump A |
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84 | | CJNE: (([acc] × [direct; data]) + [reg; indirect] × [data]) → A → Jump A |
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85 | | DJNZ: [reg ; direct] → A → Jump A |
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86 | | ADD: [acc] → [reg; direct; indirect; data] → Jump A. |
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87 | |
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88 | ndefinition xxx: Jump Nat. |
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89 | napply (DJNZ ? (mk_subaddressing_mode ?? (REGISTER [true] [true] [true]) ?) (Z: Nat)). |
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90 | napply I; |
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91 | nqed. |
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92 | |
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93 | naxiom bar: addressing_mode → Nat. |
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94 | |
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95 | ndefinition barj ≝ |
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96 | λA.λf:A → Nat.λJ:Jump A. |
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97 | match J with |
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98 | [ DJNZ arg1 arg2 ⇒ f arg2 + bar arg1 |
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99 | | _ ⇒ (Z: Nat)]. |
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100 | |
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101 | ndefinition PreInstruction ≝ λA: Type[0]. Jump A. |
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102 | |
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103 | ndefinition Instruction ≝ PreInstruction [rel]. |
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104 | |
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105 | nrecord Sigma (A: Type[0]) (T: A → Type[0]) : Type[0] ≝ { |
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106 | elem:> A; |
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107 | witness: T elem |
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108 | }. |
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109 | |
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110 | interpretation "Sigma" 'sigma T = (Sigma ? T). |
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111 | |
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112 | naxiom daemon: False. |
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113 | |
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114 | naxiom decode_register: Vector Bool (S (S (S Z))) → [reg]. |
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115 | naxiom decode_direct: Vector Bool (S (S (S Z))) → [direct]. |
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116 | |
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117 | ndefinition decode_tbl0: List ((Σn.Vector Bool n) × (Vector Bool (S (S (S Z))) → Instruction)) |
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118 | ≝ |
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119 | [mk_Cartesian ?? |
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120 | (mk_Sigma ? (λn.Vector Bool n) ? [ false; false; true; false; true]) |
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121 | (λl. |
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122 | ADD ? (mk_subaddressing_mode ? [acc] ACCUMULATORA ?) |
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123 | (mk_subaddressing_mode ? ? (decode_register l) ?)); |
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124 | mk_Cartesian ?? |
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125 | (mk_Sigma ? (λn.Vector Bool n) ? [ false; false; true; false; true]) |
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126 | (λl. |
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127 | ADD ? (mk_subaddressing_mode ? [acc] ACCUMULATORA ?) |
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128 | (mk_subaddressing_mode ? ? (decode_direct l) ?)) ]. |
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129 | ncases daemon. |
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130 | nqed. |
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131 | |
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132 | |
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133 | naxiom decode_register: List Bool → [reg]. |
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134 | naxiom decode_direct: List Bool → [direct]. |
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135 | |
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136 | ndefinition decode_tbl0: List (List Bool × (List Bool → Instruction)) |
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137 | ≝ |
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138 | [mk_Cartesian ?? |
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139 | [ false; false; true; false; true] |
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140 | (λl. |
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141 | ADD ? (mk_subaddressing_mode ? [acc] ACCUMULATORA ?) |
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142 | (mk_subaddressing_mode ? ? (decode_register l) ?)); |
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143 | mk_Cartesian ?? |
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144 | [ false; false; true; false; true] |
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145 | (λl. |
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146 | ADD ? (mk_subaddressing_mode ? [acc] ACCUMULATORA ?) |
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147 | (mk_subaddressing_mode ? ? (decode_direct l) ?)) ]. |
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148 | ncases daemon. |
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149 | nqed. |
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150 | |
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151 | |
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152 | ndefinition decode_tbl1: |
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153 | List (List Bool × Σaddr:all_types. [addr] → Instruction) |
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154 | ≝ |
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155 | [mk_Cartesian ?? |
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156 | [ false; false; true; false; true] |
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157 | (mk_Sigma ? (λaddr:all_types. [addr] → Instruction) |
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158 | reg |
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159 | (λa. |
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160 | ADD ? (mk_subaddressing_mode ? [acc] ACCUMULATORA ?) |
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161 | (mk_subaddressing_mode ? ? a ?))) ]. |
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162 | ncases daemon. |
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163 | nqed. |
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164 | |
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165 | ndefinition decode_tbl2: |
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166 | List (List Bool × Σaddr:all_types. [addr] → Instruction) |
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167 | ≝ |
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168 | [mk_Cartesian ?? |
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169 | [ false; false; true; false; false; true; false; true] |
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170 | (mk_Sigma ? (λaddr:all_types. [addr] → Instruction) |
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171 | direct |
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172 | (λa. |
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173 | ADD ? (mk_subaddressing_mode ? [acc] ACCUMULATORA ?) |
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174 | (mk_subaddressing_mode ? ? a ?))) ]. |
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175 | ncases daemon. |
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176 | nqed. |
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177 | |
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178 | ndefinition decode_tbl ≝ decode_tbl1 @ decode_tbl2. |
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179 | |
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180 | decode_addr_mode; ∀addr:all_types. List Bool → [addr]. |
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181 | |
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182 | decode ≝ |
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183 | λl:List Bit. |
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184 | List.iter |
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185 | (fun l0 addr mk_f → |
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186 | match split_prefix l l0 with |
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187 | [ None ⇒ ... |
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188 | | Some r ⇒ mk_f (decode_addr_mode r) ] |
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189 | |
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190 | ) decode_tbl |
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191 | |
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192 | encode ≝ |
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193 | |
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194 | ndefinition decode_tbl: |
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195 | List (List Bool × Σaddr:all_types. [addr] → Instruction) |
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196 | ≝ |
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197 | [mk_Cartesian ?? |
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198 | [ False; False; True; False; True] |
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199 | (mk_Sigma all_types (λaddr:all_types. [addr] → Instruction) |
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200 | reg |
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201 | (λa:subaddressing_mode ? [reg]. |
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202 | ADD ? (mk_subaddressing_mode ? [acc] ACCUMULATORA ?) |
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203 | (mk_subaddressing_mode ? ? a ?))); |
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204 | mk_Cartesian ?? |
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205 | [ False; False; True; False; False; True; False; True] |
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206 | (mk_Sigma all_types (λaddr:all_types. [addr] → Instruction) |
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207 | direct |
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208 | (λa:subaddressing_mode ? [direct]. |
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209 | ADD ? (mk_subaddressing_mode ? [acc] ACCUMULATORA ?) |
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210 | (mk_subaddressing_mode ? ? a ?))) |
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211 | ]. |
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212 | nnormalize; |
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213 | |
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214 | ]. |
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