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57  \IEEEauthorblockN{Dominic P. Mulligan}
58  \IEEEauthorblockA{Dipartimento di Scienze dell'Informazione,\\ Universit\`a di Bologna}
60  \IEEEauthorblockN{Claudio Sacerdoti Coen}
61  \IEEEauthorblockA{Dipartimento di Scienze dell'Informazione,\\ Universit\`a di Bologna}
64\title{An executable formalisation of the MCS-51 microprocessor in Matita}
66\thanks{The project CerCo acknowledges the financial support of the Future and
67Emerging Technologies (FET) programme within the Seventh Framework
68Programme for Research of the European Commission, under FET-Open grant
69number: 243881}
78We summarise the formalisation of two emulators for the MCS-51 microprocessor in O'Caml and the Matita proof assistant.
79The MCS-51 is a widely used 8-bit microprocessor, especially popular in embedded devices.
81The O'Caml emulator is intended to be `feature complete' with respect to the MCS-51 device.
82However, the Matita emulator is intended to be used as a target for a certified, complexity preserving C compiler, as part of the EU-funded CerCo project.
83As a result, not all features of the MCS-51 are formalised in the Matita emulator.
84Both the O'Caml and Matita emulators are `executable'.
85Assembly programs may be animated within Matita, producing a trace of instructions executed.
89Hardware formalisation, Matita, dependent types, CerCo
93% SECTION                                                                      %
98Formal methods aim to increase our confidence in the design and implementation of software.
99Ideally, all software should come equipped with a formal specification and a proof of correctness for the corresponding implementation.
100The majority of programs are written in high level languages and then compiled into low level ones.
101Specifications are therefore also given at a high level and correctness can be proved by reasoning on the program's source code.
102The code that is actually run is not the high level source code that we reason on, but low level code generated by the compiler.
103A few questions now arise:
106What properties are preserved during compilation?
108What properties are affected by the compilation strategy?
110To what extent can you trust your compiler in preserving those properties?
112These and other questions motivate a current `hot topic' in computer science research: \emph{compiler verification} (e.g.~\cite{chlipala:verified:2010,leroy:formal:2009}, and so on).
113So far, the field has only been focused on the first and last questions.
114Much attention has been placed on verifying compiler correctness with respect to extensional properties of programs.
115These are `easily' preserved during compilation.
117If we consider intensional properties of programs---space, time, and so forth---the situation is more complex.
118To express these properties, and reason about them, we must adopt a cost model that assigns a cost to single, or blocks, of instructions.
119A compositional cost model, assigning the same cost to all occurrences of one instruction, would be ideal.
120However, compiler optimisations are inherently non-compositional: each occurrence of a high level instruction may be compiled in a different way depending on its context.
121Therefore both the cost model and intensional specifications are affected by the compilation process.
123In the CerCo project (`Certified Complexity')~\cite{cerco:2011} we approach the problem of reasoning about intensional properties of programs as follows.
124We are currently developing a compiler that induces a cost model on high level source code.
125Costs are assigned to each block of high level instructions by considering the costs of the corresponding blocks of compiled code.
126The cost model is therefore inherently non-compositional, but has the potential to be extremely \emph{precise}, capturing a program's \emph{realistic} cost.
127That is, the compilation process is taken into account, not ignored.
128A prototype compiler, where no approximation of the cost is provided, has been developed.
129(The technical details of the cost model is explained in~\cite{amadio:certifying:2010}.)
131We believe that our approach is applicable to certifying real time programs.
132A user can certify that `deadlines' are met whilst wringing as many clock cycles from the processor---using a cost model that does not over-estimate---as possible.
134Our approach is also relevant to compiler verification and construction.
135\emph{An optimisation specified only extensionally is only half specified}; the optimisation may preserve the denotational semantics of a program, but there is no guarantee that intensional properties of the program improve.
137Another potential application is toward completeness and correctness of the compilation process in the presence of space constraints.
138A compiler could reject a source program targetting an embedded system when the size of the compiled code exceeds the available ROM size.
139Preservation of a program's semantics may only be required for those programs that do not exhaust the stack or heap.
140The statement of completeness of the compiler must take into account a realistic cost model.
142With the CerCo methodology, we assume we can assign to object code exact and realistic costs for sequential blocks of instructions.
143The WCET community has developed complex tools for bounding the worst-case execution times of sequential blocks on modern processors.
144WCET analysis takes place at the object code level.
145However, it is more convenient to reason about programs at a much higher-level of abstraction.
146Therefore, the analysis must be reflected back onto the original source code.
147This reflection process is completely `untrusted' and makes strong assumptions about the internal design and correctness of the compiler.
148For example, some WCET analysis tools, to maximise precision, require a programmer-provided strict upper bound on the number of loop iterations.
149Compiler optimizations could rearrange code in such a manner that the upper bound is no longer strict.
150The certified CerCo C compiler validates such strong assumptions, and a certified analysis tool could be obtained by combining the CerCo compiler with any certified WCET tool.
152We are interested in building a fully certified tool.
153However we are not able to build a certified WCET tool \emph{and} certified C compiler within the confines of the CerCo project.
154We therefore focus on certifying the compiler by targetting a microprocessor where complex WCET analyses are not required.
156Caching, memory effects, and advanced features such as branch prediction all have an effect on the complexity of WCET analyses (see~\cite{bate:wcet:2011,yan:wcet:2008}, and so on).
157CerCo therefore decided to focus on 8-bit microprocessors, which are still used in embedded systems.
158These have a predictable, precise cost model due to their relative paucity of features.
159Manufacturer timesheets provide \emph{exact guarantees} for the number of processor cycles each instruction will take to execute.
161We have fully formalised an executable formal semantics of a family of 8-bit Freescale microprocessors~\cite{oliboni:matita:2008}, and provided a similar executable formal semantics for the MCS-51 microprocessor.
162The latter is what we describe in this paper.
163The focus of the formalisation has been on capturing the intensional behaviour of the processor; this is not novel.
164However, the design of the MCS-51 itself has caused problems in the formalisation.
165For example, the MCS-51 has a highly unorthogonal instruction set.
166To cope with this unorthogonality, and to produce an executable specification, we rely on the dependent types of Matita, an interactive proof assistant~\cite{asperti:user:2007}.
167The manner in which we combined dependent types and coercions to handle this problem is novel.
169\paragraph*{The MCS-51}\quad
170The MCS-51 is an 8-bit microprocessor introduced by Intel in the late 1970s.
171Commonly called the 8051, in the decades since its introduction the processor has become a popular component of embedded systems.
172The processor and derivatives are still manufactured \emph{en masse} by a host of vendors.
173Surprisingly, however, there is not yet a formal model of the MCS-51.
175The 8051 is a well documented processor, with very few underspecified behaviours (almost all of these correspond to erroneous usage of the processor).
176The processor also has the support of numerous open source and commercial tools, such as compilers and emulators.
177For instance, the open source Small Device C Compiler (SDCC) recognises a dialect of C~\cite{sdcc:2010}, and other compilers for BASIC, Forth and Modula-2 are also extant.
178An open source emulator for the processor, MCU 8051 IDE, is also available~\cite{mcu8051ide:2010}.
179Both MCU 8051 IDE and SDCC were used in for validating the formalisation.
186\put(12,410){\makebox(80,0)[b]{Internal (256B)}}
190\put(12,400){\makebox(0,0)[r]{0h}}  \put(14,400){\makebox(0,0)[l]{Register bank 0}}
192\put(12,386){\makebox(0,0)[r]{8h}}  \put(14,386){\makebox(0,0)[l]{Register bank 1}}
194\put(12,372){\makebox(0,0)[r]{10h}}  \put(14,372){\makebox(0,0)[l]{Register bank 2}}
196\put(12,358){\makebox(0,0)[r]{18h}} \put(14,358){\makebox(0,0)[l]{Register bank 3}}
198\put(12,344){\makebox(0,0)[r]{20h}} \put(14,344){\makebox(0,0)[l]{Bit addressable}}
201  \put(14,309){\makebox(0,0)[l]{\quad \vdots}}
204  \put(14,263){\makebox(0,0)[l]{\quad \vdots}}
221% bit access to sfrs?
229\put(164,410){\makebox(80,0)[b]{External (64kB)}}
235\put(164,324){\makebox(80,0){Paged access}}
236  \put(164,310){\makebox(80,0){Direct/indirect}}
238  \put(164,228){\makebox(80,0){\vdots}}
239  \put(164,210){\makebox(80,0){Direct/indirect}}
241\put(264,410){\makebox(80,0)[b]{Code (64kB)}}
246  \put(264,228){\makebox(80,0){\vdots}}
247  \put(264,324){\makebox(80,0){Direct}}
248  \put(264,310){\makebox(80,0){PC relative}}
250\caption{The 8051 memory model}
254The 8051 has a relatively straightforward architecture.
255A high-level overview of the processor's memory layout, along with the ways in which different memory spaces may be addressed, is provided in Figure~\ref{fig.memory.layout}.
257Processor RAM is divided into numerous segments, with the most prominent division being between internal and (optional) external memory.
258Internal memory, commonly provided on the die itself with fast access, is composed of 256 bytes, but, in direct addressing mode, half of them are overloaded with 128 bytes of memory-mapped Special Function Registers (SFRs).
259SFRs control the operation of the processor.
260Internal RAM (IRAM) is divided again into 8 general purpose bit-addressable registers (R0--R7).
261These sit in the first 8 bytes of IRAM, though can be programmatically `shifted up' as needed.
262Bit memory, followed by a small amount of stack space, resides in the memory space immediately following the register banks.
263What remains of IRAM may be treated as general purpose memory.
264A schematic view of IRAM is also provided in Figure~\ref{fig.memory.layout}.
266External RAM (XRAM), limited to a maximum size of 64 kilobytes, is optional, and may be provided on or off chip, depending on the vendor.
267XRAM is accessed using a dedicated instruction, and requires 16 bits to address fully.
268External code memory (XCODE) is often stored as an EPROM, and limited to 64 kilobytes in size.
269However, depending on the particular processor model, a dedicated on-die read-only memory area for program code (ICODE) may be supplied.
271Memory may be addressed in numerous ways: immediate, direct, indirect, external direct and code indirect.
272As the latter two addressing modes hint, there are some restrictions enforced by the 8051, and its derivatives, on which addressing modes may be used with specific types of memory.
273For instance, the extra 128 bytes of IRAM of the 8052 cannot be addressed using indirect addressing; rather, external (in)direct addressing must be used. Moreover, some memory segments are addressed using 8-bit pointers while others require 16-bits.
275The 8051 possesses an 8-bit Arithmetic and Logic Unit (ALU), with a variety of instructions for performing arithmetic and logical operations on bits and integers.
276Two 8-bit general purpose accumulators, A and B, are provided.
278Communication with the device is handled by a UART serial port and controller.
279This can operate in numerous modes.
280Serial baud rate is determined by one of two 16-bit timers included with the 8051, which can be set to multiple modes of operation.
281(The 8052 provides an additional 16-bit timer.)
282The 8051 also provides a 4 byte bit-addressable I/O port.
284The programmer may take advantage of an interrupt mechanism.
285This is especially useful when dealing with I/O involving the serial device, as an interrupt can be set when a whole character is sent or received via the UART.
287Interrupts immediately halt the flow of execution of the processor, and cause the program counter to jump to a fixed address, where the requisite interrupt handler is stored.
288However, interrupts may be set to one of two priorities: low and high.
289The interrupt handler of an interrupt with high priority is executed ahead of the interrupt handler of an interrupt of lower priority, interrupting a currently executing handler of lower priority, if necessary.
291The 8051 has interrupts disabled by default.
292The programmer is free to handle serial input and output manually, by poking serial flags in the SFRs.
293`Exceptional circumstances' that would otherwise trigger an interrupt on more modern processors, (e.g. division by zero) are also signalled by setting flags.
299%\caption{Schematic view of 8051 IRAM layout}
303\paragraph*{Overview of paper}\quad
304In Section~\ref{} we discuss design issues in the development of the formalisation.
305In Section~\ref{sect.validation} we discuss validation of the emulator to ensure that what we formalised was an accurate model of an MCS-51 series microprocessor.
306In Section~\ref{} we describe previous work, with an eye toward describing its relation with the work described herein.
307In Section~\ref{sect.conclusions} we conclude.
310% SECTION                                                                      %
312\section{Design issues in the formalisation}
315We implemented two emulators, one in O'Caml and one in Matita.
316The O'Caml emulator is intended to be `feature complete' with respect to the MCS-51 device.
317However, the Matita emulator is intended to be used as a target for a certified, complexity preserving C compiler.
318As a result, not all features of the MCS-51 are formalised in the Matita emulator.
320We designed the O'Caml emulator to be as efficient as possible, under the constraint that it would be eventually translated into Matita.
321One performance drain in the O'Caml emulator is the use of purely functional map datastructures to represent memory spaces, used to maintain the close correspondence between the Matita and O'Caml emulators.
323Matita~\cite{asperti:user:2007} is a proof assistant based on the Calculus of Coinductive constructions, similar to Coq.
324As a programming language, Matita corresponds to the functional fragment of O'Caml extended with dependent types.
325Matita also features a rich higher-order logic for reasoning about programs.
326Unlike O'Caml, all recursive functions must be structurally recursive, and therefore total.
328We box Matita code to distinguish it from O'Caml code.
329In Matita `\texttt{$?$}' and  `\texttt{$\ldots$}' are arguments to be inferred automatically.
331A full account of the formalisation can be found in~\cite{cerco-report-code:2011}.
332All source code is available from the CerCo project website~\cite{cerco-report-code:2011}.
335% SECTION                                                                      %
337\subsection{Representation of bytes, words, etc.}
345type 'a vect = bit list
346type nibble = [`Sixteen] vect
347type byte = [`Eight] vect
348let split_word w = split_nth 4 w
349let split_byte b = split_nth 2 b
356type 'a vect
357type word = [`Sixteen] vect
358type byte = [`Eight] vect
359val split_word: word -> byte * word
360val split_byte: byte -> nibble * nibble
363\caption{Sample of O'Caml implementation and interface for bitvectors module}
367The formalization of MCS-51 must deal with bytes (8-bits), words (16-bits), and also more exoteric quantities (7, 3 and 9-bits).
368To avoid difficult-to-trace size mismatch bugs, we represented all quantities using bitvectors, i.e. fixed length vectors of booleans.
369In the O'Caml emulator, we `faked' bitvectors using phantom types~\cite{leijen:domain:1999} implemented with polymorphic variants~\cite{garrigue:programming:1998}, as in Figure~\ref{fig.ocaml.implementation.bitvectors}.
370From within the bitvector module (top) bitvectors are just lists of bits and no guarantee is provided on sizes.
371However, the module's interface (bottom) enforces size invariants in the rest of the code.
373In Matita, we are able to use the full power of dependent types to always work with vectors of a known size:
375inductive Vector (A: Type[0]): nat $\rightarrow$ Type[0] ≝
376  VEmpty: Vector A O
377| VCons: $\forall$n: nat. A $\rightarrow$ Vector A n $\rightarrow$ Vector A (S n).
379\texttt{BitVector} is a specialization of \texttt{Vector} to \texttt{bool}.
380We may use Matita's type system to provide precise typings for functions that are polymorphic in the size without code duplication:
382let rec split (A: Type[0]) (m,n: nat) on m:
383  Vector A (m+n) $\rightarrow$ (Vector A m)$\times$(Vector A n) := ...
387% SECTION                                                                      %
389\subsection{Representing memory}
392The MCS-51 has numerous disjoint memory spaces addressed by differently sized pointers.
393In the O'Caml implementation, we use a map data structure (from the standard library) for each space.
394In Matita, we exploited dependent types to design a data structure which enforced the correspondence between the size of pointer and the size of the memory space.
395Further, we assumed that large swathes of memory would often be uninitialized (an assumption on the behaviour of the programmer, not the processor!)
397We picked a modified form of trie of fixed height $h$.
398Paths are represented by bitvectors (already used in the implementation for addresses and registers) of length $h$:
400inductive BitVectorTrie(A: Type[0]):nat $\rightarrow$ Type[0] :=
401  Leaf: A $\rightarrow$ BitVectorTrie A 0
402| Node: ∀n. BitVectorTrie A n $\rightarrow$ BitVectorTrie A n $\rightarrow$
403  BitVectorTrie A (S n)
404| Stub: ∀n. BitVectorTrie A n.
406\texttt{Stub} is a constructor that can appear at any point in a trie.
407It represents `uninitialized data'.
408Performing a lookup in memory is now straight-forward.
409The only subtlety over normal trie lookup is how we handle \texttt{Stub}.
410We traverse a path, and upon encountering \texttt{Stub}, we return a default value.
411All manufacturer data sheets that we consulted were silent on the subject of what should be returned if we attempt to access uninitialized memory.
412We defaulted to simply returning zero, though our \texttt{lookup} function is parametric in this choice.
413We believe that this is reasonable, as SDCC for instance generates code which first `zeroes' memory in a preamble before executing the program proper.
414This is in line with the C standard, which guarantees that all global variables will be zero initialized piecewise.
416\texttt{BitVectorTrie} and \texttt{Vector}, and related functions, can be used in the formalisation of other microprocessors.
419% SECTION                                                                      %
421\subsection{Labels and pseudoinstructions}
424Aside from implementing the core MCS-51 instruction set, we also provided \emph{pseudoinstructions}, \emph{labels} and \emph{cost labels}.
425The purpose of \emph{cost labels} will be explained in Subsection~\ref{subsect.computation.cost.traces}.
427Introducing pseudoinstructions had the effect of simplifying a C compiler---another component of the CerCo project---that was being implemented in parallel with our implementation.
428To see why, consider the fact that the MCS-51's instruction set has numerous instructions for unconditional and conditional jumps to memory locations.
429For instance, the instructions \texttt{AJMP}, \texttt{JMP} and \texttt{LJMP} all perform unconditional jumps.
430However, these instructions differ in how large the maximum size of the offset of the jump to be performed can be.
431Further, all jump instructions require a concrete memory address---to jump to---to be specified.
432Compilers that support separate compilation cannot directly compute these offsets and select the appropriate jump instructions.
433These operations are also burdensome for compilers that do not do separate compilation and are handled by assemblers.
434We followed suit.
436While introducing pseudoinstructions, we also introduced labels for locations to jump to, and for global data.
437To specify global data via labels, we introduced a preamble before the program where labels and the size of reserved space for data is stored.
438A pseudoinstruction \texttt{Mov} moves (16-bit) data stored at a label into the MCS-51's 16-bit register, \texttt{DPTR}.
439(This register is used for indirect addressing of data stored in external memory.)
441The pseudoinstructions and labels induce an assembly language similar to that of SDCC's.
442All pseudoinstructions and labels are `assembled away' prior to program execution.
443Jumps are computed in two stages.
444A map associating memory addresses to labels is built, before replacing pseudojumps with concrete jumps to the correct address.
445The algorithm currently implemented does not try to minimize object code size by picking the shortest possible jump instruction.
446A better algorithm is left for future work.
449% SECTION                                                                      %
451\subsection{Anatomy of the (Matita) emulator}
454The Matita emulator's internal state is a record:
456record Status: Type[0] := {
457  code_memory: BitVectorTrie Byte 16;
458  low_internal_ram: BitVectorTrie Byte 7;
459  high_internal_ram: BitVectorTrie Byte 7;
460  external_ram: BitVectorTrie Byte 16;
461  program_counter: Word;
462  special_function_registers_8051: Vector Byte 19;
463  ... }.
465This record encapsulates the current memory contents, the program counter, the state of the current SFRs, and so on.
467Here the MCS-51's memory model is implemented using four disjoint memory spaces, plus SFRs.
468From the programmer's point of view, what \emph{really} matters are the addressing modes that are in a many-to-many relationship with the spaces.
469\texttt{DIRECT} addressing can be used to address either lower IRAM (if the first bit is 0) or the SFRs (if the first bit is 1), for instance.
470That's why DIRECT uses 8-bit addresses but pointers to lower IRAM only use 7 bits.
471The complexity of the memory model is captured in a pair of functions, \texttt{get\_arg\_XX} and \texttt{set\_arg\_XX}, that `get' and `set' data of size \texttt{XX} from memory.
473%Overlapping, and checking which addressing modes can be used to address particular memory spaces, is handled through numerous \texttt{get\_arg\_XX} and \texttt{set\_arg\_XX} (for 1, 8 and 16 bits) functions.
475Both the Matita and O'Caml emulators follow the classic `fetch-decode-execute' model of processor operation.
476The next instruction to be processed, indexed by the program counter, is fetched from code memory with \texttt{fetch}.
477An updated program counter, along with its concrete cost in processor cycles, is also returned.
478These costs are taken from a Siemens Semiconductor Group data sheet for the MCS-51~\cite{siemens:2011}, and will likely vary between particular implementations.
480definition fetch: BitVectorTrie Byte 16 $\rightarrow$ Word $\rightarrow$
481  instruction $\times$ Word $\times$ nat
483Instruction are assembled to bit encodings by \texttt{assembly1}:
485definition assembly1: instruction $\rightarrow$ list Byte
487An assembly program---comprising a preamble containing global data and a list of pseudoinstructions---is assembled using \texttt{assembly}.
488Pseudoinstructions and labels are eliminated in favour of instructions from the MCS-51 instruction set.
489A map associating memory locations and cost labels (see Subsection~\ref{subsect.computation.cost.traces}) is produced.
491definition assembly: assembly_program $\rightarrow$
492  option (list Byte $\times$ (BitVectorTrie String 16))
494A single fetch-decode-execute cycle is performed by \texttt{execute\_1}:
496definition execute_1: Status $\rightarrow$ Status
498The \texttt{execute} functions performs a fixed number of cycles by iterating
501let rec execute (n: nat) (s: Status): Status := ...
503This differs from the O'Caml emulator, which executed a program indefinitely.
504A callback function was also accepted as an argument, which `witnessed' the execution as it happened.
505Due to Matita's termination requirement, \texttt{execute} cannot execute a program indefinitely.
506An alternative would be to produce an infinite stream of statuses representing an execution trace using Matita's co-inductive types.
509% SECTION                                                                      %
511\subsection{Instruction set unorthogonality}
514A peculiarity of the MCS-51 is its unorthogonal instruction set; \texttt{MOV} can be invoked using one of 16 combinations of addressing modes out of a total of 361, for instance.
516% Show example of pattern matching with polymorphic variants
518Such unorthogonality in the instruction set was handled with the use of polymorphic variants in O'Caml~\cite{garrigue:programming:1998}.
519For instance, we introduced types corresponding to each addressing mode:
521type direct = [ `DIRECT of byte ]
522type indirect = [ `INDIRECT of bit ]
525Which were then combined in the inductive datatype for assembly preinstructions using the union operator `$|$':
527type 'addr preinstruction =
528[ `ADD of acc * [ reg | direct | indirect | data ]
530| `MOV of
531   (acc * [ reg| direct | indirect | data ],
532   [ reg | indirect ] * [ acc | direct | data ],
533   direct * [ acc | reg | direct | indirect | data ],
534   dptr * data16,
535   carry * bit,
536   bit * carry
537   ) union6
540Here, \texttt{union6} is a disjoint union type, defined as follows:
542type ('a,'b,'c,'d,'e,'f) union6 =
543  [ `U1 of 'a | ... | `U6 of 'f ]
545The types \texttt{union2}, \texttt{union3} and \texttt{union6} sufficed.
547This polymorphic variant machinery worked well: it introduced a certain level of type safety (for instance, the type of \texttt{MOV} above guarantees it cannot be invoked with arguments in the \texttt{carry} and \texttt{data16} addressing modes, respectively), and also allowed us to pattern match against instructions, when necessary.
548However, this polymorphic variant machinery is \emph{not} present in Matita.
549We needed some way to produce the same effect, which Matita supported.
550We used dependent types.
552We provided an inductive data type representing all addressing modes, a type that functions will pattern match against:
554inductive addressing_mode: Type[0] :=
555  DIRECT: Byte $\rightarrow$ addressing_mode
556| INDIRECT: Bit $\rightarrow$ addressing_mode
559We also wished to express in the type of functions the \emph{impossibility} of pattern matching against certain constructors.
560In order to do this, we introduced an inductive type of addressing mode `tags'.
561The constructors of \texttt{addressing\_mode\_tag} are in one-to-one correspondence with the constructors of \texttt{addressing\_mode}:
563inductive addressing_mode_tag : Type[0] :=
564  direct: addressing_mode_tag
565| indirect: addressing_mode_tag
568The \texttt{is\_a} function checks if an \texttt{addressing\_mode} matches an \texttt{addressing\_mode\_tag}:
570definition is_a :=
571  $\lambda$d: addressing_mode_tag. $\lambda$A: addressing_mode.
572match d with
573[ direct $\Rightarrow$
574  match A with [ DIRECT _ $\Rightarrow$ true | _ $\Rightarrow$ false ]
575| indirect $\Rightarrow$
576  match A with [ INDIRECT _ $\Rightarrow$ true | _ $\Rightarrow$ false ]
579The \texttt{is\_in} function checks if an \texttt{addressing\_mode} matches a set of tags represented as a vector.
580It simply extends the \texttt{is\_a} function in the obvious manner.
582A \texttt{subaddressing\_mode} is an \emph{ad hoc} non-empty $\Sigma$-type of \texttt{addressing\_mode}s in a set of tags:
584record subaddressing_mode
585  (n: nat)
586  (l: Vector addressing_mode_tag (S n)): Type[0] :=
588  subaddressing_modeel :> addressing_mode;
589  subaddressing_modein:
590    bool_to_Prop (is_in $\ldots$ l subaddressing_modeel)
593An implicit coercion~\cite{luo:coercive:1999} is provided to promote vectors of tags (denoted with $\llbracket - \rrbracket$) to the corresponding \texttt{subaddressing\_mode} so that we can use a syntax close to that of O'Caml to specify \texttt{preinstruction}s:
595inductive preinstruction (A: Type[0]): Type[0] ≝
596  ADD: $\llbracket$acc_a$\rrbracket$ $\rightarrow$ $\llbracket$register;direct;indirect;data$\rrbracket$ $\rightarrow$
597       preinstruction A
598| ADDC: $\llbracket$acc_a$\rrbracket$ $\rightarrow$ $\llbracket$register;direct;indirect;data$\rrbracket$ $\rightarrow$
599        preinstruction A
602The constructor \texttt{ADD} expects two parameters, the first being the accumulator A (\texttt{acc\_a}), the second being a register, direct, indirect or data addressing mode.
604% One of these coercions opens up a proof obligation which needs discussing
605% Have lemmas proving that if an element is a member of a sub, then it is a member of a superlist, and so on
606Finally, type coercions from \texttt{addressing\_mode} to \texttt{subaddressing\_mode} and from \texttt{Vector addressing\_mode\_tag} to \texttt{Type$\lbrack0\rbrack$}, are required.
607The first opens a proof obligation wherein we must prove that the provided value is in the admissible set, simulating PVS subset types~\cite{shankar:principles:1999}.
608%PVS introduced subset types, and these later featured in Coq as part of Russell~\cite{sozeau:subset:2006}.
609%All coercions in Matita can open proof obligations.
611Proof obligations require us to state and prove a few auxilliary lemmas related to the transitivity of subtyping.
612For instance, an \texttt{addressing\_mode} that belongs to an allowed set also belongs to any one of its supersets.
613At the moment, Matita's automation exploits these lemmas to completely solve all the proof obligations opened in the formalisation.
614The \texttt{execute\_1} function, for instance, opens over 200 proof obligations during type checking.
616The machinery just described allows us to restrict the set of \texttt{addressing\_mode}s expected by a function and use this information during pattern matching.
617This allows us to skip impossible cases.
618For instance, consider \texttt{set\_arg\_16}, which expects only a \texttt{DPTR}:
620definition set_arg_16:
621  Status $\rightarrow$ Word $\rightarrow$ $\llbracket$dptr$\rrbracket$ $\rightarrow$ Status := $~\lambda$s, v, a.
622match a return
623   $\lambda$x. bool_to_Prop (is_in ? $\llbracket$dptr$\rrbracket$ x) $\rightarrow$ ? with
624  [ DPTR $\Rightarrow$ $\lambda$_: True.
625    let $\langle$bu, bl$\rangle$ := split $\ldots$ eight eight v in
626    let status := set_8051_sfr s SFR_DPH bu in
627    let status := set_8051_sfr status SFR_DPL bl in
628      status
629  | _ $\Rightarrow$ $\lambda$_: False. $\bot$
630  ] $~$(subaddressing_modein $\ldots$ a).
632We give a proof (the expression \texttt{(subaddressing\_modein} $\ldots$ \texttt{a)}) that the argument $a$ is in the set $\llbracket$ \texttt{dptr} $\rrbracket$ to the \texttt{match} expression.
633In every case but \texttt{DPTR}, the proof is a proof of \texttt{False}, and the system opens a proof obligation $\bot$ that can be discarded using \emph{ex falso}.
634Attempting to match against a disallowed addressing mode (replacing \texttt{False} with \texttt{True} in the branch) produces a type error.
636We tried other dependently and non-dependently typed solutions before settling on this approach.
637As we need a large number of different combinations of addressing modes to describe the instruction set, it is infeasible to declare a datatype for each one of these combinations.
638The current solution is closest to the corresponding O'Caml code, to the point that the translation from O'Caml to Matita is almost syntactical.
639% We would like to investigate the possibility of changing the code extraction procedure of Matita so that it recognises this programming pattern and outputs O'Caml code using polymorphic variants.
641% Talk about extraction to O'Caml code, which hopefully will allow us to extract back to using polymorphic variants, or when extracting vectors we could extract using phantom types
642% Discuss alternative approaches, i.e. Sigma types to piece together smaller types into larger ones, as opposed to using a predicate to `cut out' pieces of a larger type, which is what we did
645% SECTION                                                                      %
647\subsection{I/O and timers}
650% `Real clock' for I/O and timers
651The O'Caml emulator has code for handling timers, asynchronous I/O and interrupts (these are not in the Matita emulator as they are not relevant to CerCo).
652All three of these features interact with each other in subtle ways.
653Interrupts can `fire' when an input is detected on the processor's UART port, and, in certain modes, timers reset when a high signal is detected on one of the MCS-51's communication pins.
655To accurately model timers and I/O, we add an unbounded integral field \texttt{clock} to the central \texttt{status} record.
656This field is only logical, since it does not represent any quantity stored in the physical processor, and is used to keep track of the current `processor time'.
657Before every execution step, \texttt{clock} is incremented by the number of processor cycles that the instruction just fetched will take to execute.
658The emulator executes the instruction then the code implementing timers and I/O (it isn't specified by the data sheets if I/O is handled at the beginning or the end of each cycle.)
659To model I/O, we store in \texttt{status} a \emph{continuation} which is a description of the behaviour of the environment:
661type line =
662[ `P1 of byte | `P3 of byte
663| `SerialBuff of
664   [ `Eight of byte
665   | `Nine of BitVectors.bit * byte ]  ]
666type continuation =
667[`In of time * line *
668  epsilon * continuation] option *
669[`Out of (time -> line -> time * continuation)]
671The second projection of the continuation $k$ describes how the environment will react to an output event performed in the future by the processor.
672Suppose $\pi_2(k)(\tau,o) = \langle \tau',k' \rangle$.
673If the emulator at time $\tau$ starts an asynchronous output $o$ either on the P1 or P3 output lines, or on the UART, then the environment will receive the output at time $\tau'$.
674Moreover \texttt{status} is immediately updated with the continuation $k'$.
676Further, if $\pi_1(k) = \mathtt{Some}~\langle \tau',i,\epsilon,k'\rangle$, then at time $\tau'$ the environment will send the asynchronous input $i$ to the emulator and \texttt{status} is updated with the continuation $k'$.
677This input is visible to the emulator only at time $\tau' + \epsilon$.
679The time required to perform an I/O operation is partially specified in the data sheets of the UART module.
680This computation is complex so we prefer to abstract over it.
681We leave the computation of the delay time to the environment.
683We use only the P1 and P3 lines despite the MCS-51 having~4 output lines, P0--P3.
684This is because P0 and P2 become inoperable if XRAM is present (we assume it is).
686The UART port can work in several modes, depending on the how the SFRs are set.
687In an asyncrhonous mode, the UART transmits 8 bits at a time, using a ninth line for synchronisation.
688In a synchronous mode the ninth line is used to transmit an additional bit.
689All UART modes are formalised.
692% SECTION                                                                      %
694\subsection{Computation of cost traces}
697As mentioned in Subsection~\ref{subsect.labels.pseudoinstructions} we introduced a notion of \emph{cost label}.
698Cost labels are inserted by the prototype C compiler at specific locations in the object code.
700Cost labels are used to calculate a precise costing for a program by marking the start of basic blocks.
701During the assembly phase, where labels and pseudoinstructions are eliminated, a map is generated associating cost labels with memory locations.
702This map is later used in a separate analysis which computes the cost of a program by traversing through a program, fetching one instruction at a time, and computing the cost of blocks.
703When targetting more complex processors, this simple analysis will need to be replaced by a more sophisticated WCET analysis.
704These block costings are stored in another map, and will later be passed back to the prototype compiler.
707% SECTION                                                                      %
715%08: mov 81 #07
717% Processor status:                               
719%   ACC: 0   B: 0   PSW: 0
720%    with flags set as:
721%     CY: false    AC: false   FO: false   RS1: false
722%     RS0: false   OV: false   UD: false   P: false
723%   SP: 7   IP: 0   PC: 8   DPL: 0   DPH: 0   SCON: 0
724%   SBUF: 0   TMOD: 0   TCON: 0
725%   Registers:                                   
726%    R0: 0   R1: 0   R2: 0   R3: 0
727%    R4: 0   R5: 0   R6: 0   R7: 0
730%\caption{An example snippet from an emulator execution trace}
734We attempted to ensure that what we have formalised is an accurate model of the MCS-51 microprocessor.
736We made use of multiple data sheets, each from a different manufacturer.
737This helped us triangulate errors in the specification of the processor's instruction set, and its behaviour, for instance, in a data sheet from Philips Semiconductor.
739The O'Caml emulator was especially useful for validation purposes.
740We wrote a module for parsing and loading Intel HEX format files.
741Intel HEX is a standard format that all compilers targetting the MCS-51, and similar processors, produce.
742It is essentially a snapshot of the processor's code memory in compressed form.
743Using this we were able to compile C programs with SDCC and load the resulting program directly into the emulator's code memory, ready for execution.
744Further, we can produce a HEX file from the emulator's code memory for loading into third party tools.
745After each step of execution, we can print out both the instruction that had been executed and a snapshot of the processor's state, including all flags and register contents.
746These traces were useful in spotting anything that was `obviously' wrong with the execution of the program.
748We further used MCU 8051 IDE as a reference, which allows a user to step through an assembly program one instruction at a time.
749With these execution traces, we could step through a compiled program in MCU 8051 IDE and compare the resulting execution trace with the trace produced by our emulator.
751We partially validated the assembler by proving in Matita that on all defined opcodes the \texttt{assembly\_1} and \texttt{fetch} functions are inverse.
753The Matita formalisation was largely copied from the O'Caml source code apart from the changes already mentioned.
754As the Matita emulator is executable we could perform further validation by comparing the trace of a program's execution in the Matita and O'Caml emulators.
757% SECTION                                                                      %
759\section{Related work}
761A large body of literature on the formalisation of microprocessors exists.
762The majority of it deals with proving correctness of implementations of microprocessors at the microcode or gate level, with many considering `cycle accurate' models.
763We are interested in providing a precise specification of the behaviour of the microprocessor in order to prove the correctness of a compiler which will target the processor.
764In particular, we are interested in intensional properties of the processor; precise timings of instruction execution in clock cycles.
765Moreover, in addition to formalising the interface of an MCS-51 processor, we have also built a complete MCS-51 ecosystem: UART, I/O lines, and hardware timers, complete with an assembler.
767Work closely related to our own can be found in~\cite{fox:trustworthy:2010}.
768Here, the authors describe the formalisation, in HOL4, of the ARMv7 instruction set architecture.
769They further point to an excellent list of references to related work in the literature.
770This formalisation also considers the machine code level, opposed to their formalisation, which only considering an abstract assembly language.
771Instruction decoding is explicitly modeled inside HOL4's logic.
772We go further in also providing an assembly language, complete with assembler, to translate instructions and pseudoinstruction into machine code.
774Further, in~\cite{fox:trustworthy:2010} the authors validated their formalisation by using development boards and random testing.
775We currently rely on non-exhaustive testing against a third party emulator.
776We recognise the importance of this exhaustive testing, but currently leave it for future work.
778Executability is another key difference between our work and that of~\cite{fox:trustworthy:2010}.
779Our formalisation is executable: applying the emulation function to an input state eventually reduces to an output state.
780This is because Matita is based on a logic, CIC, which internalizes conversion.
781In~\cite{fox:trustworthy:2010} the authors provide an automation layer to derive single step theorems: if the processor is in a state that satisfies some preconditions, then after execution of an instruction it will reside in a state satisfying some postconditions.
782We will not need single step theorems of this form to prove properties of the assembly code.
784Our main difficulties resided in the non-uniformity of an old 8-bit architecture, in terms of the instruction set, addressing modes and memory models.
785In contrast, the various ARM instruction sets and memory models are relatively uniform.
787Two close projects to CerCo are CompCert~\cite{leroy:formally:2009} and the CLI Stack.
788CompCert concerns the certification of a C compiler and includes a formalisation in Coq of a subset of PowerPC.
789The CLI Stack consists of the design and verification of a whole chain of artifacts including a 32-bit microprocessor, the Piton assembler and two compilers for high-level languages.
790Like CerCo, the CLI Stack compilers gave the cost of high-level instructions in processor cycles.
791However, unlike CerCo, both the CLI Stack high-level languages ($\mu$Gypsy and Nqthm Lisp) and FM9001 microprocessor were not commercial products, but designs created for the purpose of verification (see~\cite{moore:grand:2005}).
793The CompCert C compiler is extracted to O'Caml using Coq's code extraction facility.
794Many other formalised emulators/compilers have also been extracted from proof assistants using similar technology (e.g. see~\cite{blanqui:designing:2010}).
795We aim to make use of a similar code extraction facility in Matita, but only if the extracted code exhibits the same degree of type safety, provided by polymorphic variants, and human readability that the O'Caml emulator posseses.
796This is because we aim to use the emulator as a library for non-certified software written directly in O'Caml.
797How we have used Matita's dependent types to handle the instruction set (Subsection~\ref{subsect.instruction.set.unorthogonality}) could enable code extraction to make use of polymorphic variants.
798Using Coq's current code extraction algorithm we could write assembly programs that would generate runtime errors when emulated.
799We leave this for future work.
801Despite the apparent similarity between CerCo and CompCert, the two formalisations do not have much in common.
802First, CompCert provides a formalisation at the assembly level (no instruction decoding).
803This impels them to trust an unformalised assembler and linker, whereas we provide our own.
804Our formalisation is \emph{directly} executable, while the one in CompCert only provides a relation that describes execution.
805In CompCert I/O is only described as a synchronous external function call and there is no I/O at the processor level.
806Moreover an idealized abstract and uniform memory model is assumed, while we take into account the complicated overlapping memory model of the MCS-51 architecture.
807Finally, 82 instructions of the more than 200 offered by the processor are formalised in CompCert, and the assembly language is augmented with macro instructions that are turned into `real' instructions only during communication with the external assembler.
808Even from a technical level the two formalisations differ: we tried to exploit dependent types whilst CompCert largely sticks to a non-dependent fragment of Coq.
810In~\cite{atkey:coqjvm:2007} an executable specification of the Java Virtual Machine, using dependent types, is presented.
811As we do, dependent types there are used to remove spurious partiality from the model.
812They also lower the need for over-specifying the behaviour of the processor in impossible cases.
813Our use of dependent types will also help to maintain invariants when we prove the correctness of the CerCo prototype C compiler.
815Finally~\cite{sarkar:semantics:2009} provides an executable semantics for x86-CC multiprocessor machine code.
816This machine code exhibits a degree of non-uniformity similar to the MCS-51.
817Only a small subset of the instruction set is considered, and they over-approximate the possibilities of unorthogonality of the instruction set, largely dodging the problems we had to face.
819Further, it seems that the definition of the decode function is potentially error prone.
820A domain specific language of patterns is formalised in HOL4, similar to the specification language of the x86 instruction set found in manufacturer's data sheets.
821A decode function is implemented by copying lines from data sheets into the proof script, which are then partially evaluated to obtain a compiler.
822We are currently considering implementing a similar domain specific language in Matita.
825% SECTION                                                                      %
830In CerCo, we are interested in the certification of a compiler for C that induces a precise cost model on the source code.
831Our cost model assigns costs to blocks of instructions by tracing the way that blocks are compiled, and by computing exact costs on generated machine language.
832To perform this accurately, we have provided an executable semantics for the MCS-51 family of processors.
833An O'Caml and Matita formalisation was provided, and both capture the exact timings of the MCS-51 (according to a Siemen's data sheet).
834The O'Caml formalisation also considers timers and I/O.
835Adding support for I/O and timers in Matita is on-going work that will not present any problem, and was delayed only because the addition is not immediately useful for the formalisation of the CerCo compiler.
837The formalisation is done at machine level and not at assembly level; we also formalise fetching and decoding.
838We separately provide an assembly language, enhanched with labels and pseudoinstructions, and an assembler from this language to machine code.
839This assembly language is similar to those found in `industrial strength' compilers, such as SDCC.
840We introduce cost labels in the machine language to relate the data flow of the assembly program to that of the C source language, in order to associate costs to the C program.
841For the O'Caml version, we provide a parser and pretty printer from code memory to Intel HEX.
842Hence we can perform testing on programs compiled using any free or commercial compiler.
844Our main difficulty in formalising the MCS-51 was the unorthogonality of its memory model and instruction set.
845These problems are handled in O'Caml by using language features like polymorphic variants and phantom types, simulating Generalized Abstract Data Types~\cite{xi:guarded:2003}.
846Importantly, we searched for a manner of using dependent types to recover the same flexibility, reduce spurious partiality, and grant invariants that will be later useful in other formalisations in CerCo.
848The formalisation has been partially verified by computing execution traces on selected programs and comparing them with an existing emulator.
849All instructions have been tested at least once, but we have not yet pushed testing further, for example with random testing or by using development boards.
850I/O in particular has not been tested yet, and it is currently unclear how to provide exhaustive testing in the presence of I/O.
851Finally, we are aware of having over-specified the processor in several places, by fixing a behaviour hopefully consistent with the real machine, where manufacturer data sheets are ambiguous or under-specified.
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