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56\author{
57  \IEEEauthorblockN{Dominic P. Mulligan}
58  \IEEEauthorblockA{Dipartimento di Scienze dell'Informazione,\\ Universit\`a di Bologna}
59\and
60  \IEEEauthorblockN{Claudio Sacerdoti Coen}
61  \IEEEauthorblockA{Dipartimento di Scienze dell'Informazione,\\ Universit\`a di Bologna}
62}
63
64\title{An executable formalisation of the MCS-51 microprocessor in Matita}
65
66\thanks{The project CerCo acknowledges the financial support of the Future and
67Emerging Technologies (FET) programme within the Seventh Framework
68Programme for Research of the European Commission, under FET-Open grant
69number: 243881}
70
71\bibliographystyle{plain}
72
73\begin{document}
74
75\maketitle
76
77\begin{abstract}
78We summarise the formalisation of two emulators for the MCS-51 microprocessor in O'Caml and the Matita proof assistant.
79The MCS-51 is a widely used 8-bit microprocessor, especially popular in embedded devices.
80
81The O'Caml emulator is intended to be `feature complete' with respect to the MCS-51 device.
82However, the Matita emulator is intended to be used as a target for a certified, complexity preserving C compiler, as part of the EU-funded CerCo project.
83As a result, not all features of the MCS-51 are formalised in the Matita emulator.
84
85%The formalisation proceeded in two stages, first implementing an O'Caml prototype, for quickly `ironing out' bugs, and then porting the O'Caml emulator to Matita.
86%Though mostly straight-forward, this porting presented multiple problems.
87%Of particular interest is how the unorthoganality of the MSC-51's instruction set is handled.
88%In O'Caml, this was handled with polymorphic variants.
89%In Matita, we achieved the same effect with a non-standard use of dependent types.
90
91Both the O'Caml and Matita emulators are `executable'.
92Assembly programs may be animated within Matita, producing a trace of instructions executed.
93\end{abstract}
94
95\begin{IEEEkeywords}
96Hardware formalisation, Matita, dependent types, CerCo
97\end{IEEEkeywords}
98
99%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
100% SECTION                                                                      %
101%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
102\section{Introduction}
103\label{sect.introduction}
104
105Formal methods aim to increase our confidence in the design and implementation of software.
106Ideally, all software should come equipped with a formal specification and a proof of correctness for the corresponding implementation.
107The majority of programs are written in high level languages and then compiled into low level ones.
108Specifications are therefore also given at a high level and correctness can be proved by reasoning on the program's source code.
109The code that is actually run, however, is not the high level source code that we reason on, but low level code generated by the compiler.
110A few questions now arise:
111\begin{itemize*}
112\item
113What properties are preserved during compilation?
114\item
115What properties are affected by the compilation strategy?
116\item
117To what extent can you trust your compiler in preserving those properties?
118\end{itemize*}
119These questions, and others like them, motivate a current `hot topic' in computer science research: \emph{compiler verification} (for instance~\cite{chlipala:verified:2010,leroy:formal:2009}, and many others).
120So far, the field has only been focused on the first and last questions.
121Much attention has been placed on verifying compiler correctness with respect to extensional properties of programs.
122These are `easily' preserved during compilation.
123
124If we consider intensional properties of programs---space, time, and so forth---the situation is more complex.
125To express these properties, and reason about them, we must adopt a cost model that assigns a cost to single, or blocks, of instructions.
126A compositional cost model, assigning the same cost to all occurrences of one instruction, would be ideal.
127However, compiler optimisations are inherently non-compositional: each occurrence of a high level instruction may be compiled in a different way depending on its context.
128Therefore both the cost model and intensional specifications are affected by the compilation process.
129
130In the CerCo project (`Certified Complexity')~\cite{cerco:2011} we approach the problem of reasoning about intensional properties of programs as follows.
131We are currently developing a compiler that induces a cost model on high level source code.
132Costs are assigned to each block of high level instructions by considering the costs of the corresponding blocks of compiled code.
133The cost model is therefore inherently non-compositional, but has the potential to be extremely \emph{precise}, capturing a program's \emph{realistic} cost.
134That is, the compilation process is taken into account, not ignored.
135A prototype compiler, where no approximation of the cost is provided, has been developed.
136(The technical details of the cost model is explained in~\cite{amadio:certifying:2010}.)
137
138We believe that our approach is applicable to certifying real time programs.
139A user can certify that `deadlines' are met whilst wringing as many clock cycles from the processor---using a cost model that does not over-estimate---as possible.
140
141We also see our approach as being relevant to compiler verification (and construction).
142\emph{An optimisation specified only extensionally is only half specified}.
143Though the optimisation may preserve the denotational semantics of a program, there is no guarantee that intensional properties of the program improve.
144
145Another potential application is toward completeness and correctness of the compilation process in the presence of space constraints.
146A compiler could reject a source program targetting an embedded system when the size of the compiled code exceeds the available ROM size.
147Preservation of a program's semantics may only be required for those programs that do not exhaust the stack or heap.
148The statement of completeness of the compiler must therefore take into account a realistic cost model.
149
150With the CerCo methodology, we assume we can assign to object code exact and realistic costs for sequential blocks of instructions.
151The WCET community has developed complex tools for bounding the worst-case execution times of sequential blocks on modern processors.
152WCET analysis takes place at the object code level.
153However, it is more convenient to reason about programs at a much higher-level of abstraction.
154Therefore, the analysis must be reflected back onto the original source code.
155This reflection process is completely `untrusted' and makes strong assumptions about the internal design and correctness of the compiler.
156For example, some WCET analysis tools, to maximise precision, require a programmer-provided strict upper bound on the number of loop iterations.
157Compiler optimizations could rearrange code in such a manner that the upper bound is no longer strict.
158The certified CerCo C compiler validates such strong assumptions, and a certified analysis tool could be obtained by combining the CerCo compiler with any certified WCET tool.
159
160We are interested in building a fully certified tool.
161However we are not able to build a certified WCET tool \emph{and} certified C compiler within the confines of the CerCo project.
162We therefore focus on certifying the compiler by targetting a microprocessor where complex WCET analyses are not required.
163
164Caching, memory effects, and advanced features such as branch prediction all have an effect on the complexity of WCET analyses (see~\cite{bate:wcet:2011,yan:wcet:2008}, and so on).
165CerCo therefore decided to focus on 8-bit microprocessors, which are still used in embedded systems.
166These have a predictable, precise cost model due to their relative paucity of features.
167Manufacturer timesheets provide \emph{exact guarantees} for the number of processor cycles each instruction will take to execute.
168
169We have fully formalised an executable formal semantics of a family of 8-bit Freescale microprocessors~\cite{oliboni:matita:2008}, and provided a similar executable formal semantics for the MCS-51 microprocessor.
170The latter is what we describe in this paper.
171The focus of the formalisation has been on capturing the intensional behaviour of the processor; this is not novel.
172However, the design of the MCS-51 itself has caused problems in the formalisation.
173For example, the MCS-51 has a highly unorthogonal instruction set.
174To cope with this unorthogonality, and to produce an executable specification, we rely on the dependent types of Matita, an interactive proof assistant~\cite{asperti:user:2007}.
175The manner in which we combined dependent types and coercions to handle this problem is novel.
176
177\paragraph*{The MCS-51}\quad
178The MCS-51 is an 8-bit microprocessor introduced by Intel in the late 1970s.
179Commonly called the 8051, in the decades since its introduction the processor has become a popular component of embedded systems.
180The processor and derivatives are still manufactured \emph{en masse} by a host of vendors.
181Surprisingly, however, there is not yet a formal model of the MCS-51.
182
183The 8051 is a well documented processor, with very few underspecified behaviours (almost all of these correspond to erroneous usage of the processor).
184The processor also has the support of numerous open source and commercial tools, such as compilers and emulators.
185For instance, the open source Small Device C Compiler (SDCC) recognises a dialect of C~\cite{sdcc:2010}, and other compilers for BASIC, Forth and Modula-2 are also extant.
186An open source emulator for the processor, MCU 8051 IDE, is also available~\cite{mcu8051ide:2010}.
187Both MCU 8051 IDE and SDCC were used in for validating the formalisation.
188
189\begin{figure*}
190\centering
191\setlength{\unitlength}{0.87pt}
192\begin{picture}(410,250)(-50,200)
193%\put(-50,200){\framebox(410,250){}}
194\put(12,410){\makebox(80,0)[b]{Internal (256B)}}
195\put(13,242){\line(0,1){165}}
196\put(93,242){\line(0,1){165}}
197\put(13,407){\line(1,0){80}}
198\put(12,400){\makebox(0,0)[r]{0h}}  \put(14,400){\makebox(0,0)[l]{Register bank 0}}
199\put(13,393){\line(1,0){80}}
200\put(12,386){\makebox(0,0)[r]{8h}}  \put(14,386){\makebox(0,0)[l]{Register bank 1}}
201\put(13,379){\line(1,0){80}}
202\put(12,372){\makebox(0,0)[r]{10h}}  \put(14,372){\makebox(0,0)[l]{Register bank 2}}
203\put(13,365){\line(1,0){80}}
204\put(12,358){\makebox(0,0)[r]{18h}} \put(14,358){\makebox(0,0)[l]{Register bank 3}}
205\put(13,351){\line(1,0){80}}
206\put(12,344){\makebox(0,0)[r]{20h}} \put(14,344){\makebox(0,0)[l]{Bit addressable}}
207\put(13,323){\line(1,0){80}}
208\put(12,316){\makebox(0,0)[r]{30h}}
209  \put(14,309){\makebox(0,0)[l]{\quad \vdots}}
210\put(13,291){\line(1,0){80}}
211\put(12,284){\makebox(0,0)[r]{80h}}
212  \put(14,263){\makebox(0,0)[l]{\quad \vdots}}
213\put(12,249){\makebox(0,0)[r]{ffh}}
214\put(13,242){\line(1,0){80}}
215
216\qbezier(-2,407)(-6,407)(-6,393)
217\qbezier(-6,393)(-6,324)(-10,324)
218\put(-12,324){\makebox(0,0)[r]{Indirect/stack}}
219\qbezier(-6,256)(-6,324)(-10,324)
220\qbezier(-2,242)(-6,242)(-6,256)
221
222\qbezier(94,407)(98,407)(98,393)
223\qbezier(98,393)(98,349)(102,349)
224\put(104,349){\makebox(0,0)[l]{Direct}}
225\qbezier(98,305)(98,349)(102,349)
226\qbezier(94,291)(98,291)(98,305)
227
228\put(102,242){\framebox(20,49){SFR}}
229% bit access to sfrs?
230
231\qbezier(124,291)(128,291)(128,277)
232\qbezier(128,277)(128,266)(132,266)
233\put(134,266){\makebox(0,0)[l]{Direct}}
234\qbezier(128,257)(128,266)(132,266)
235\qbezier(124,242)(128,242)(128,256)
236
237\put(164,410){\makebox(80,0)[b]{External (64kB)}}
238\put(164,220){\line(0,1){187}}
239\put(164,407){\line(1,0){80}}
240\put(244,220){\line(0,1){187}}
241\put(164,242){\line(1,0){80}}
242\put(163,400){\makebox(0,0)[r]{0h}}
243\put(164,324){\makebox(80,0){Paged access}}
244  \put(164,310){\makebox(80,0){Direct/indirect}}
245\put(163,235){\makebox(0,0)[r]{80h}}
246  \put(164,228){\makebox(80,0){\vdots}}
247  \put(164,210){\makebox(80,0){Direct/indirect}}
248
249\put(264,410){\makebox(80,0)[b]{Code (64kB)}}
250\put(264,220){\line(0,1){187}}
251\put(264,407){\line(1,0){80}}
252\put(344,220){\line(0,1){187}}
253\put(263,400){\makebox(0,0)[r]{0h}}
254  \put(264,228){\makebox(80,0){\vdots}}
255  \put(264,324){\makebox(80,0){Direct}}
256  \put(264,310){\makebox(80,0){PC relative}}
257\end{picture}
258\caption{The 8051 memory model}
259\label{fig.memory.layout}
260\end{figure*}
261
262The 8051 has a relatively straightforward architecture.
263A high-level overview of the processor's memory layout, along with the ways in which different memory spaces may be addressed, is provided in Figure~\ref{fig.memory.layout}.
264
265Processor RAM is divided into numerous segments, with the most prominent division being between internal and (optional) external memory.
266Internal memory, commonly provided on the die itself with fast access, is composed of 256 bytes, but, in direct addressing mode, half of them are overloaded with 128 bytes of memory-mapped Special Function Registers (SFRs).
267SFRs control the operation of the processor.
268Internal RAM (IRAM) is divided again into 8 general purpose bit-addressable registers (R0--R7).
269These sit in the first 8 bytes of IRAM, though can be programmatically `shifted up' as needed.
270Bit memory, followed by a small amount of stack space, resides in the memory space immediately following the register banks.
271What remains of IRAM may be treated as general purpose memory.
272A schematic view of IRAM layout is also provided in Figure~\ref{fig.memory.layout}.
273
274External RAM (XRAM), limited to a maximum size of 64 kilobytes, is optional, and may be provided on or off chip, depending on the vendor.
275XRAM is accessed using a dedicated instruction, and requires 16 bits to address fully.
276External code memory (XCODE) is often stored as an EPROM, and limited to 64 kilobytes in size.
277However, depending on the particular processor model, a dedicated on-die read-only memory area for program code (ICODE) may be supplied.
278
279Memory may be addressed in numerous ways: immediate, direct, indirect, external direct and code indirect.
280As the latter two addressing modes hint, there are some restrictions enforced by the 8051, and its derivatives, on which addressing modes may be used with specific types of memory.
281For instance, the extra 128 bytes of IRAM of the 8052 cannot be addressed using indirect addressing; rather, external (in)direct addressing must be used. Moreover, some memory segments are addressed using 8-bit pointers while others require 16-bits.
282
283The 8051 possesses an 8-bit Arithmetic and Logic Unit (ALU), with a variety of instructions for performing arithmetic and logical operations on bits and integers.
284Two 8-bit general purpose accumulators, A and B, are provided.
285
286Communication with the device is handled by an inbuilt UART serial port and controller.
287This can operate in numerous modes.
288Serial baud rate is determined by one of two 16-bit timers included with the 8051, which can be set to multiple modes of operation.
289(The 8052 provides an additional 16-bit timer.)
290The 8051 also provides a 4 byte bit-addressable I/O port.
291
292The programmer may take advantage of an interrupt mechanism.
293This is especially useful when dealing with I/O involving the serial device, as an interrupt can be set when a whole character is sent or received via the UART.
294
295Interrupts immediately halt the flow of execution of the processor, and cause the program counter to jump to a fixed address, where the requisite interrupt handler is stored.
296However, interrupts may be set to one of two priorities: low and high.
297The interrupt handler of an interrupt with high priority is executed ahead of the interrupt handler of an interrupt of lower priority, interrupting a currently executing handler of lower priority, if necessary.
298
299The 8051 has interrupts disabled by default.
300The programmer is free to handle serial input and output manually, by poking serial flags in the SFRs.
301`Exceptional circumstances' that would otherwise trigger an interrupt on more modern processors, (e.g. division by zero) are also signalled by setting flags.
302
303%\begin{figure}[t]
304%\begin{center}
305%\includegraphics[scale=0.5]{iramlayout.png}
306%\end{center}
307%\caption{Schematic view of 8051 IRAM layout}
308%\label{fig.iram.layout}
309%\end{figure}
310
311\paragraph*{Overview of paper}\quad
312In Section~\ref{sect.design.issues.formalisation} we discuss design issues in the development of the formalisation.
313In Section~\ref{sect.validation} we discuss validation of the emulator to ensure that what we formalised was an accurate model of an MCS-51 series microprocessor.
314In Section~\ref{sect.related.work} we describe previous work, with an eye toward describing its relation with the work described herein.
315In Section~\ref{sect.conclusions} we conclude.
316
317%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
318% SECTION                                                                      %
319%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
320\section{Design issues in the formalisation}
321\label{sect.design.issues.formalisation}
322
323We implemented two emulators, one in O'Caml and one in Matita.
324The O'Caml emulator is intended to be `feature complete' with respect to the MCS-51 device.
325However, the Matita emulator is intended to be used as a target for a certified, complexity preserving C compiler.
326As a result, not all features of the MCS-51 are formalised in the Matita emulator.
327
328We designed the O'Caml emulator to be as efficient as possible, under the constraint that it would be eventually translated into Matita.
329One performance drain in the O'Caml emulator is the use of purely functional map datastructures to represent memory spaces, used to maintain the close correspondence between the Matita and O'Caml emulators.
330
331Matita~\cite{asperti:user:2007} is a proof assistant based on the Calculus of Coinductive constructions, similar to Coq.
332As a programming language, Matita corresponds to the functional fragment of O'Caml extended with dependent types.
333Matita also features a rich higher-order logic for reasoning about programs.
334Unlike O'Caml, all recursive functions must be structurally recursive, and therefore total.
335
336We box Matita code to distinguish it from O'Caml code.
337In Matita, `\texttt{?}' or `\texttt{$\ldots$}' denote arguments to be inferred automatically.
338
339A full account of the formalisation can be found in~\cite{cerco-report:2011}.
340All source code is available from the CerCo project website~\cite{cerco-code:2011}.
341
342%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
343% SECTION                                                                      %
344%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
345\subsection{Representation of bytes, words, etc.}
346\label{subsect.representation.integers}
347
348\begin{figure}[t]
349\begin{minipage}[t]{0.45\textwidth}
350\vspace{0pt}
351\small{
352\begin{lstlisting}
353type 'a vect = bit list
354type nibble = [`Sixteen] vect
355type byte = [`Eight] vect
356let split_word w = split_nth 4 w
357let split_byte b = split_nth 2 b
358\end{lstlisting}}
359\end{minipage}
360%
361\begin{minipage}[t]{0.55\textwidth}
362\vspace{0pt}
363\begin{lstlisting}
364type 'a vect
365type word = [`Sixteen] vect
366type byte = [`Eight] vect
367val split_word: word -> byte * word
368val split_byte: byte -> nibble * nibble
369\end{lstlisting}
370\end{minipage}
371\caption{Sample of O'Caml implementation and interface for bitvectors module}
372\label{fig.ocaml.implementation.bitvectors}
373\end{figure}
374
375The formalization of MCS-51 must deal with bytes (8-bits), words (16-bits), and also more exoteric quantities (7, 3 and 9-bits).
376To avoid difficult-to-trace size mismatch bugs, we represented all quantities using bitvectors, i.e. fixed length vectors of booleans.
377In the O'Caml emulator, we `faked' bitvectors using phantom types~\cite{leijen:domain:1999} implemented with polymorphic variants~\cite{garrigue:programming:1998}, as in Figure~\ref{fig.ocaml.implementation.bitvectors}.
378From within the bitvector module (top) bitvectors are just lists of bits and no guarantee is provided on sizes.
379However, the module's interface (bottom) enforces size invariants in the rest of the code.
380
381In Matita, we are able to use the full power of dependent types to always work with vectors of a known size:
382\begin{lstlisting}[frame=single]
383inductive Vector (A: Type[0]): nat $\rightarrow$ Type[0] ≝
384  VEmpty: Vector A O
385| VCons: $\forall$n: nat. A $\rightarrow$ Vector A n $\rightarrow$ Vector A (S n).
386\end{lstlisting}
387We define \texttt{BitVector} as a specialization of \texttt{Vector} to \texttt{bool}.
388We may use Matita's type system to provide precise typings for functions that are polymorphic in the size without code duplication:
389\begin{lstlisting}[frame=single]
390let rec split (A: Type[0]) (m,n: nat) on m:
391   Vector A (m + n) $\rightarrow$ (Vector A m)$\times$(Vector A n) := ...
392\end{lstlisting}
393
394%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
395% SECTION                                                                      %
396%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
397\subsection{Representing memory}
398\label{subsect.representing.memory}
399
400The MCS-51 has numerous disjoint memory spaces addressed by differently sized pointers.
401In the O'Caml implementation, we use a map data structure (from the standard library) for each space.
402In Matita, we exploited dependent types to design a data structure which enforced the correspondence between the size of pointer and the size of the memory space.
403Further, we assumed that large swathes of memory would often be uninitialized (an assumption on the behaviour of the programmer, not the processor!)
404
405We picked a modified form of trie of fixed height $h$.
406Paths are represented by bitvectors (already used in the implementation for addresses and registers) of length $h$:
407\begin{lstlisting}[frame=single]
408inductive BitVectorTrie (A: Type[0]): nat $\rightarrow$ Type[0] ≝
409  Leaf: A $\rightarrow$ BitVectorTrie A 0
410| Node: ∀n. BitVectorTrie A n $\rightarrow$ BitVectorTrie A n $\rightarrow$
411  BitVectorTrie A (S n)
412| Stub: ∀n. BitVectorTrie A n.
413\end{lstlisting}
414\texttt{Stub} is a constructor that can appear at any point in a trie.
415It represents `uninitialized data'.
416Performing a lookup in memory is now straight-forward.
417The only subtlety over normal trie lookup is how we handle \texttt{Stub}.
418We traverse a path, and upon encountering \texttt{Stub}, we return a default value\footnote{All manufacturer data sheets that we consulted were silent on the subject of what should be returned if we attempt to access uninitialized memory.  We defaulted to simply returning zero, though our \texttt{lookup} function is parametric in this choice.  We do not believe that this is an outrageous decision, as SDCC for instance generates code which first `zeroes out' all memory in a preamble before executing the program proper.  This is in line with the C standard, which guarantees that all global variables will be zero initialized piecewise.}.
419
420\texttt{BitVectorTrie} and \texttt{Vector} datastructures, and related functions, can be used in the formalising other microprocessors.
421
422%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
423% SECTION                                                                      %
424%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
425\subsection{Labels and pseudoinstructions}
426\label{subsect.labels.pseudoinstructions}
427
428Aside from implementing the core MCS-51 instruction set, we also provided \emph{pseudoinstructions}, \emph{labels} and \emph{cost labels}.
429The purpose of \emph{cost labels} will be explained in Subsection~\ref{subsect.computation.cost.traces}.
430
431Introducing pseudoinstructions had the effect of simplifying a C compiler---another component of the CerCo project---that was being implemented in parallel with our implementation.
432To see why, consider the fact that the MCS-51's instruction set has numerous instructions for unconditional and conditional jumps to memory locations.
433For instance, the instructions \texttt{AJMP}, \texttt{JMP} and \texttt{LJMP} all perform unconditional jumps.
434However, these instructions differ in how large the maximum size of the offset of the jump to be performed can be.
435Further, all jump instructions require a concrete memory address---to jump to---to be specified.
436Compilers that support separate compilation cannot directly compute these offsets and select the appropriate jump instructions.
437These operations are also burdensome for compilers that do not do separate compilation and are handled by assemblers.
438We followed suit.
439
440While introducing pseudoinstructions, we also introduced labels for locations to jump to, and for global data.
441To specify global data via labels, we introduced a preamble before the program where labels and the size of reserved space for data is stored.
442A pseudoinstruction \texttt{Mov} moves (16-bit) data stored at a label into the MCS-51's 16-bit register, \texttt{DPTR}.
443(This register is used for indirect addressing of data stored in external memory.)
444
445The pseudoinstructions and labels induce an assembly language similar to that of SDCC's.
446All pseudoinstructions and labels are `assembled away' prior to program execution.
447Jumps are computed in two stages.
448A map associating memory addresses to labels is built, before replacing pseudojumps with concrete jumps to the correct address.
449The algorithm currently implemented does not try to minimize object code size by picking the shortest possible jump instruction.
450A better algorithm is left for future work.
451
452%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
453% SECTION                                                                      %
454%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
455\subsection{Anatomy of the (Matita) emulator}
456\label{subsect.anatomy.matita.emulator}
457
458The internal state of the Matita emulator is represented as a record:
459\begin{lstlisting}[frame=single]
460record Status: Type[0] :=
461{
462  code_memory: BitVectorTrie Byte 16;
463  low_internal_ram: BitVectorTrie Byte 7;
464  high_internal_ram: BitVectorTrie Byte 7;
465  external_ram: BitVectorTrie Byte 16;
466  program_counter: Word;
467  special_function_registers_8051: Vector Byte 19;
468  ...
469}.
470\end{lstlisting}
471This record encapsulates the current memory contents, the program counter, the state of the current SFRs, and so on.
472
473Here the MCS-51's memory model is implemented using four disjoint memory spaces, plus SFRs.
474From the programmer's point of view, what \emph{really} matters are the addressing modes that are in a many-to-many relationship with the spaces.
475\texttt{DIRECT} addressing can be used to address either lower IRAM (if the first bit is 0) or the SFRs (if the first bit is 1), for instance.
476That's why DIRECT uses 8-bit addresses but pointers to lower IRAM only use 7 bits.
477The complexity of the memory model is captured in a pair of functions, \texttt{get\_arg\_XX} and \texttt{set\_arg\_XX}, that `get' and `set' data of size \texttt{XX} from memory.
478
479%Overlapping, and checking which addressing modes can be used to address particular memory spaces, is handled through numerous \texttt{get\_arg\_XX} and \texttt{set\_arg\_XX} (for 1, 8 and 16 bits) functions.
480
481Both the Matita and O'Caml emulators follow the classic `fetch-decode-execute' model of processor operation.
482The next instruction to be processed, indexed by the program counter, is fetched from code memory with \texttt{fetch}.
483An updated program counter, along with its concrete cost in processor cycles, is also returned.
484These costs are taken from a Siemens Semiconductor Group data sheet for the MCS-51~\cite{siemens:2011}, and will likely vary between particular implementations.
485\begin{lstlisting}[frame=single]
486definition fetch: BitVectorTrie Byte 16 $\rightarrow$ Word $\rightarrow$
487  instruction $\times$ Word $\times$ nat
488\end{lstlisting}
489Instruction are assembled to bit encodings by \texttt{assembly1}:
490\begin{lstlisting}[frame=single]
491definition assembly1: instruction $\rightarrow$ list Byte
492\end{lstlisting}
493An assembly program---comprising a preamble containing global data and a list of pseudoinstructions---is assembled using \texttt{assembly}.
494Pseudoinstructions and labels are eliminated in favour of instructions from the MCS-51 instruction set.
495A map associating memory locations and cost labels (see Subsection~\ref{subsect.computation.cost.traces}) is produced.
496\begin{lstlisting}[frame=single]
497definition assembly: assembly_program $\rightarrow$
498  option (list Byte $\times$ (BitVectorTrie String 16))
499\end{lstlisting}
500A single fetch-decode-execute cycle is performed by \texttt{execute\_1}:
501\begin{lstlisting}[frame=single]
502definition execute_1: Status $\rightarrow$ Status
503\end{lstlisting}
504The \texttt{execute} functions performs a fixed number of cycles by iterating
505\texttt{execute\_1}:
506\begin{lstlisting}[frame=single]
507let rec execute (n: nat) (s: Status): Status := ...
508\end{lstlisting}
509This differs from the O'Caml emulator, which executed a program indefinitely.
510A callback function was also accepted as an argument, which `witnessed' the execution as it happened.
511Due to Matita's termination requirement, \texttt{execute} cannot execute a program indefinitely.
512An alternative approach would be to produce an infinite stream of statuses representing an execution trace.
513Matita supports infinite streams through co-inductive types.
514
515%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
516% SECTION                                                                      %
517%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
518\subsection{Instruction set unorthogonality}
519\label{subsect.instruction.set.unorthogonality}
520
521A peculiarity of the MCS-51 is its unorthogonal instruction set.
522For instance, the \texttt{MOV} instruction can be invoked using one of 16 combinations of addressing modes out of a possible 361.
523
524% Show example of pattern matching with polymorphic variants
525
526Such unorthogonality in the instruction set was handled with the use of polymorphic variants in O'Caml~\cite{garrigue:programming:1998}.
527For instance, we introduced types corresponding to each addressing mode:
528\begin{lstlisting}
529type direct = [ `DIRECT of byte ]
530type indirect = [ `INDIRECT of bit ]
531...
532\end{lstlisting}
533Which were then combined in the inductive datatype for assembly preinstructions using the union operator `$|$':
534\begin{lstlisting}
535type 'addr preinstruction =
536[ `ADD of acc * [ reg | direct | indirect | data ]
537...
538| `MOV of
539   (acc * [ reg| direct | indirect | data ],
540   [ reg | indirect ] * [ acc | direct | data ],
541   direct * [ acc | reg | direct | indirect | data ],
542   dptr * data16,
543   carry * bit,
544   bit * carry
545   ) union6
546...
547\end{lstlisting}
548Here, \texttt{union6} is a disjoint union type, defined as follows:
549\begin{lstlisting}
550type ('a,'b,'c,'d,'e,'f) union6 =
551  [ `U1 of 'a | ... | `U6 of 'f ]
552\end{lstlisting}
553For our purposes, the types \texttt{union2}, \texttt{union3} and \texttt{union6} sufficed.
554
555This polymorphic variant machinery worked well: it introduced a certain level of type safety (for instance, the type of \texttt{MOV} above guarantees it cannot be invoked with arguments in the \texttt{carry} and \texttt{data16} addressing modes, respectively), and also allowed us to pattern match against instructions, when necessary.
556However, this polymorphic variant machinery is \emph{not} present in Matita.
557We needed some way to produce the same effect, which Matita supported.
558For this task, we used dependent types.
559
560We first provided an inductive data type representing all possible addressing modes, a type that functions will pattern match against:
561\begin{lstlisting}[frame=single]
562inductive addressing_mode: Type[0] :=
563  DIRECT: Byte $\rightarrow$ addressing_mode
564| INDIRECT: Bit $\rightarrow$ addressing_mode
565...
566\end{lstlisting}
567We also wished to express in the type of functions the \emph{impossibility} of pattern matching against certain constructors.
568In order to do this, we introduced an inductive type of addressing mode `tags'.
569The constructors of \texttt{addressing\_mode\_tag} are in one-to-one correspondence with the constructors of \texttt{addressing\_mode}:
570\begin{lstlisting}[frame=single]
571inductive addressing_mode_tag : Type[0] :=
572  direct: addressing_mode_tag
573| indirect: addressing_mode_tag
574...
575\end{lstlisting}
576The \texttt{is\_a} function checks if an \texttt{addressing\_mode} matches an \texttt{addressing\_mode\_tag}:
577\begin{lstlisting}[frame=single]
578let rec is_a
579  (d: addressing_mode_tag)
580  (A: addressing_mode) on d :=
581match d with
582[ direct $\Rightarrow$
583  match A with [ DIRECT _ $\Rightarrow$ true | _ $\Rightarrow$ false ]
584| indirect $\Rightarrow$
585  match A with [ INDIRECT _ $\Rightarrow$ true | _ $\Rightarrow$ false ]
586...
587\end{lstlisting}
588The \texttt{is\_in} function checks if an \texttt{addressing\_mode} matches a set of tags represented as a vector. It simply extends the \texttt{is\_a} function in the obvious manner.
589
590A \texttt{subaddressing\_mode} is an \emph{ad hoc} non-empty $\Sigma$-type of \texttt{addressing\_mode}s constrained to be in a set of tags:
591\begin{lstlisting}[frame=single]
592record subaddressing_mode
593  (n: nat)
594  (l: Vector addressing_mode_tag (S n)): Type[0] :=
595{
596  subaddressing_modeel :> addressing_mode;
597  subaddressing_modein:
598    bool_to_Prop (is_in ? l subaddressing_modeel)
599}.
600\end{lstlisting}
601An implicit coercion~\cite{luo:coercive:1999} is provided to promote vectors of tags (denoted with $\llbracket - \rrbracket$) to the corresponding \texttt{subaddressing\_mode} so that we can use a syntax close to that of O'Caml to specify \texttt{preinstruction}s:
602\begin{lstlisting}[frame=single]
603inductive preinstruction (A: Type[0]): Type[0] ≝
604  ADD: $\llbracket$acc_a$\rrbracket$ $\rightarrow$ $\llbracket$register;direct;indirect;data$\rrbracket$ $\rightarrow$
605       preinstruction A
606| ADDC: $\llbracket$acc_a$\rrbracket$ $\rightarrow$ $\llbracket$register;direct;indirect;data$\rrbracket$ $\rightarrow$
607        preinstruction A
608...
609\end{lstlisting}
610The constructor \texttt{ADD} expects two parameters, the first being the accumulator A (\texttt{acc\_a}), the second being a register, direct, indirect or data addressing mode.
611
612% One of these coercions opens up a proof obligation which needs discussing
613% Have lemmas proving that if an element is a member of a sub, then it is a member of a superlist, and so on
614The final component is a pair of type coercions from \texttt{addressing\_mode} to \texttt{subaddressing\_mode} and from \texttt{subaddressing\_mode} to \texttt{Type$\lbrack0\rbrack$}, respectively.
615The first is a forgetful coercion, while the second opens a proof obligation wherein we must prove that the provided value is in the admissible set.
616These coercions were first introduced by PVS to implement subset types~\cite{shankar:principles:1999}, and later in Coq as part of Russell~\cite{sozeau:subset:2006}.
617In Matita all coercions can open proof obligations.
618
619Proof obligations require us to state and prove a few auxilliary lemmas related to the transitivity of subtyping.
620For instance, an \texttt{addressing\_mode} that belongs to an allowed set also belongs to any one of its supersets.
621At the moment, Matita's automation exploits these lemmas to completely solve all the proof obligations opened in the formalisation.
622The \texttt{execute\_1} function, for instance, opens over 200 proof obligations during type checking.
623
624The machinery just described allows us to restrict the set of \texttt{addressing\_mode}s expected by a function and use this information during pattern matching.
625This allows us to skip impossible cases.
626For instance, consider \texttt{set\_arg\_16}, which expects only a \texttt{DPTR}:
627\begin{lstlisting}[frame=single]
628definition set_arg_16:
629  Status $\rightarrow$ Word $\rightarrow$ $\llbracket$dptr$\rrbracket$ $\rightarrow$ Status := $~\lambda$s, v, a.
630match a return
631   $\lambda$x. bool_to_Prop (is_in ? $\llbracket$dptr$\rrbracket$ x) $\rightarrow$ ? with
632  [ DPTR $\Rightarrow$ $\lambda$_: True.
633    let $\langle$bu, bl$\rangle$ := split $\ldots$ eight eight v in
634    let status := set_8051_sfr s SFR_DPH bu in
635    let status := set_8051_sfr status SFR_DPL bl in
636      status
637  | _ $\Rightarrow$ $\lambda$_: False. $\bot$
638  ] $~$(subaddressing_modein $\ldots$ a).
639\end{lstlisting}
640We give a proof (the expression \texttt{(subaddressing\_modein} $\ldots$ \texttt{a)}) that the argument $a$ is in the set $\llbracket$ \texttt{dptr} $\rrbracket$ to the \texttt{match} expression.
641In every case but \texttt{DPTR}, the proof is a proof of \texttt{False}, and the system opens a proof obligation $\bot$ that can be discarded using \emph{ex falso}.
642Attempting to match against a disallowed addressing mode (replacing \texttt{False} with \texttt{True} in the branch) produces a type error.
643
644We tried other dependently and non-dependently typed solutions before settling on this approach.
645As we need a large number of different combinations of addressing modes to describe the whole instruction set, it is infeasible to declare a datatype for each one of these combinations.
646The current solution is closest to the corresponding O'Caml code, to the point that the translation from O'Caml to Matita is almost syntactical.
647We would like to investigate the possibility of changing the code extraction procedure of Matita so that it recognises this programming pattern and outputs O'Caml code using polymorphic variants.
648
649% Talk about extraction to O'Caml code, which hopefully will allow us to extract back to using polymorphic variants, or when extracting vectors we could extract using phantom types
650% Discuss alternative approaches, i.e. Sigma types to piece together smaller types into larger ones, as opposed to using a predicate to `cut out' pieces of a larger type, which is what we did
651
652%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
653% SECTION                                                                      %
654%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
655\subsection{I/O and timers}
656\label{subsect.i/o.timers}
657
658% `Real clock' for I/O and timers
659The O'Caml emulator has code for handling timers, asynchronous I/O and interrupts (these are not in the Matita emulator as they are not relevant to CerCo).
660All three of these features interact with each other in subtle ways.
661Interrupts can `fire' when an input is detected on the processor's UART port, and, in certain modes, timers reset when a high signal is detected on one of the MCS-51's communication pins.
662
663To accurately model timers and I/O, we add an unbounded integral field \texttt{clock} to the central \texttt{status} record.
664This field is only logical, since it does not represent any quantity stored in the physical processor, and is used to keep track of the current `processor time'.
665Before every execution step, \texttt{clock} is incremented by the number of processor cycles that the instruction just fetched will take to execute.
666The emulator then executes the instruction, followed by the code implementing the timers and I/O\footnote{Though it isn't fully specified by the manufacturer's data sheets if I/O is handled at the beginning or the end of each cycle.}.
667In order to model I/O, we also store in \texttt{status} a \emph{continuation} which is a description of the behaviour of the environment:
668\begin{lstlisting}
669type line =
670[ `P1 of byte | `P3 of byte
671| `SerialBuff of
672   [ `Eight of byte
673   | `Nine of BitVectors.bit * byte ]
674]
675type continuation =
676[`In of time * line *
677  epsilon * continuation] option *
678[`Out of (time -> line -> time * continuation)]
679\end{lstlisting}
680At each moment, the second projection of the continuation $k$ describes how the environment will react to an output event performed in the future by the processor.
681Suppose $\pi_2(k)(\tau,o) = \langle \tau',k' \rangle$.
682If the emulator at time $\tau$ starts an asynchronous output $o$ either on the P1 or P3 output lines, or on the UART, then the environment will receive the output at time $\tau'$.
683Moreover \texttt{status} is immediately updated with the continuation $k'$.
684
685Further, if $\pi_1(k) = \mathtt{Some}~\langle \tau',i,\epsilon,k'\rangle$, then at time $\tau'$ the environment will send the asynchronous input $i$ to the emulator and \texttt{status} is updated with the continuation $k'$.
686This input is visible to the emulator only at time $\tau' + \epsilon$.
687
688The time required to perform an I/O operation is partially specified in the data sheets of the UART module.
689This computation is complex so we prefer to abstract over it.
690We leave the computation of the delay time to the environment.
691
692We use only the P1 and P3 lines despite the MCS-51 having 4 output lines, P0--P3.
693This is because P0 and P2 become inoperable if XRAM is present (we assume it is).
694
695The UART port can work in several modes, depending on the how the SFRs are set.
696In an asyncrhonous mode, the UART transmits 8 bits at a time, using a ninth line for synchronisation.
697In a synchronous mode the ninth line is used to transmit an additional bit.
698All UART modes are formalised.
699
700%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
701% SECTION                                                                      %
702%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
703\subsection{Computation of cost traces}
704\label{subsect.computation.cost.traces}
705
706As mentioned in Subsection~\ref{subsect.labels.pseudoinstructions} we introduced a notion of \emph{cost label}.
707Cost labels are inserted by the prototype C compiler at specific locations in the object code.
708Roughly, for those familiar with control flow graphs, they are inserted at the start of every basic block.
709
710Cost labels are used to calculate a precise costing for a program by marking the location of basic blocks.
711During the assembly phase, where labels and pseudoinstructions are eliminated, a map is generated associating cost labels with memory locations.
712This map is later used in a separate analysis which computes the cost of a program by traversing through a program, fetching one instruction at a time, and computing the cost of blocks.
713When targetting more complex processors, this simple analysis will need to be replaced by a more sophisticated WCET analysis.
714These block costings are stored in another map, and will later be passed back to the prototype compiler.
715
716%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
717% SECTION                                                                      %
718%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
719\section{Validation}
720\label{sect.validation}
721
722%\begin{figure}[t]
723%\begin{scriptsize}
724%\begin{verbatim}
725%08: mov 81 #07
726%
727% Processor status:                               
728%
729%   ACC: 0   B: 0   PSW: 0
730%    with flags set as:
731%     CY: false    AC: false   FO: false   RS1: false
732%     RS0: false   OV: false   UD: false   P: false
733%   SP: 7   IP: 0   PC: 8   DPL: 0   DPH: 0   SCON: 0
734%   SBUF: 0   TMOD: 0   TCON: 0
735%   Registers:                                   
736%    R0: 0   R1: 0   R2: 0   R3: 0
737%    R4: 0   R5: 0   R6: 0   R7: 0
738%\end{verbatim}
739%\end{scriptsize}
740%\caption{An example snippet from an emulator execution trace}
741%\label{fig.execution.trace}
742%\end{figure}
743
744We spent considerable effort attempting to ensure that what we have formalised is an accurate model of the MCS-51 microprocessor.
745
746We made use of multiple data sheets, each from a different manufacturer.
747This helped us triangulate errors in the specification of the processor's instruction set, and its behaviour, for instance, in a data sheet from Philips Semiconductor.
748
749The O'Caml emulator was especially useful for validation purposes.
750We wrote a module for parsing and loading Intel HEX format files.
751Intel HEX is a standard format that all compilers targetting the MCS-51, and similar processors, produce.
752It is essentially a snapshot of the processor's code memory in compressed form.
753Using this we were able to compile C programs with SDCC and load the resulting program directly into the emulator's code memory, ready for execution.
754Further, we can produce a HEX file from the emulator's code memory for loading into third party tools.
755After each step of execution, we can print out both the instruction that had been executed and a snapshot of the processor's state, including all flags and register contents.
756These traces were useful in spotting anything that was `obviously' wrong with the execution of the program.
757
758We further used MCU 8051 IDE as a reference, which allows a user to step through an assembly program one instruction at a time.
759Using these execution traces, we were able to step through a compiled program in MCU 8051 IDE and compare the resulting execution trace with the trace produced by our emulator.
760
761We partially validated the assembler by proving in Matita that on all defined opcodes the \texttt{assembly\_1} and \texttt{fetch} functions are inverse.
762
763The Matita formalisation was largely copied from the O'Caml source code, apart from the changes already mentioned.
764However, as the Matita emulator is executable, we could perform further validation by comparing the trace of a program's execution in the Matita emulator with the trace of the same program in the O'Caml emulator.
765
766%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
767% SECTION                                                                      %
768%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
769\section{Related work}
770\label{sect.related.work}
771A large body of literature on the formalisation of microprocessors exists.
772The majority of it deals with proving correctness of implementations of microprocessors at the microcode or gate level, with many considering `cycle accurate' models.
773We are interested in providing a precise specification of the behaviour of the microprocessor in order to prove the correctness of a compiler which will target the processor.
774In particular, we are interested in intensional properties of the processor; precise timings of instruction execution in clock cycles.
775Moreover, in addition to formalising the interface of an MCS-51 processor, we have also built a complete MCS-51 ecosystem: UART, I/O lines, and hardware timers, complete with an assembler.
776
777Work closely related to our own can be found in~\cite{fox:trustworthy:2010}.
778Here, the authors describe the formalisation, in HOL4, of the ARMv7 instruction set architecture.
779They further point to an excellent list of references to related work in the literature for the interested reader.
780This formalisation also considers the machine code level, opposed to their formalisation, which only considering an abstract assembly language.
781In particular, instruction decoding is explicitly modeled inside HOL4's logic.
782We go further in also providing an assembly language, complete with assembler, to translate instructions and pseudoinstruction into machine code.
783
784Further, in~\cite{fox:trustworthy:2010} the authors validated their formalisation by using development boards and random testing.
785We currently rely on non-exhaustive testing against a third party emulator.
786We recognise the importance of this exhaustive testing, but currently leave it for future work.
787
788Executability is another key difference between our work and that of~\cite{fox:trustworthy:2010}.
789Our formalisation is executable: applying the emulation function to an input state eventually reduces to an output state.
790This is because Matita is based on a logic, CIC, which internalizes conversion.
791In~\cite{fox:trustworthy:2010} the authors provide an automation layer to derive single step theorems: if the processor is in a state that satisfies some preconditions, then after execution of an instruction it will reside in a state satisfying some postconditions.
792We will not need single step theorems of this form to prove properties of the assembly code.
793
794Our main difficulties resided in the non-uniformity of an old 8-bit architecture, in terms of the instruction set, addressing modes and memory models.
795In contrast, the various ARM instruction sets and memory models are relatively uniform.
796
797Two close projects to CerCo are CompCert~\cite{leroy:formally:2009} and the CLI Stack.
798CompCert concerns the certification of a C compiler and includes a formalisation in Coq of a subset of PowerPC.
799The CLI Stack consists of the design and verification of a whole chain of artifacts including a 32-bit microprocessor, the Piton assembler and two compilers for high-level languages.
800Like CerCo, the CLI Stack compilers gave the cost of high-level instructions in processor cycles.
801However, unlike CerCo, both the CLI Stack high-level languages ($\mu$Gypsy and Nqthm Pure Lisp) and FM9001 microprocessor were not commercial products, but `artificial' designs created for the purpose of verification (see~\cite{moore:grand:2005}).
802
803The CompCert C compiler is extracted to O'Caml using Coq's code extraction facility.
804Many other formalised emulators/compilers have also been extracted from proof assistants using similar technology (e.g. see~\cite{blanqui:designing:2010}).
805We aim to make use of a similar code extraction facility in Matita, but only if the extracted code exhibits the same degree of type safety, provided by polymorphic variants, and human readability that the O'Caml emulator posseses.
806This is because we aim to use the emulator as a library for non-certified software written directly in O'Caml.
807How we have used Matita's dependent types to handle the instruction set (Subsection~\ref{subsect.instruction.set.unorthogonality}) could enable code extraction to make use of polymorphic variants.
808Using Coq's current code extraction algorithm we could write assembly programs that would generate runtime errors when emulated.
809We leave this for future work.
810
811Despite the apparent similarity between CerCo and CompCert, the two formalisations do not have much in common.
812First, CompCert provides a formalisation at the assembly level (no instruction decoding).
813This impels them to trust an unformalised assembler and linker, whereas we provide our own.
814Our formalisation is \emph{directly} executable, while the one in CompCert only provides a relation that describes execution.
815In CompCert I/O is only described as a synchronous external function call and there is no I/O at the processor level.
816Moreover an idealized abstract and uniform memory model is assumed, while we take into account the complicated overlapping memory model of the MCS-51 architecture.
817Finally, 82 instructions of the more than 200 offered by the processor are formalised in CompCert, and the assembly language is augmented with macro instructions that are turned into `real' instructions only during communication with the external assembler.
818Even from a technical level the two formalisations differ: we tried to exploit dependent types whilst CompCert largely sticks to a non-dependent fragment of Coq.
819
820In~\cite{atkey:coqjvm:2007} an executable specification of the Java Virtual Machine, using dependent types, is presented.
821As we do, dependent types there are used to remove spurious partiality from the model.
822They also lower the need for over-specifying the behaviour of the processor in impossible cases.
823Our use of dependent types will also help to maintain invariants when we prove the correctness of the CerCo prototype C compiler.
824
825Finally~\cite{sarkar:semantics:2009} provides an executable semantics for x86-CC multiprocessor machine code.
826This machine code exhibits a high degree of non-uniformity similar to the MCS-51.
827However, only a small subset of the instruction set is considered, and they over-approximate the possibilities of unorthogonality of the instruction set, largely dodging the problems we had to face.
828
829Further, it seems that the definition of the decode function is potentially error prone.
830A small domain specific language of patterns is formalised in HOL4.
831This is similar to the specification language of the x86 instruction set found in manufacturer's data sheets.
832A decode function is implemented by copying lines from data sheets into the proof script, which are then partially evaluated to obtain a compiler.
833We are currently considering implementing a similar domain specific language in Matita.
834
835%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
836% SECTION                                                                      %
837%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
838\section{Conclusions}
839\label{sect.conclusions}
840
841In CerCo, we are interested in the certification of a compiler for C that induces a precise cost model on the source code.
842Our cost model assigns costs to blocks of instructions by tracing the way that blocks are compiled, and by computing exact costs on generated machine language.
843To perform this accurately, we have provided an executable semantics for the MCS-51 family of processors.
844The formalisation was done twice, first in O'Caml and then in Matita, and captures the exact timings of the processor (according to a Siemen's data sheet).
845Moreover, the O'Caml formalisation also considers timers and I/O.
846Adding support for I/O and timers in Matita is on-going work that will not present any major problem, and was delayed only because the addition is not immediately useful for the formalisation of the CerCo compiler.
847
848The formalisation is done at machine level and not at assembly level; we also formalise fetching and decoding.
849We separately provide an assembly language, enhanched with labels and pseudoinstructions, and an assembler from this language to machine code.
850This assembly language is similar to those found in `industrial strength' compilers, such as SDCC.
851We introduce cost labels in the machine language to relate the data flow of the assembly program to that of the C source language, in order to associate costs to the C program.
852For the O'Caml version, we provide a parser and pretty printer from code memory to Intel HEX.
853Hence we can perform testing on programs compiled using any free or commercial compiler.
854
855Our main difficulty in formalising the MCS-51 was the unorthogonality of its memory model and instruction set.
856These problems are easily handled in O'Caml by using advanced language features like polymorphic variants and phantom types, simulating Generalized Abstract Data Types~\cite{xi:guarded:2003}.
857Importantly, we discovered the best manner of using dependent types to recover the same flexibility, to reduce spurious partiality, and to grant invariants that will be later useful in other formalisations in the CerCo project.
858
859The formalisation has been partially verified by computing execution traces on selected programs and comparing them with an existing emulator.
860All instructions have been tested at least once, but we have not yet pushed testing further, for example with random testing or by using development boards.
861I/O in particular has not been tested yet, and it is currently unclear how to provide exhaustive testing in the presence of I/O.
862Finally, we are aware of having over-specified the processor in several places, by fixing a behaviour hopefully consistent with the real machine, where manufacturer data sheets are ambiguous or under-specified.
863
864\bibliography{itp-2011.bib}
865
866\end{document}
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