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55
56\author{
57  \IEEEauthorblockN{Dominic P. Mulligan}
58  \IEEEauthorblockA{Dipartimento di Scienze dell'Informazione,\\ Universit\`a di Bologna}
59\and
60  \IEEEauthorblockN{Claudio Sacerdoti Coen}
61  \IEEEauthorblockA{Dipartimento di Scienze dell'Informazione,\\ Universit\`a di Bologna}
62}
63
64\title{An executable formalisation of the MCS-51 microprocessor in Matita}
65
66\thanks{The project CerCo acknowledges the financial support of the Future and
67Emerging Technologies (FET) programme within the Seventh Framework
68Programme for Research of the European Commission, under FET-Open grant
69number: 243881}
70
71\bibliographystyle{plain}
72
73\begin{document}
74
75\maketitle
76
77\begin{abstract}
78We summarise the formalisation of two emulators for the MCS-51 microprocessor in O'Caml and the Matita proof assistant.
79The MCS-51 is a widely used 8-bit microprocessor, especially popular in embedded devices.
80
81The O'Caml emulator is intended to be `feature complete' with respect to the MCS-51 device.
82However, the Matita emulator is intended to be used as a target for a certified, complexity preserving C compiler, as part of the EU-funded CerCo project.
83As a result, not all features of the MCS-51 are formalised in the Matita emulator.
84
85%The formalisation proceeded in two stages, first implementing an O'Caml prototype, for quickly `ironing out' bugs, and then porting the O'Caml emulator to Matita.
86%Though mostly straight-forward, this porting presented multiple problems.
87%Of particular interest is how the unorthoganality of the MSC-51's instruction set is handled.
88%In O'Caml, this was handled with polymorphic variants.
89%In Matita, we achieved the same effect with a non-standard use of dependent types.
90
91Both the O'Caml and Matita emulators are `executable'.
92Assembly programs may be animated within Matita, producing a trace of instructions executed.
93\end{abstract}
94
95\begin{IEEEkeywords}
96Hardware formalisation, Matita, dependent types, CerCo
97\end{IEEEkeywords}
98
99%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
100% SECTION                                                                      %
101%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
102\section{Introduction}
103\label{sect.introduction}
104
105Formal methods aim to increase our confidence in the design and implementation of software.
106Ideally, all software should come equipped with a formal specification and a proof of correctness for the corresponding implementation.
107The majority of programs are written in high level languages and then compiled into low level ones.
108Specifications are therefore also given at a high level and correctness can be proved by reasoning on the program's source code.
109The code that is actually run, however, is not the high level source code that we reason on, but low level code generated by the compiler.
110A few questions now arise:
111\begin{itemize*}
112\item
113What properties are preserved during compilation?
114\item
115What properties are affected by the compilation strategy?
116\item
117To what extent can you trust your compiler in preserving those properties?
118\end{itemize*}
119These questions, and others like them, motivate a current `hot topic' in computer science research: \emph{compiler verification} (for instance~\cite{chlipala:verified:2010,leroy:formal:2009}, and many others).
120So far, the field has only been focused on the first and last questions.
121Much attention has been placed on verifying compiler correctness with respect to extensional properties of programs.
122These are `easily' preserved during compilation.
123
124If we consider intensional properties of programs---space, time, and so forth---the situation is more complex.
125To express these properties, and reason about them, we must adopt a cost model that assigns a cost to single, or blocks, of instructions.
126A compositional cost model, assigning the same cost to all occurrences of one instruction, would be ideal.
127However, compiler optimisations are inherently non-compositional: each occurrence of a high level instruction may be compiled in a different way depending on its context.
128Therefore both the cost model and intensional specifications are affected by the compilation process.
129
130In the CerCo project (`Certified Complexity')~\cite{cerco:2011} we approach the problem of reasoning about intensional properties of programs as follows.
131We are currently developing a compiler that induces a cost model on high level source code.
132Costs are assigned to each block of high level instructions by considering the costs of the corresponding blocks of compiled code.
133The cost model is therefore inherently non-compositional, but has the potential to be extremely \emph{precise}, capturing a program's \emph{realistic} cost.
134That is, the compilation process is taken into account, not ignored.
135A prototype compiler, where no approximation of the cost is provided, has been developed.
136(The technical details of the cost model is explained in~\cite{amadio:certifying:2010}.)
137
138We believe that our approach is applicable to certifying real time programs.
139A user can certify that `deadlines' are met whilst wringing as many clock cycles from the processor---using a cost model that does not over-estimate---as possible.
140
141We also see our approach as being relevant to compiler verification (and construction).
142\emph{An optimisation specified only extensionally is only half specified}.
143Though the optimisation may preserve the denotational semantics of a program, there is no guarantee that intensional properties of the program improve.
144
145Another potential application is toward completeness and correctness of the compilation process in the presence of space constraints.
146A compiler could reject a source program targetting an embedded system when the size of the compiled code exceeds the available ROM size.
147Preservation of a program's semantics may only be required for those programs that do not exhaust the stack or heap.
148The statement of completeness of the compiler must therefore take into account a realistic cost model.
149
150With the CerCo methodology, we assume we can assign to object code exact and realistic costs for sequential blocks of instructions.
151The WCET community has developed complex tools for bounding the worst-case execution times of sequential blocks on modern processors.
152WCET analysis takes place at the object code level.
153However, it is more convenient to reason about programs at a much higher-level of abstraction.
154Therefore, the analysis must be reflected back onto the original source code.
155This reflection process is completely `untrusted' and makes strong assumptions about the internal design and correctness of the compiler.
156For example, some WCET analysis tools, to maximise precision, require a programmer-provided strict upper bound on the number of loop iterations.
157Compiler optimizations could rearrange code in such a manner that the upper bound is no longer strict.
158The certified CerCo C compiler validates such strong assumptions, and a certified analysis tool could be obtained by combining the CerCo compiler with any certified WCET tool.
159
160We are interested in building a fully certified tool.
161However we are not able to build a certified WCET tool \emph{and} certified C compiler within the confines of the CerCo project.
162We therefore focus on certifying the compiler by targetting a microprocessor where complex WCET analyses are not required.
163
164Caching, memory effects, and advanced features such as branch prediction all have an effect on the complexity of WCET analyses (see~\cite{bate:wcet:2011,yan:wcet:2008}, and so on).
165CerCo therefore decided to focus on 8-bit microprocessors, which are still used in embedded systems.
166These have a predictable, precise cost model due to their relative paucity of features.
167Manufacturer timesheets provide \emph{exact guarantees} for the number of processor cycles each instruction will take to execute.
168
169We have fully formalised an executable formal semantics of a family of 8-bit Freescale microprocessors~\cite{oliboni:matita:2008}, and provided a similar executable formal semantics for the MCS-51 microprocessor.
170The latter is what we describe in this paper.
171The focus of the formalisation has been on capturing the intensional behaviour of the processor.
172However, the design of the MCS-51 itself has caused problems in the formalisation.
173For example, the MCS-51 has a highly unorthogonal instruction set.
174To cope with this unorthogonality, and to produce an executable specification, we rely on the dependent types of Matita, an interactive proof assistant~\cite{asperti:user:2007}.
175
176\paragraph*{The MCS-51}\quad
177The MCS-51 is an 8-bit microprocessor introduced by Intel in the late 1970s.
178Commonly called the 8051, in the decades since its introduction the processor has become a popular component of embedded systems.
179The processor and derivatives are still manufactured \emph{en masse} by a host of vendors.
180Surprisingly, however, there is not yet a formal model of the MCS-51.
181
182The 8051 is a well documented processor, with very few underspecified behaviours (almost all of these correspond to erroneous usage of the processor).
183The processor also has the support of numerous open source and commercial tools, such as compilers and emulators.
184For instance, the open source Small Device C Compiler (SDCC) recognises a dialect of C~\cite{sdcc:2010}, and other compilers for BASIC, Forth and Modula-2 are also extant.
185An open source emulator for the processor, MCU 8051 IDE, is also available~\cite{mcu8051ide:2010}.
186Both MCU 8051 IDE and SDCC were used in for validating the formalisation.
187
188\begin{figure*}
189\centering
190\setlength{\unitlength}{0.87pt}
191\begin{picture}(410,250)(-50,200)
192%\put(-50,200){\framebox(410,250){}}
193\put(12,410){\makebox(80,0)[b]{Internal (256B)}}
194\put(13,242){\line(0,1){165}}
195\put(93,242){\line(0,1){165}}
196\put(13,407){\line(1,0){80}}
197\put(12,400){\makebox(0,0)[r]{0h}}  \put(14,400){\makebox(0,0)[l]{Register bank 0}}
198\put(13,393){\line(1,0){80}}
199\put(12,386){\makebox(0,0)[r]{8h}}  \put(14,386){\makebox(0,0)[l]{Register bank 1}}
200\put(13,379){\line(1,0){80}}
201\put(12,372){\makebox(0,0)[r]{10h}}  \put(14,372){\makebox(0,0)[l]{Register bank 2}}
202\put(13,365){\line(1,0){80}}
203\put(12,358){\makebox(0,0)[r]{18h}} \put(14,358){\makebox(0,0)[l]{Register bank 3}}
204\put(13,351){\line(1,0){80}}
205\put(12,344){\makebox(0,0)[r]{20h}} \put(14,344){\makebox(0,0)[l]{Bit addressable}}
206\put(13,323){\line(1,0){80}}
207\put(12,316){\makebox(0,0)[r]{30h}}
208  \put(14,309){\makebox(0,0)[l]{\quad \vdots}}
209\put(13,291){\line(1,0){80}}
210\put(12,284){\makebox(0,0)[r]{80h}}
211  \put(14,263){\makebox(0,0)[l]{\quad \vdots}}
212\put(12,249){\makebox(0,0)[r]{ffh}}
213\put(13,242){\line(1,0){80}}
214
215\qbezier(-2,407)(-6,407)(-6,393)
216\qbezier(-6,393)(-6,324)(-10,324)
217\put(-12,324){\makebox(0,0)[r]{Indirect/stack}}
218\qbezier(-6,256)(-6,324)(-10,324)
219\qbezier(-2,242)(-6,242)(-6,256)
220
221\qbezier(94,407)(98,407)(98,393)
222\qbezier(98,393)(98,349)(102,349)
223\put(104,349){\makebox(0,0)[l]{Direct}}
224\qbezier(98,305)(98,349)(102,349)
225\qbezier(94,291)(98,291)(98,305)
226
227\put(102,242){\framebox(20,49){SFR}}
228% bit access to sfrs?
229
230\qbezier(124,291)(128,291)(128,277)
231\qbezier(128,277)(128,266)(132,266)
232\put(134,266){\makebox(0,0)[l]{Direct}}
233\qbezier(128,257)(128,266)(132,266)
234\qbezier(124,242)(128,242)(128,256)
235
236\put(164,410){\makebox(80,0)[b]{External (64kB)}}
237\put(164,220){\line(0,1){187}}
238\put(164,407){\line(1,0){80}}
239\put(244,220){\line(0,1){187}}
240\put(164,242){\line(1,0){80}}
241\put(163,400){\makebox(0,0)[r]{0h}}
242\put(164,324){\makebox(80,0){Paged access}}
243  \put(164,310){\makebox(80,0){Direct/indirect}}
244\put(163,235){\makebox(0,0)[r]{80h}}
245  \put(164,228){\makebox(80,0){\vdots}}
246  \put(164,210){\makebox(80,0){Direct/indirect}}
247
248\put(264,410){\makebox(80,0)[b]{Code (64kB)}}
249\put(264,220){\line(0,1){187}}
250\put(264,407){\line(1,0){80}}
251\put(344,220){\line(0,1){187}}
252\put(263,400){\makebox(0,0)[r]{0h}}
253  \put(264,228){\makebox(80,0){\vdots}}
254  \put(264,324){\makebox(80,0){Direct}}
255  \put(264,310){\makebox(80,0){PC relative}}
256\end{picture}
257\caption{The 8051 memory model}
258\label{fig.memory.layout}
259\end{figure*}
260
261The 8051 has a relatively straightforward architecture.
262A high-level overview of the processor's memory layout, along with the ways in which different memory spaces may be addressed, is provided in Figure~\ref{fig.memory.layout}.
263
264Processor RAM is divided into numerous segments, with the most prominent division being between internal and (optional) external memory.
265Internal memory, commonly provided on the die itself with fast access, is composed of 256 bytes, but, in direct addressing mode, half of them are overloaded with 128 bytes of memory-mapped Special Function Registers (SFRs).
266SFRs control the operation of the processor.
267Internal RAM (IRAM) is divided again into 8 general purpose bit-addressable registers (R0--R7).
268These sit in the first 8 bytes of IRAM, though can be programmatically `shifted up' as needed.
269Bit memory, followed by a small amount of stack space, resides in the memory space immediately following the register banks.
270What remains of IRAM may be treated as general purpose memory.
271A schematic view of IRAM layout is also provided in Figure~\ref{fig.memory.layout}.
272
273External RAM (XRAM), limited to a maximum size of 64 kilobytes, is optional, and may be provided on or off chip, depending on the vendor.
274XRAM is accessed using a dedicated instruction, and requires 16 bits to address fully.
275External code memory (XCODE) is often stored as an EPROM, and limited to 64 kilobytes in size.
276However, depending on the particular processor model, a dedicated on-die read-only memory area for program code (ICODE) may be supplied.
277
278Memory may be addressed in numerous ways: immediate, direct, indirect, external direct and code indirect.
279As the latter two addressing modes hint, there are some restrictions enforced by the 8051, and its derivatives, on which addressing modes may be used with specific types of memory.
280For instance, the extra 128 bytes of IRAM of the 8052 cannot be addressed using indirect addressing; rather, external (in)direct addressing must be used. Moreover, some memory segments are addressed using 8-bit pointers while others require 16-bits.
281
282The 8051 possesses an 8-bit Arithmetic and Logic Unit (ALU), with a variety of instructions for performing arithmetic and logical operations on bits and integers.
283Two 8-bit general purpose accumulators, A and B, are provided.
284
285Communication with the device is handled by an inbuilt UART serial port and controller.
286This can operate in numerous modes.
287Serial baud rate is determined by one of two 16-bit timers included with the 8051, which can be set to multiple modes of operation.
288(The 8052 provides an additional 16-bit timer.)
289The 8051 also provides a 4 byte bit-addressable I/O port.
290
291The programmer may take advantage of an interrupt mechanism.
292This is especially useful when dealing with I/O involving the serial device, as an interrupt can be set when a whole character is sent or received via the UART.
293
294Interrupts immediately halt the flow of execution of the processor, and cause the program counter to jump to a fixed address, where the requisite interrupt handler is stored.
295However, interrupts may be set to one of two priorities: low and high.
296The interrupt handler of an interrupt with high priority is executed ahead of the interrupt handler of an interrupt of lower priority, interrupting a currently executing handler of lower priority, if necessary.
297
298The 8051 has interrupts disabled by default.
299The programmer is free to handle serial input and output manually, by poking serial flags in the SFRs.
300`Exceptional circumstances' that would otherwise trigger an interrupt on more modern processors, (e.g. division by zero) are also signalled by setting flags.
301
302%\begin{figure}[t]
303%\begin{center}
304%\includegraphics[scale=0.5]{iramlayout.png}
305%\end{center}
306%\caption{Schematic view of 8051 IRAM layout}
307%\label{fig.iram.layout}
308%\end{figure}
309
310\paragraph*{Overview of paper}\quad
311In Section~\ref{sect.design.issues.formalisation} we discuss design issues in the development of the formalisation.
312In Section~\ref{sect.validation} we discuss how we validated the design and implementation of the emulator to ensure that what we formalised was an accurate model of an MCS-51 series microprocessor.
313In Section~\ref{sect.related.work} we describe previous work, with an eye toward describing its relation with the work described herein.
314In Section~\ref{sect.conclusions} we conclude.
315
316%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
317% SECTION                                                                      %
318%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
319\section{Design issues in the formalisation}
320\label{sect.design.issues.formalisation}
321
322Matita~\cite{asperti:user:2007} is a proof assistant based on the Calculus of Coinductive constructions, similar to Coq.
323As a programming language, Matita corresponds to the functional fragment of O'Caml extended with dependent types.
324Matita also features a rich higher-order logic for reasoning about programs.
325Unlike O'Caml, all recursive functions must be structurally recursive, and therefore total.
326
327We box Matita code to distinguish it from O'Caml code.
328In Matita, `\texttt{?}' or `\texttt{$\ldots$}' denote arguments to be inferred automatically.
329
330A full account of the formalisation can be found in~\cite{cerco-report:2011}.
331All source code is available from the CerCo project website~\cite{cerco-code:2011}.
332
333%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
334% SECTION                                                                      %
335%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
336\subsection{Representation of bytes, words, etc.}
337\label{subsect.representation.integers}
338
339\begin{figure}[t]
340\begin{minipage}[t]{0.45\textwidth}
341\vspace{0pt}
342\small{
343\begin{lstlisting}
344type 'a vect = bit list
345type nibble = [`Sixteen] vect
346type byte = [`Eight] vect
347let split_word w = split_nth 4 w
348let split_byte b = split_nth 2 b
349\end{lstlisting}}
350\end{minipage}
351%
352\begin{minipage}[t]{0.55\textwidth}
353\vspace{0pt}
354\begin{lstlisting}
355type 'a vect
356type word = [`Sixteen] vect
357type byte = [`Eight] vect
358val split_word: word -> byte * word
359val split_byte: byte -> nibble * nibble
360\end{lstlisting}
361\end{minipage}
362\caption{Sample of O'Caml implementation and interface for bitvectors module}
363\label{fig.ocaml.implementation.bitvectors}
364\end{figure}
365
366The formalization of MCS-51 must deal with bytes (8-bits), words (16-bits), and also more exoteric quantities (7, 3 and 9-bits).
367To avoid difficult-to-trace size mismatch bugs, we represented all quantities using bitvectors, i.e. fixed length vectors of booleans.
368In the O'Caml emulator, we `faked' bitvectors using phantom types~\cite{leijen:domain:1999} implemented with polymorphic variants~\cite{garrigue:programming:1998}, as in Figure~\ref{fig.ocaml.implementation.bitvectors}.
369From within the bitvector module (top) bitvectors are just lists of bits and no guarantee is provided on sizes.
370However, the module's interface (bottom) enforces size invariants in the rest of the code.
371
372In Matita, we are able to use the full power of dependent types to always work with vectors of a known size:
373\begin{lstlisting}[frame=single]
374inductive Vector (A: Type[0]): nat $\rightarrow$ Type[0] ≝
375  VEmpty: Vector A O
376| VCons: $\forall$n: nat. A $\rightarrow$ Vector A n $\rightarrow$ Vector A (S n).
377\end{lstlisting}
378We define \texttt{BitVector} as a specialization of \texttt{Vector} to \texttt{bool}.
379We may use Matita's type system to provide precise typings for functions that are polymorphic in the size without code duplication:
380\begin{lstlisting}[frame=single]
381let rec split (A: Type[0]) (m,n: nat) on m:
382   Vector A (m + n) $\rightarrow$ (Vector A m)$\times$(Vector A n) := ...
383\end{lstlisting}
384
385%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
386% SECTION                                                                      %
387%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
388\subsection{Representing memory}
389\label{subsect.representing.memory}
390
391The MCS-51 has numerous disjoint memory spaces addressed by differently sized pointers.
392In the O'Caml implementation, we use a map data structure (from the standard library) for each space.
393In Matita, we exploited dependent types to design a data structure which enforced the correspondence between the size of pointer and the size of the memory space.
394Further, we assumed that large swathes of memory would often be uninitialized (an assumption on the behaviour of the programmer, not the processor!)
395
396We picked a modified form of trie of fixed height $h$.
397Paths are represented by bitvectors (already used in the implementation for addresses and registers) of length $h$:
398\begin{lstlisting}[frame=single]
399inductive BitVectorTrie (A: Type[0]): nat $\rightarrow$ Type[0] ≝
400  Leaf: A $\rightarrow$ BitVectorTrie A 0
401| Node: ∀n. BitVectorTrie A n $\rightarrow$ BitVectorTrie A n $\rightarrow$
402  BitVectorTrie A (S n)
403| Stub: ∀n. BitVectorTrie A n.
404\end{lstlisting}
405\texttt{Stub} is a constructor that can appear at any point in a trie.
406It represents `uninitialized data'.
407Performing a lookup in memory is now straight-forward.
408The only subtlety over normal trie lookup is how we handle \texttt{Stub}.
409We traverse a path, and upon encountering \texttt{Stub}, we return a default value\footnote{All manufacturer data sheets that we consulted were silent on the subject of what should be returned if we attempt to access uninitialized memory.  We defaulted to simply returning zero, though our \texttt{lookup} function is parametric in this choice.  We do not believe that this is an outrageous decision, as SDCC for instance generates code which first `zeroes out' all memory in a preamble before executing the program proper.  This is in line with the C standard, which guarantees that all global variables will be zero initialized piecewise.}.
410
411%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
412% SECTION                                                                      %
413%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
414\subsection{Labels and pseudoinstructions}
415\label{subsect.labels.pseudoinstructions}
416
417Aside from implementing the core MCS-51 instruction set, we also provided \emph{pseudoinstructions}, \emph{labels} and \emph{cost labels}.
418The purpose of \emph{cost labels} will be explained in Subsection~\ref{subsect.computation.cost.traces}.
419
420Introducing pseudoinstructions had the effect of simplifying a C compiler---another component of the CerCo project---that was being implemented in parallel with our implementation.
421To see why, consider the fact that the MCS-51's instruction set has numerous instructions for unconditional and conditional jumps to memory locations.
422For instance, the instructions \texttt{AJMP}, \texttt{JMP} and \texttt{LJMP} all perform unconditional jumps.
423However, these instructions differ in how large the maximum size of the offset of the jump to be performed can be.
424Further, all jump instructions require a concrete memory address---to jump to---to be specified.
425Compilers that support separate compilation cannot directly compute these offsets and select the appropriate jump instructions.
426These operations are also burdensome for compilers that do not do separate compilation and are handled by assemblers.
427We followed suit.
428
429While introducing pseudoinstructions, we also introduced labels for locations to jump to, and for global data.
430To specify global data via labels, we introduced a preamble before the program where labels and the size of reserved space for data is stored.
431A pseudoinstruction \texttt{Mov} moves (16-bit) data stored at a label into the MCS-51's one 16-bit register, \texttt{DPTR}.
432(This register is used for indirect addressing of data stored in external memory.)
433
434The pseudoinstructions and labels induce an assembly language similar to that of SDCC's.
435All pseudoinstructions and labels are `assembled away' prior to program execution.
436Jumps are computed in two stages.
437A map associating memory addresses to labels is built, before replacing pseudojumps with concrete jumps to the correct address.
438The algorithm currently implemented does not try to minimize object code size by picking the shortest possible jump instruction.
439A better algorithm is left for future work.
440
441%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
442% SECTION                                                                      %
443%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
444\subsection{Anatomy of the (Matita) emulator}
445\label{subsect.anatomy.matita.emulator}
446
447The internal state of the Matita emulator is represented as a record:
448\begin{lstlisting}[frame=single]
449record Status: Type[0] :=
450{
451  code_memory: BitVectorTrie Byte 16;
452  low_internal_ram: BitVectorTrie Byte 7;
453  high_internal_ram: BitVectorTrie Byte 7;
454  external_ram: BitVectorTrie Byte 16;
455  program_counter: Word;
456  special_function_registers_8051: Vector Byte 19;
457  ...
458}.
459\end{lstlisting}
460This record encapsulates the current memory contents, the program counter, the state of the current SFRs, and so on.
461
462Here the MCS-51's memory model is implemented using four disjoint memory spaces, plus SFRs.
463From the programmer's point of view, what \emph{really} matters are the addressing modes that are in a many-to-many relationship with the spaces.
464\texttt{DIRECT} addressing can be used to address either lower IRAM (if the first bit is 0) or the SFRs (if the first bit is 1), for instance.
465That's why DIRECT uses 8-bit addresses but pointers to lower IRAM only use 7 bits.
466The complexity of the memory model is captured in a pair of functions, \texttt{get\_arg\_XX} and \texttt{set\_arg\_XX}, that `get' and `set' data of size \texttt{XX} from memory.
467
468%Overlapping, and checking which addressing modes can be used to address particular memory spaces, is handled through numerous \texttt{get\_arg\_XX} and \texttt{set\_arg\_XX} (for 1, 8 and 16 bits) functions.
469
470Both the Matita and O'Caml emulators follow the classic `fetch-decode-execute' model of processor operation.
471The next instruction to be processed, indexed by the program counter, is fetched from code memory with \texttt{fetch}.
472An updated program counter, along with its concrete cost in processor cycles, is also returned.
473These costs are taken from a Siemens Semiconductor Group data sheet for the MCS-51~\cite{siemens:2011}, and will likely vary between particular implementations.
474\begin{lstlisting}[frame=single]
475definition fetch: BitVectorTrie Byte 16 $\rightarrow$ Word $\rightarrow$
476  instruction $\times$ Word $\times$ nat
477\end{lstlisting}
478Instruction are assembled to bit encodings by \texttt{assembly1}:
479\begin{lstlisting}[frame=single]
480definition assembly1: instruction $\rightarrow$ list Byte
481\end{lstlisting}
482An assembly program---comprising a preamble containing global data and a list of pseudoinstructions---is assembled using \texttt{assembly}.
483Pseudoinstructions and labels are eliminated in favour of instructions from the MCS-51 instruction set.
484A map associating memory locations and cost labels (see Subsection~\ref{subsect.computation.cost.traces}) is produced.
485\begin{lstlisting}[frame=single]
486definition assembly: assembly_program $\rightarrow$
487  option (list Byte $\times$ (BitVectorTrie String 16))
488\end{lstlisting}
489A single fetch-decode-execute cycle is performed by \texttt{execute\_1}:
490\begin{lstlisting}[frame=single]
491definition execute_1: Status $\rightarrow$ Status
492\end{lstlisting}
493The \texttt{execute} functions performs a fixed number of cycles by iterating
494\texttt{execute\_1}:
495\begin{lstlisting}[frame=single]
496let rec execute (n: nat) (s: Status): Status := ...
497\end{lstlisting}
498This differs from the O'Caml emulator, which executed a program indefinitely.
499A callback function was also accepted as an argument, which `witnessed' the execution as it happened.
500Due to Matita's termination requirement, \texttt{execute} cannot execute a program indefinitely.
501An alternative approach would be to produce an infinite stream of statuses representing an execution trace.
502Matita supports infinite streams through co-inductive types.
503
504%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
505% SECTION                                                                      %
506%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
507\subsection{Instruction set unorthogonality}
508\label{subsect.instruction.set.unorthogonality}
509
510A peculiarity of the MCS-51 is its unorthogonal instruction set.
511For instance, the \texttt{MOV} instruction can be invoked using one of 16 combinations of addressing modes out of a possible 361.
512
513% Show example of pattern matching with polymorphic variants
514
515Such unorthogonality in the instruction set was handled with the use of polymorphic variants in O'Caml~\cite{garrigue:programming:1998}.
516For instance, we introduced types corresponding to each addressing mode:
517\begin{lstlisting}
518type direct = [ `DIRECT of byte ]
519type indirect = [ `INDIRECT of bit ]
520...
521\end{lstlisting}
522Which were then combined in the inductive datatype for assembly preinstructions using the union operator `$|$':
523\begin{lstlisting}
524type 'addr preinstruction =
525[ `ADD of acc * [ reg | direct | indirect | data ]
526...
527| `MOV of
528   (acc * [ reg| direct | indirect | data ],
529   [ reg | indirect ] * [ acc | direct | data ],
530   direct * [ acc | reg | direct | indirect | data ],
531   dptr * data16,
532   carry * bit,
533   bit * carry
534   ) union6
535...
536\end{lstlisting}
537Here, \texttt{union6} is a disjoint union type, defined as follows:
538\begin{lstlisting}
539type ('a,'b,'c,'d,'e,'f) union6 =
540  [ `U1 of 'a | ... | `U6 of 'f ]
541\end{lstlisting}
542For our purposes, the types \texttt{union2}, \texttt{union3} and \texttt{union6} sufficed.
543
544This polymorphic variant machinery worked well: it introduced a certain level of type safety (for instance, the type of \texttt{MOV} above guarantees it cannot be invoked with arguments in the \texttt{carry} and \texttt{data16} addressing modes, respectively), and also allowed us to pattern match against instructions, when necessary.
545However, this polymorphic variant machinery is \emph{not} present in Matita.
546We needed some way to produce the same effect, which Matita supported.
547For this task, we used dependent types.
548
549We first provided an inductive data type representing all possible addressing modes, a type that functions will pattern match against:
550\begin{lstlisting}[frame=single]
551inductive addressing_mode: Type[0] :=
552  DIRECT: Byte $\rightarrow$ addressing_mode
553| INDIRECT: Bit $\rightarrow$ addressing_mode
554...
555\end{lstlisting}
556We also wished to express in the type of functions the \emph{impossibility} of pattern matching against certain constructors.
557In order to do this, we introduced an inductive type of addressing mode `tags'.
558The constructors of \texttt{addressing\_mode\_tag} are in one-to-one correspondence with the constructors of \texttt{addressing\_mode}:
559\begin{lstlisting}[frame=single]
560inductive addressing_mode_tag : Type[0] :=
561  direct: addressing_mode_tag
562| indirect: addressing_mode_tag
563...
564\end{lstlisting}
565The \texttt{is\_a} function checks if an \texttt{addressing\_mode} matches an \texttt{addressing\_mode\_tag}:
566\begin{lstlisting}[frame=single]
567let rec is_a
568  (d: addressing_mode_tag)
569  (A: addressing_mode) on d :=
570match d with
571[ direct $\Rightarrow$
572  match A with [ DIRECT _ $\Rightarrow$ true | _ $\Rightarrow$ false ]
573| indirect $\Rightarrow$
574  match A with [ INDIRECT _ $\Rightarrow$ true | _ $\Rightarrow$ false ]
575...
576\end{lstlisting}
577The \texttt{is\_in} function checks if an \texttt{addressing\_mode} matches a set of tags represented as a vector. It simply extends the \texttt{is\_a} function in the obvious manner.
578
579A \texttt{subaddressing\_mode} is an \emph{ad hoc} non-empty $\Sigma$-type of \texttt{addressing\_mode}s constrained to be in a set of tags:
580\begin{lstlisting}[frame=single]
581record subaddressing_mode
582  (n: nat)
583  (l: Vector addressing_mode_tag (S n)): Type[0] :=
584{
585  subaddressing_modeel :> addressing_mode;
586  subaddressing_modein:
587    bool_to_Prop (is_in ? l subaddressing_modeel)
588}.
589\end{lstlisting}
590An implicit coercion~\cite{luo:coercive:1999} is provided to promote vectors of tags (denoted with $\llbracket - \rrbracket$) to the corresponding \texttt{subaddressing\_mode} so that we can use a syntax close to that of O'Caml to specify \texttt{preinstruction}s:
591\begin{lstlisting}[frame=single]
592inductive preinstruction (A: Type[0]): Type[0] ≝
593  ADD: $\llbracket$acc_a$\rrbracket$ $\rightarrow$ $\llbracket$register;direct;indirect;data$\rrbracket$ $\rightarrow$
594       preinstruction A
595| ADDC: $\llbracket$acc_a$\rrbracket$ $\rightarrow$ $\llbracket$register;direct;indirect;data$\rrbracket$ $\rightarrow$
596        preinstruction A
597...
598\end{lstlisting}
599The constructor \texttt{ADD} expects two parameters, the first being the accumulator A (\texttt{acc\_a}), the second being a register, direct, indirect or data addressing mode.
600
601% One of these coercions opens up a proof obligation which needs discussing
602% Have lemmas proving that if an element is a member of a sub, then it is a member of a superlist, and so on
603The final component is a pair of type coercions from \texttt{addressing\_mode} to \texttt{subaddressing\_mode} and from \texttt{subaddressing\_mode} to \texttt{Type$\lbrack0\rbrack$}, respectively.
604The first is a forgetful coercion, while the second opens a proof obligation wherein we must prove that the provided value is in the admissible set.
605These coercions were first introduced by PVS to implement subset types~\cite{shankar:principles:1999}, and later in Coq as part of Russell~\cite{sozeau:subset:2006}.
606In Matita all coercions can open proof obligations.
607
608Proof obligations require us to state and prove a few auxilliary lemmas related to the transitivity of subtyping.
609For instance, an \texttt{addressing\_mode} that belongs to an allowed set also belongs to any one of its supersets.
610At the moment, Matita's automation exploits these lemmas to completely solve all the proof obligations opened in the formalisation.
611The \texttt{execute\_1} function, for instance, opens over 200 proof obligations during type checking.
612
613The machinery just described allows us to restrict the set of \texttt{addressing\_mode}s expected by a function and use this information during pattern matching.
614This allows us to skip impossible cases.
615For instance, consider \texttt{set\_arg\_16}, which expects only a \texttt{DPTR}:
616\begin{lstlisting}[frame=single]
617definition set_arg_16:
618  Status $\rightarrow$ Word $\rightarrow$ $\llbracket$dptr$\rrbracket$ $\rightarrow$ Status := $~\lambda$s, v, a.
619match a return
620   $\lambda$x. bool_to_Prop (is_in ? $\llbracket$dptr$\rrbracket$ x) $\rightarrow$ ? with
621  [ DPTR $\Rightarrow$ $\lambda$_: True.
622    let $\langle$bu, bl$\rangle$ := split $\ldots$ eight eight v in
623    let status := set_8051_sfr s SFR_DPH bu in
624    let status := set_8051_sfr status SFR_DPL bl in
625      status
626  | _ $\Rightarrow$ $\lambda$_: False. $\bot$
627  ] $~$(subaddressing_modein $\ldots$ a).
628\end{lstlisting}
629We give a proof (the expression \texttt{(subaddressing\_modein} $\ldots$ \texttt{a)}) that the argument $a$ is in the set $\llbracket$ \texttt{dptr} $\rrbracket$ to the \texttt{match} expression.
630In every case but \texttt{DPTR}, the proof is a proof of \texttt{False}, and the system opens a proof obligation $\bot$ that can be discarded using \emph{ex falso}.
631Attempting to match against a disallowed addressing mode (replacing \texttt{False} with \texttt{True} in the branch) produces a type error.
632
633We tried other dependently and non-dependently typed solutions before settling on this approach.
634As we need a large number of different combinations of addressing modes to describe the whole instruction set, it is infeasible to declare a datatype for each one of these combinations.
635The current solution is closest to the corresponding O'Caml code, to the point that the translation from O'Caml to Matita is almost syntactical.
636We would like to investigate the possibility of changing the code extraction procedure of Matita so that it recognises this programming pattern and outputs O'Caml code using polymorphic variants.
637
638% Talk about extraction to O'Caml code, which hopefully will allow us to extract back to using polymorphic variants, or when extracting vectors we could extract using phantom types
639% Discuss alternative approaches, i.e. Sigma types to piece together smaller types into larger ones, as opposed to using a predicate to `cut out' pieces of a larger type, which is what we did
640
641%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
642% SECTION                                                                      %
643%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
644\subsection{I/O and timers}
645\label{subsect.i/o.timers}
646
647% `Real clock' for I/O and timers
648The O'Caml emulator has code for handling timers, asynchronous I/O and interrupts (these are not in the Matita emulator as they are not relevant to CerCo).
649All three of these features interact with each other in subtle ways.
650Interrupts can `fire' when an input is detected on the processor's UART port, and, in certain modes, timers reset when a high signal is detected on one of the MCS-51's communication pins.
651
652To accurately model timers and I/O, we add an unbounded integral field \texttt{clock} to the central \texttt{status} record.
653This field is only logical, since it does not represent any quantity stored in the physical processor, and is used to keep track of the current `processor time'.
654Before every execution step, \texttt{clock} is incremented by the number of processor cycles that the instruction just fetched will take to execute.
655The emulator then executes the instruction, followed by the code implementing the timers and I/O\footnote{Though it isn't fully specified by the manufacturer's data sheets if I/O is handled at the beginning or the end of each cycle.}.
656In order to model I/O, we also store in \texttt{status} a \emph{continuation} which is a description of the behaviour of the environment:
657\begin{lstlisting}
658type line =
659[ `P1 of byte | `P3 of byte
660| `SerialBuff of
661   [ `Eight of byte
662   | `Nine of BitVectors.bit * byte ]
663]
664type continuation =
665[`In of time * line *
666  epsilon * continuation] option *
667[`Out of (time -> line -> time * continuation)]
668\end{lstlisting}
669At each moment, the second projection of the continuation $k$ describes how the environment will react to an output event performed in the future by the processor.
670Suppose $\pi_2(k)(\tau,o) = \langle \tau',k' \rangle$.
671If the emulator at time $\tau$ starts an asynchronous output $o$ either on the P1 or P3 output lines, or on the UART, then the environment will receive the output at time $\tau'$.
672Moreover \texttt{status} is immediately updated with the continuation $k'$.
673
674Further, if $\pi_1(k) = \mathtt{Some}~\langle \tau',i,\epsilon,k'\rangle$, then at time $\tau'$ the environment will send the asynchronous input $i$ to the emulator and \texttt{status} is updated with the continuation $k'$.
675This input is visible to the emulator only at time $\tau' + \epsilon$.
676
677The time required to perform an I/O operation is partially specified in the data sheets of the UART module.
678This computation is complex so we prefer to abstract over it.
679We leave the computation of the delay time to the environment.
680
681We use only the P1 and P3 lines despite the MCS-51 having 4 output lines, P0--P3.
682This is because P0 and P2 become inoperable if the processor is equipped with XRAM (we assume it is).
683
684The UART port can work in several modes, depending on the how the SFRs are set.
685In an asyncrhonous mode, the UART transmits 8 bits at a time, using a ninth line for synchronisation.
686In a synchronous mode the ninth line is used to transmit an additional bit.
687All UART modes are formalised.
688
689%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
690% SECTION                                                                      %
691%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
692\subsection{Computation of cost traces}
693\label{subsect.computation.cost.traces}
694
695As mentioned in Subsection~\ref{subsect.labels.pseudoinstructions} we introduced a notion of \emph{cost label}.
696Cost labels are inserted by the prototype C compiler at specific locations in the object code.
697Roughly, for those familiar with control flow graphs, they are inserted at the start of every basic block.
698
699Cost labels are used to calculate a precise costing for a program by marking the location of basic blocks.
700During the assembly phase, where labels and pseudoinstructions are eliminated, a map is generated associating cost labels with memory locations.
701This map is later used in a separate analysis which computes the cost of a program by traversing through a program, fetching one instruction at a time, and computing the cost of blocks.
702When targetting more complex processors, this simple analysis will need to be replaced by a more sophisticated WCET analysis.
703These block costings are stored in another map, and will later be passed back to the prototype compiler.
704
705%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
706% SECTION                                                                      %
707%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
708\section{Validation}
709\label{sect.validation}
710
711%\begin{figure}[t]
712%\begin{scriptsize}
713%\begin{verbatim}
714%08: mov 81 #07
715%
716% Processor status:                               
717%
718%   ACC: 0   B: 0   PSW: 0
719%    with flags set as:
720%     CY: false    AC: false   FO: false   RS1: false
721%     RS0: false   OV: false   UD: false   P: false
722%   SP: 7   IP: 0   PC: 8   DPL: 0   DPH: 0   SCON: 0
723%   SBUF: 0   TMOD: 0   TCON: 0
724%   Registers:                                   
725%    R0: 0   R1: 0   R2: 0   R3: 0
726%    R4: 0   R5: 0   R6: 0   R7: 0
727%\end{verbatim}
728%\end{scriptsize}
729%\caption{An example snippet from an emulator execution trace}
730%\label{fig.execution.trace}
731%\end{figure}
732
733We spent considerable effort attempting to ensure that what we have formalised is an accurate model of the MCS-51 microprocessor.
734
735We made use of multiple data sheets, each from a different manufacturer.
736This helped us triangulate errors in the specification of the processor's instruction set, and its behaviour, for instance, in a data sheet from Philips Semiconductor.
737
738The O'Caml emulator was especially useful for validation purposes.
739We wrote a module for parsing and loading Intel HEX format files.
740Intel HEX is a standard format that all compilers targetting the MCS-51, and similar processors, produce.
741It is essentially a snapshot of the processor's code memory in compressed form.
742Using this we were able to compile C programs with SDCC and load the resulting program directly into the emulator's code memory, ready for execution.
743Further, we can produce a HEX file from the emulator's code memory for loading into third party tools.
744After each step of execution, we can print out both the instruction that had been executed and a snapshot of the processor's state, including all flags and register contents.
745These traces were useful in spotting anything that was `obviously' wrong with the execution of the program.
746
747We further used MCU 8051 IDE as a reference, which allows a user to step through an assembly program one instruction at a time.
748Using these execution traces, we were able to step through a compiled program in MCU 8051 IDE and compare the resulting execution trace with the trace produced by our emulator.
749
750We partially validated the assembler by checking that on defined opcodes the \texttt{assembly\_1} and \texttt{fetch} functions are inverse.
751
752The Matita formalisation was largely copied from the O'Caml source code, apart from the changes already mentioned.
753However, as the Matita emulator is executable, we could perform further validation by comparing the trace of a program's execution in the Matita emulator with the trace of the same program in the O'Caml emulator.
754
755%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
756% SECTION                                                                      %
757%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
758\section{Related work}
759\label{sect.related.work}
760A large body of literature on the formalisation of microprocessors exists.
761The majority of it deals with proving correctness of implementations of microprocessors at the microcode or gate level.
762We are interested in providing a precise specification of the behaviour of the microprocessor in order to prove the correctness of a compiler which will target the processor.
763In particular, we are interested in intensional properties of the processor; precise timings of instruction execution in clock cycles.
764Moreover, in addition to formalising the interface of an MCS-51 processor, we have also built a complete MCS-51 ecosystem: UART, I/O lines, and hardware timers, complete with an assembler.
765
766Work closely related to our own can be found in~\cite{fox:trustworthy:2010}.
767Here, the authors describe the formalisation, in HOL4, of the ARMv7 instruction set architecture.
768They further point to an excellent list of references to related work in the literature for the interested reader.
769This formalisation also considers the machine code level, opposed to their formalisation, which only considering an abstract assembly language.
770In particular, instruction decoding is explicitly modeled inside HOL4's logic.
771We go further in also providing an assembly language, complete with assembler, to translate instructions and pseudoinstruction into machine code.
772
773Further, in~\cite{fox:trustworthy:2010} the authors validated their formalisation by using development boards and random testing.
774We currently rely on non-exhaustive testing against a third party emulator.
775We recognise the importance of this exhaustive testing, but currently leave it for future work.
776
777Executability is another key difference between our work and that of~\cite{fox:trustworthy:2010}.
778Our formalisation is executable: applying the emulation function to an input state eventually reduces to an output state.
779This is because Matita is based on a logic, CIC, which internalizes conversion.
780In~\cite{fox:trustworthy:2010} the authors provide an automation layer to derive single step theorems: if the processor is in a state that satisfies some preconditions, then after execution of an instruction it will reside in a state satisfying some postconditions.
781We will not need single step theorems of this form to prove properties of the assembly code.
782
783Our main difficulties resided in the non-uniformity of an old 8-bit architecture, in terms of the instruction set, addressing modes and memory models.
784In contrast, the various ARM instruction sets and memory models are relatively uniform.
785
786Perhaps the closest project to CerCo is CompCert~\cite{leroy:formally:2009}.
787CompCert concerns the certification of a C compiler and includes a formalisation in Coq of a subset of PowerPC.
788The CompCert C compiler is extracted to O'Caml using Coq's code extraction facility.
789We aim to make use of a similar facility in Matita.
790Many other formalised emulators/compilers have also been extracted from proof assistants using similar technology (e.g. see~\cite{blanqui:designing:2010}).
791
792Despite this similarity, the two formalisations do not have much in common.
793First, CompCert provides a formalisation at the assembly level (no instruction decoding).
794This impels them to trust an unformalised assembler and linker, whereas we provide our own.
795Our formalisation is \emph{directly} executable, while the one in CompCert only provides a relation that describes execution.
796In CompCert I/O is only described as a synchronous external function call and there is no I/O at the processor level.
797Moreover an idealized abstract and uniform memory model is assumed, while we take into account the complicated overlapping memory model of the MCS-51 architecture.
798Finally, 82 instructions of the more than 200 offered by the processor are formalised in CompCert, and the assembly language is augmented with macro instructions that are turned into `real' instructions only during communication with the external assembler.
799Even from a technical level the two formalisations differ: we tried to exploit dependent types whilst CompCert largely sticks to a non-dependent fragment of Coq.
800
801In~\cite{atkey:coqjvm:2007} an executable specification of the Java Virtual Machine, using dependent types, is presented.
802As we do, dependent types there are used to remove spurious partiality from the model.
803They also lower the need for over-specifying the behaviour of the processor in impossible cases.
804Our use of dependent types will also help to maintain invariants when we prove the correctness of the CerCo prototype C compiler.
805
806Finally~\cite{sarkar:semantics:2009} provides an executable semantics for x86-CC multiprocessor machine code.
807This machine code exhibits a high degree of non-uniformity similar to the MCS-51.
808However, only a small subset of the instruction set is considered, and they over-approximate the possibilities of unorthogonality of the instruction set, largely dodging the problems we had to face.
809
810Further, it seems that the definition of the decode function is potentially error prone.
811A small domain specific language of patterns is formalised in HOL4.
812This is similar to the specification language of the x86 instruction set found in manufacturer's data sheets.
813A decode function is implemented by copying lines from data sheets into the proof script, which are then partially evaluated to obtain a compiler.
814We are currently considering implementing a similar domain specific language in Matita.
815
816%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
817% SECTION                                                                      %
818%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
819\section{Conclusions}
820\label{sect.conclusions}
821
822In CerCo, we are interested in the certification of a compiler for C that induces a precise cost model on the source code.
823Our cost model assigns costs to blocks of instructions by tracing the way that blocks are compiled, and by computing exact costs on generated machine language.
824To perform this accurately, we have provided an executable semantics for the MCS-51 family of processors.
825The formalisation was done twice, first in O'Caml and then in Matita, and captures the exact timings of the processor (according to a Siemen's data sheet).
826Moreover, the O'Caml formalisation also considers timers and I/O.
827Adding support for I/O and timers in Matita is on-going work that will not present any major problem, and was delayed only because the addition is not immediately useful for the formalisation of the CerCo compiler.
828
829The formalisation is done at machine level and not at assembly level; we also formalise fetching and decoding.
830We separately provide an assembly language, enhanched with labels and pseudoinstructions, and an assembler from this language to machine code.
831This assembly language is similar to those found in `industrial strength' compilers, such as SDCC.
832We introduce cost labels in the machine language to relate the data flow of the assembly program to that of the C source language, in order to associate costs to the C program.
833For the O'Caml version, we provide a parser and pretty printer from code memory to Intel HEX.
834Hence we can perform testing on programs compiled using any free or commercial compiler.
835
836Our main difficulty in formalising the MCS-51 was the unorthogonality of its memory model and instruction set.
837These problems are easily handled in O'Caml by using advanced language features like polymorphic variants and phantom types, simulating Generalized Abstract Data Types~\cite{xi:guarded:2003}.
838In Matita, we use dependent types to recover the same flexibility, to reduce spurious partiality, and to grant invariants that will be later useful in other formalisations in the CerCo project.
839
840The formalisation has been partially verified by computing execution traces on selected programs and comparing them with an existing emulator.
841All instructions have been tested at least once, but we have not yet pushed testing further, for example with random testing or by using development boards.
842I/O in particular has not been tested yet, and it is currently unclear how to provide exhaustive testing in the presence of I/O.
843Finally, we are aware of having over-specified the processor in several places, by fixing a behaviour hopefully consistent with the real machine, where manufacturer data sheets are ambiguous or under-specified.
844
845\bibliography{itp-2011.bib}
846
847\end{document}
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