source: Deliverables/D4.1/ITP-Paper/itp-2011.tex @ 561

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\author{Dominic P. Mulligan\thanks{The project CerCo acknowledges the financial support of the Future and
Emerging Technologies (FET) programme within the Seventh Framework
Programme for Research of the European Commission, under FET-Open grant
number: 243881} \and Claudio Sacerdoti Coen$^\star$}
\authorrunning{D. P. Mulligan and C. Sacerdoti Coen}
\title{An executable formalisation of the MCS-51 microprocessor in Matita}
\titlerunning{An executable formalisation of the MCS-51}
\institute{Dipartimento di Scienze dell'Informazione, Universit\`a di Bologna}

\bibliographystyle{plain}

\begin{document}

\maketitle

\begin{abstract}
We summarise our formalisation of an emulator for the MCS-51 microprocessor in the Matita proof assistant.
The MCS-51 is a widely used 8-bit microprocessor, especially popular in embedded devices.

We proceeded in two stages, first implementing in O'Caml a prototype emulator, where bugs could be `ironed out' quickly.
We then ported our O'Caml emulator to Matita's internal language.
Though mostly straight-forward, this porting presented multiple problems.
Of particular interest is how we handle the extreme non-orthoganality of the MSC-51's instruction set.
In O'Caml, this was handled through heavy use of polymorphic variants.
In Matita, we achieve the same effect through a non-standard use of dependent types.

Both the O'Caml and Matita emulators are `executable'.
Assembly programs may be animated within Matita, producing a trace of instructions executed.

Our formalisation is a major component of the ongoing EU-funded CerCo project.
\end{abstract}

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% SECTION                                                                      %
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\section{Background}
\label{sect.introduction}

Formal methods are designed to increase our confidence in the design and implementation of software (and hardware).
Ideally, we would like all software to come equipped with a formal specification, along with a proof of correctness that the software meets this specification.
Today the majority of programs are written in high level languages and then compiled into low level ones.
Specifications are therefore also given at a high level and correctness can be proved by reasoning automatically or interactively on the program's source code.
The code that is actually run, however, is not the high level source code that we reason on, but the object code that is generated by the compiler.
A few simple questions now arise:
\begin{itemize*}
\item
What properties are preserved during compilation?
\item
What properties are affected by the compilation strategy?
\item
To what extent can you trust your compiler in preserving those properties?
\end{itemize*}
These questions, and others like them, motivate a current `hot topic' in computer science research: \emph{compiler verification} (for instance~\cite{leroy:formal:2009,chlipala:verified:2010}, and many others).
So far, the field has been focused on the first and last questions only.
In particular, much attention has been placed on verifying compiler correctness with respect to extensional properties of programs, which are easily preserved during compilation; it is sufficient to completely preserve the denotational semantics of the input program.

However, if we consider intensional properties of programs---such as space, time or energy spent into computation and transmission of data---the situation is more complex.
To even be able to express these properties, and to be able to reason about them, we are forced to adopt a cost model that assigns a cost to single, or blocks, of instructions.
Ideally, we would like to have a compositional cost model that assigns the same cost to all occurrences of one instruction.
However, compiler optimisations are inherently non-compositional: each occurrence of a high level instruction is usually compiled in a different way according to the context it finds itself in.
Therefore both the cost model and intensional specifications are affected by the compilation process.

In the current EU project CerCo (`Certified Complexity')~\cite{cerco:2011} we approach the problem of reasoning about intensional properties of programs as follows.
We are currently developing a compiler that induces a cost model on the high level source code.
Costs are assigned to each block of high level instructions by considering the costs of the corresponding blocks of compiled object code.
The cost model is therefore inherently non-compositional.
However, the model has the potential to be extremely \emph{precise}, capturing a program's \emph{realistic} cost, by taking into account, not ignoring, the compilation process.
A prototype compiler, where no approximation of the cost is provided, has been developed.
(The full technical details of the CerCo cost model is explained in~\cite{amadio:certifying:2010}.)

We believe that our approach is especially applicable to certifying real time programs.
Here, a user can certify that all `deadlines' are met whilst wringing as many clock cycles from the processor---using a cost model that does not over-estimate---as possible.

Further, we see our approach as being relevant to the field of compiler verification (and construction) itself.
For instance, an optimisation specified only extensionally is only half specified; though the optimisation may preserve the denotational semantics of a program, there is no guarantee that any intensional properties of the program, such as space or time usage, will be improved.
Another potential application is toward completeness and correctness of the compilation process in the presence of space constraints.
Here, a compiler could potentially reject a source program targetting an embedded system when the size of the compiled code exceeds the available ROM size.
Moreover, preservation of a program's semantics may only be required for those programs that do not exhaust the stack or heap.
Hence the statement of completeness of the compiler must take in to account a realistic cost model.

In the methodology proposed in CerCo we assume we are able to compute on the object code exact and realistic costs for sequential blocks of instructions.
With modern processors, though possible (see~\cite{bate:wcet:2011,yan:wcet:2008} for instance), it is difficult to compute exact costs or to reasonably approximate them.
This is because the execution of a program itself has an influence on the speed of processing.
For instance, caching, memory effects and other advanced features such as branch prediction all have a profound effect on execution speeds.
For this reason CerCo decided to focus on 8-bit microprocessors.
These are still widely used in embedded systems, and have the advantage of an easily predictable cost model due to the relative sparcity of features that they possess.

In particular, we have fully formalised an executable formal semantics of a family of 8 bit Freescale Microprocessors~\cite{oliboni:matita:2008}, and provided a similar executable formal semantics for the MCS-51 microprocessor.
The latter work is what we describe in this paper.
The main focus of the formalisation has been on capturing the intensional behaviour of the processor.
However, the design of the MCS-51 itself has caused problems in our formalisation.
For example, the MCS-51 has a highly unorthogonal instruction set.
To cope with this unorthogonality, and to produce an executable specification, we have exploited the dependent type system of Matita, an interactive proof assistant.

\subsection{The 8051/8052}
\label{subsect.8051-8052}

The MCS-51 is an eight bit microprocessor introduced by Intel in the late 1970s.
Commonly called the 8051, in the three decades since its introduction the processor has become a highly popular target for embedded systems engineers.
Further, the processor, its immediate successor the 8052, and many derivatives are still manufactured \emph{en masse} by a host of semiconductor suppliers.

The 8051 is a well documented processor, and has the additional support of numerous open source and commercial tools, such as compilers for high-level languages and emulators.
For instance, the open source Small Device C Compiler (SDCC) recognises a dialect of C~\cite{sdcc:2010}, and other compilers targeting the 8051 for BASIC, Forth and Modula-2 are also extant.
An open source emulator for the processor, MCU-8051 IDE, is also available~\cite{mcu8051ide:2010}.
Both MCU-8051 IDE and SDCC were used profitably in the implementation of our formalisation.

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\caption{The 8051 memory model}
\label{fig.memory.layout}
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The 8051 has a relatively straightforward architecture, unencumbered by advanced features of modern processors, making it an ideal target for formalisation.
A high-level overview of the processor's memory layout, along with the ways in which different memory spaces may be addressed, is provided in Figure~\ref{fig.memory.layout}.

Processor RAM is divided into numerous segments, with the most prominent division being between internal and (optional) external memory.
Internal memory, commonly provided on the die itself with fast access, is composed of 256 bytes, but, in direct addressing mode, half of them are overloaded with 128 bytes of memory mapped Special Function Registers (SFRs) which control the operation of the processor.
Internal RAM (IRAM) is further divided into eight general purpose bit-addressable registers (R0--R7).
These sit in the first eight bytes of IRAM, though can be programmatically `shifted up' as needed.
Bit memory, followed by a small amount of stack space, resides in the memory space immediately after the register banks.
What remains of the IRAM may be treated as general purpose memory.
A schematic view of IRAM layout is also provided in Figure~\ref{fig.memory.layout}.

External RAM (XRAM), limited to a maximum size of 64 kilobytes, is optional, and may be provided on or off chip, depending on the manufacturer.
XRAM is accessed using a dedicated instruction, and requires sixteen bits to address fully.
External code memory (XCODE) is often stored in the form of an EPROM, and limited to 64 kilobytes in size.
However, depending on the particular manufacturer and processor model, a dedicated on-die read-only memory area for program code (ICODE) may also be supplied.

Memory may be addressed in numerous ways: immediate, direct, indirect, external direct and code indirect.
As the latter two addressing modes hint, there are some restrictions enforced by the 8051 and its derivatives on which addressing modes may be used with specific types of memory.
For instance, the 128 bytes of extra internal RAM that the 8052 features cannot be addressed using indirect addressing; rather, external (in)direct addressing must be used. Moreover, some memory segments are addressed using 8 bits pointers while others require 16 bits.

The 8051 series possesses an eight bit Arithmetic and Logic Unit (ALU), with a wide variety of instructions for performing arithmetic and logical operations on bits and integers.
Further, the processor possesses two eight bit general purpose accumulators, A and B.

Communication with the device is facilitated by an onboard UART serial port, and associated serial controller, which can operate in numerous modes.
Serial baud rate is determined by one of two sixteen bit timers included with the 8051, which can be set to multiple modes of operation.
(The 8052 provides an additional sixteen bit timer.)
As an additional method of communication, the 8051 also provides a four byte bit-addressable input-output port.

The programmer may take advantage of the interrupt mechanism that the processor provides.
This is especially useful when dealing with input or output involving the serial device, as an interrupt can be set when a whole character is sent or received via the serial port.

Interrupts immediately halt the flow of execution of the processor, and cause the program counter to jump to a fixed address, where the requisite interrupt handler is stored.
However, interrupts may be set to one of two priorities: low and high.
The interrupt handler of an interrupt with high priority is executed ahead of the interrupt handler of an interrupt of lower priority, interrupting a currently executing handler of lower priority, if necessary.

The 8051 has interrupts disabled by default.
The programmer is free to handle serial input and output manually, by poking serial flags in the SFRs.
Similarly, `exceptional circumstances' that would otherwise trigger an interrupt on more modern processors, for example, division by zero, are also signalled by setting flags.

%\begin{figure}[t]
%\begin{center}
%\includegraphics[scale=0.5]{iramlayout.png}
%\end{center}
%\caption{Schematic view of 8051 IRAM layout}
%\label{fig.iram.layout}
%\end{figure}

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% SECTION                                                                      %
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\subsection{Overview of paper}
\label{subsect.overview.paper}

In Section~\ref{sect.design.issues.formalisation} we discuss design issues in the development of the formalisation.
In Section~\ref{sect.validation} we discuss how we validated the design and implementation of our emulator to ensure that what we formalised was an accurate model of an MCS-51 series microprocessor.
In Section~\ref{sect.related.work} we describe previous work, with an eye toward describing its relation with the work described herein.
In Section~\ref{sect.conclusions} we conclude the paper.

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% SECTION                                                                      %
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\section{Design issues in the formalisation}
\label{sect.design.issues.formalisation}

From hereonin, we typeset O'Caml source with \texttt{\color{blue}{blue}} and Matita source with \texttt{\color{red}{red}} to distinguish the two syntaxes.
Matita's syntax is largely straightforward to those familiar with Coq or O'Caml.
The only subtlety is the use of `\texttt{?}' in an argument position denoting an argument that should be inferred automatically.

A full account of the formalisation can be found in~\cite{cerco-report:2011}.

\subsection{Development strategy}
\label{subsect.development.strategy}

Our implementation progressed in two stages.
We began with an emulator written in O'Caml.
We used this to `iron out' any bugs in our design and implementation within O'Caml's more permissive type system.
O'Caml's ability to perform file input-output also eased debugging and validation.
Once we were happy with the performance and design of the O'Caml emulator, we moved to the Matita formalisation.

Matita's syntax is lexically similar to O'Caml's.
This eased the translation, as large swathes of code were merely copy-pasted with minor modifications.
However, several major issues had to be addresses when moving from O'Caml to Matita.
These are now discussed.

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% SECTION                                                                      %
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\subsection{Representation of bytes, words, etc.}
\label{subsect.representation.integers}

\begin{figure}[t]
\begin{minipage}[t]{0.45\textwidth}
\vspace{0pt}
\begin{lstlisting}
type 'a vect = bit list
type nibble = [`Sixteen] vect
type byte = [`Eight] vect
$\color{blue}{\mathtt{let}}$ split_word w = split_nth 4 w
$\color{blue}{\mathtt{let}}$ split_byte b = split_nth 2 b
\end{lstlisting}
\end{minipage}
%
\begin{minipage}[t]{0.55\textwidth}
\vspace{0pt}
\begin{lstlisting}
type 'a vect
type word = [`Sixteen] vect
type byte = [`Eight] vect
val split_word: word -> byte * word
val split_byte: byte -> nibble * nibble
\end{lstlisting}
\end{minipage}
\caption{Sample of O'Caml implementation and interface for bitvectors module}
\label{fig.ocaml.implementation.bitvectors}
\end{figure}

The formalization of MCS-51 must deal with bytes (8 bits), words (16 bits) but also with more exoteric quantities (7 bits, 3 bits, 9 bits).
To avoid size mismatch bugs difficult to spot, we represent all of these quantities using bitvectors, i.e. fixed length vectors of booleans.
In our O'Caml emulator, we `faked' bitvectors using phantom types~\cite{leijen:domain:1999} implemented with polymorphic variants~\cite{garrigue:programming:1998}, as in Figure~\ref{fig.ocaml.implementation.bitvectors}.
From within the bitvector module (left column) bitvectors are just lists of bits and no guarantee is provided on sizes.
However, the module's interface (right column) enforces the size invariants in the rest of the code.

In Matita, we are able to use the full power of dependent types to always work with vectors of a known size:
\begin{lstlisting}
inductive Vector (A: Type[0]): nat → Type[0] ≝
  VEmpty: Vector A O
| VCons: ∀n: nat. A → Vector A n → Vector A (S n).
\end{lstlisting}
We define \texttt{BitVector} as a specialization of \texttt{Vector} to \texttt{bool}.
We may use Matita's type system to provide precise typing for functions that are
polymorphic in the size without having to duplicate the code as we did in O'Caml:
\begin{lstlisting}
let rec split (A: Type[0]) (m,n: nat) on m:
   Vector A (plus m n) $\rightarrow$ (Vector A m) $\times$ (Vector A n) := ...
\end{lstlisting}

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% SECTION                                                                      %
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\subsection{Representing memory}
\label{subsect.representing.memory}

The MCS-51 has numerous disjoint memory segments addressed by pointers of
different sizes.
In our prototype implementation, we simply used a map datastructure (from the O'Caml standard library) for each segment.
Matita's standard library is relatively small, and does not contain a generic map datastructure. Therefore, we had the opportunity of crafting a dependently typed special-purpose datastructure for the job to enforce the correspondence between the size of pointers and the size of the segment .
We also worked under the assumption that large swathes of memory would often be uninitialized, trying to represent them concisely using stubs.

We picked a modified form of trie of fixed height $h$ where paths are
represented by bitvectors of length $h$, that are already used in our
implementation for addresses and registers:
\begin{lstlisting}
inductive BitVectorTrie (A: Type[0]): nat $\rightarrow$ Type[0] ≝
  Leaf: A $\rightarrow$ BitVectorTrie A 0
| Node: ∀n. BitVectorTrie A n $\rightarrow$ BitVectorTrie A n $\rightarrow$ BitVectorTrie A (S n)
| Stub: ∀n. BitVectorTrie A n.
\end{lstlisting}
Here, \texttt{Stub} is a constructor that can appear at any point in our tries.
It internalises the notion of `uninitialized data'.
Performing a lookup in memory is now straight-forward.
We merely traverse a path, and if at any point we encounter a \texttt{Stub}, we return a default value\footnote{All manufacturer data sheets that we consulted were silent on the subject of what should be returned if we attempt to access uninitialized memory.  We defaulted to simply returning zero, though our \texttt{lookup} function is parametric in this choice.  We do not believe that this is an outrageous decision, as SDCC for instance generates code which first `zeroes out' all memory in a preamble before executing the program proper.  This is in line with the C standard, which guarantees that all global variables will be zero initialized piecewise.}.

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% SECTION                                                                      %
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\subsection{Labels and pseudoinstructions}
\label{subsect.labels.pseudoinstructions}

Aside from implementing the core MCS-51 instruction set, we also provided \emph{pseudoinstructions}, \emph{labels} and \emph{cost labels}.
The purpose of \emph{cost labels} will be explained in Subsection~\ref{subsect.computation.cost.traces}.

Introducing pseudoinstructions had the effect of simplifying a C compiler---another component of the CerCo project---that was being implemented in parallel with our implementation.
To understand why this is so, consider the fact that the MCS-51's instruction set has numerous instructions for unconditional and conditional jumps to memory locations.
For instance, the instructions \texttt{AJMP}, \texttt{JMP} and \texttt{LJMP} all perform unconditional jumps.
However, these instructions differ in how large the maximum size of the offset of the jump to be performed can be.
Further, all jump instructions require a concrete memory address---to jump to---to be specified.
Hence compilers that support separate compilation cannot directly compute these offsets and select the appropriate jump instructions. These operations are
needleslly burdensome also for compilers that do not do separate compilation
and are thus handled by the assemblers, as we decided to do.

While introducing pseudo instructions we also introduced labels for locations
for jumps and for global data.
To specify global data via labels, we have introduced the notion of a preamble
before the program to hold the association of labels to sizes of reserved space.
A pseudoinstruction \texttt{Mov} moves (16-bit) data stored at a label into the (16-bit) register \texttt{DPTR}.

Our pseudoinstructions and labels induce an assembly language similar to that of SDCC. All pseudoinstructions and labels are `assembled away', prior to program execution, using a preprocessing stage. Jumps are computed in two stages.
The first stage builds a map associating memory addresses to labels, with the second stage removing pseudojumps with concrete jumps to the correct address. The algorithm currently implemented does not try to minimize the object code size by always picking the shortest possible jump instruction. The choice of an optimal algorithm is currently left as future work.

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% SECTION                                                                      %
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\subsection{Anatomy of the (Matita) emulator}
\label{subsect.anatomy.matita.emulator}

The internal state of our Matita emulator is represented as a record:
\begin{lstlisting}
record Status: Type[0] ≝ {
  code_memory: BitVectorTrie Byte 16;
  low_internal_ram: BitVectorTrie Byte 7;
  high_internal_ram: BitVectorTrie Byte 7;
  external_ram: BitVectorTrie Byte 16;
  program_counter: Word;
  special_function_registers_8051: Vector Byte 19;
  special_function_registers_8052: Vector Byte 5;
  ...  }.
\end{lstlisting}
This record neatly encapsulates the current memory contents, the program counter, the state of the current SFRs, and so on.

Here we choosed to represent the MCS-51 memory model using four disjoint
segments plus the SFRs. From the programmer point of view, however, what
matters are addressing modes that are in a many-to-many relation with the
segments. For instance, the \texttt{DIRECT} addressing mode can be used to
address either low internal RAM (if the first bit is 0) or the SFRs (if the first bit is 1). That's why DIRECT uses 8-bits address but pointers to the low
internal RAM only have 7 bits. Hence the complexity of the memory model
is incapsulated in the  \texttt{get\_arg\_XX} and \texttt{set\_arg\_XX}
functions that get and set data of size \texttt{XX} from the
memory by considering all possible addressing modes

%Overlapping, and checking which addressing modes can be used to address particular memory spaces, is handled through numerous \texttt{get\_arg\_XX} and \texttt{set\_arg\_XX} (for 1, 8 and 16 bits) functions.

Both the Matita and O'Caml emulators follows the classic `fetch-decode-execute' model of processor operation.
The next instruction to be processed, indexed by the program counter, is fetched from code memory with \texttt{fetch}.
An updated program counter, along with the concrete cost, in processor cycles for executing this instruction, is also returned.
These costs are taken from a Siemens Semiconductor Group data sheet for the MCS-51~\cite{siemens:2011}, and will likely vary across manufacturers and particular derivatives of the processor.
\begin{lstlisting}
definition fetch: BitVectorTrie Byte 16 $\rightarrow$ Word $\rightarrow$ instruction $\times$ Word $\times$ nat
\end{lstlisting}
Instruction are assembled to bit encodings by \texttt{assembly1}:
\begin{lstlisting}
definition assembly1: instruction $\rightarrow$ list Byte
\end{lstlisting}
An assembly program, consisting of a preamble containing global data, and a list of (pseudo)instructions, is assembled using \texttt{assembly}.
Pseudoinstructions and labels are eliminated in favour of concrete instructions from the MCS-51 instruction set.
A map associating memory locations and cost labels (see Subsection~\ref{subsect.computation.cost.traces}) is also produced.
\begin{lstlisting}
definition assembly:
  assembly_program $\rightarrow$ option (list Byte $\times$ (BitVectorTrie String 16))
\end{lstlisting}
A single fetch-decode-execute cycle is performed by \texttt{execute\_1}:
\begin{lstlisting}
definition execute_1: Status $\rightarrow$ Status
\end{lstlisting}
The \texttt{execute} functions performs a fixed number of cycles by iterating
\texttt{execute\_1}:
\begin{lstlisting}
let rec execute (n: nat) (s: Status) on n: Status := ...
\end{lstlisting}
This differs slightly from the design of the O'Caml emulator, which executed a program indefinitely, and also accepted a callback function as an argument, which could `witness' the execution as it happened, and provide a print-out of the processor state, and other debugging information.
Due to Matita's requirement that all functions be strongly normalizing, \texttt{execute} cannot execute a program indefinitely. An alternative is to
produce an infinite stream of statuses representing the execution trace.
Infinite streams are encodable in Matita as co-inductive types.

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% SECTION                                                                      %
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\subsection{Instruction set unorthogonality}
\label{subsect.instruction.set.unorthogonality}

A peculiarity of the MCS-51 is the non-orthogonality of its instruction set.
For instance, the \texttt{MOV} instruction, can be invoked using one of sixteen combinations of addressing modes out of 361.

% Show example of pattern matching with polymorphic variants

Such non-orthogonality in the instruction set was handled with the use of polymorphic variants in the O'Caml emulator.
For instance, we introduced types corresponding to each addressing mode:
\begin{lstlisting}
type direct = [ `DIRECT of byte ]
type indirect = [ `INDIRECT of bit ]
...
\end{lstlisting}
Which were then combined in our inductive datatype for assembly instructions using the union operator `$|$':
\begin{lstlisting}
type 'addr preinstruction =
 [ `ADD of acc * [ reg | direct | indirect | data ]
...
 | `MOV of 
    (acc * [ reg | direct | indirect | data ],
     [ reg | indirect ] * [ acc | direct | data ],
     direct * [ acc | reg | direct | indirect | data ],
     dptr * data16,
     carry * bit,
     bit * carry
     ) union6
...
\end{lstlisting}
Here, \texttt{union6} is a disjoint union type, defined as follows:
\begin{lstlisting}
type ('a,'b,'c,'d,'e,'f) union6 = [ `U1 of 'a | ... | `U6 of 'f ]
\end{lstlisting}
For our purposes, the types \texttt{union2}, \texttt{union3} and \texttt{union6} sufficed.

This polymorphic variant machinery worked well: it introduced a certain level of type safety (for instance, the type of our \texttt{MOV} instruction above guarantees it cannot be invoked with arguments in the \texttt{carry} and \texttt{data16} addressing modes, respectively), and also allowed us to pattern match against instructions, when necessary.
However, this polymorphic variant machinery is \emph{not} present in Matita.
We needed some way to produce the same effect, which Matita supported.
For this task, we used dependent types.

We first provided an inductive data type representing all possible addressing modes, a type that functions will pattern match against:
\begin{lstlisting}
inductive addressing_mode: Type[0] ≝
  DIRECT: Byte $\rightarrow$ addressing_mode
| INDIRECT: Bit $\rightarrow$ addressing_mode
...
\end{lstlisting}
We also wished to express in the type of functions the \emph{impossibility} of pattern matching against certain constructors.
In order to do this, we introduced an inductive type of addressing mode `tags'.
The constructors of \texttt{addressing\_mode\_tag} are in one-to-one correspondence with the constructors of \texttt{addressing\_mode}:
\begin{lstlisting}
inductive addressing_mode_tag : Type[0] ≝
  direct: addressing_mode_tag
| indirect: addressing_mode_tag
...
\end{lstlisting}
The \texttt{is\_a} function checks if an \texttt{addressing\_mode} matches an \texttt{addressing\_mode\_tag}:
\begin{lstlisting}
let rec is_a (d: addressing_mode_tag) (A: addressing_mode) on d :=
  match d with
   [ direct $\Rightarrow$ match A with [ DIRECT _ $\Rightarrow$ true | _ $\Rightarrow$ false ]
   | indirect $\Rightarrow$ match A with [ INDIRECT _ $\Rightarrow$ true | _ $\Rightarrow$ false ]
...
\end{lstlisting}
The \texttt{is\_in} function checks if an \texttt{addressing\_mode} matches a set of tags represented as a vector. It simply extends the \texttt{is\_a} function in the obvious manner.

Finally, a \texttt{subaddressing\_mode} is an ad-hoc non empty $\Sigma$-type of addressing
modes constrained to be in a given set of tags:
\begin{lstlisting}
record subaddressing_mode n (l: Vector addressing_mode_tag (S n)): Type[0] :=
 { subaddressing_modeel :> addressing_mode;
   subaddressing_modein: bool_to_Prop (is_in ? l subaddressing_modeel) }.
\end{lstlisting}
An implicit coercion is provided to promote vectors of tags (denoted with
$\llbracket - \rrbracket$)
to the
corresponding \texttt{subaddressing\_mode} so that we can use a syntax
close to the O'Caml one to specify preinstructions:
\begin{lstlisting}
inductive preinstruction (A: Type[0]): Type[0] ≝
   ADD: $\llbracket$ acc_a $\rrbracket$ $\rightarrow$ $\llbracket$ register; direct; indirect; data $\rrbracket$ $\rightarrow$ preinstruction A
 | ADDC: $\llbracket$ acc_a $\rrbracket$ $\rightarrow$ $\llbracket$ register; direct; indirect; data $\rrbracket$ $\rightarrow$ preinstruction A
...
\end{lstlisting}
We see that the constructor \texttt{ADD} expects two parameters, the first being the accumulator A (\texttt{acc\_a}), and the second being one of a register, direct, indirect or data addressing mode.

% One of these coercions opens up a proof obligation which needs discussing
% Have lemmas proving that if an element is a member of a sub, then it is a member of a superlist, and so on
The final, missing component is a pair of type coercions from \texttt{addressing\_mode} to \texttt{subaddressing\_mode} and from \texttt{subaddressing\_mode} to \texttt{Type$\lbrack0\rbrack$}, respectively.
The first one is simply a forgetful coercion, while the second one opens
a proof obligation wherein we must prove that the provided value is in the
admissible set. This kind of coercions were firstly introduced in PVS to
implement subset types~\cite{pvs?} and then in Coq as an additional machinery~\cite{russell}. In Matita all coercions can open proof obligations.

Proof obligations impels us to state and prove a few auxilliary lemmas related
to transitivity of subtyping. For instance, an addressing mode that belongs
to an allowed set also belongs to any one of its super-set. At the moment,
Matita's automation exploits these lemmas to completely solve all the proof
obligations opened in our formalization, comprising the 200 proof obligations
related to the main \texttt{execute\_1} function.

The machinery just described allows us to restrict the set of addressing
modes expected by a function and use this information during pattern matching
to skip impossible cases.
For instance, consider \texttt{set\_arg\_16}, which expects only a \texttt{DPTR}:
\begin{lstlisting}
definition set_arg_16: Status $\rightarrow$ Word $\rightarrow$ $\llbracket$ dptr $\rrbracket$ $\rightarrow$ Status ≝ $~\lambda$s, v, a.
   match a return $\lambda$x. bool_to_Prop (is_in ? $\llbracket$ dptr $\rrbracket$ x) $\rightarrow$ ? with
     [ DPTR $\Rightarrow$ $\lambda$_: True.
       let 〈 bu, bl 〉 := split $\ldots$ eight eight v in
       let status := set_8051_sfr s SFR_DPH bu in
       let status := set_8051_sfr status SFR_DPL bl in
         status
     | _ $\Rightarrow$ $\lambda$_: False. $\bot$ ] $~$(subaddressing_modein $\ldots$ a).
\end{lstlisting}
We feed to the pattern matching the proof \texttt{(subaddressing\_modein} $\ldots$ \texttt{a)} that the argument $a$ is in the set $\llbracket$ \texttt{dptr} $\rrbracket$. In all cases but \texttt{DPTR}, the proof is a proof of \texttt{False} and we can ask the system to open a proof obligation $\bot$ that will be
discarded automatically using ex-falso.
Attempting to match against a non allowed addressing mode
(replacing \texttt{False} with \texttt{True} in the branch) will produce a
type-error.

All the other dependently and non dependently typed solutions we tried before
the current one resulted to be sub-optimal in practice. In particular, since
we need a large number of different combinations of address modes to describe
the whole instruction set, it is unfeasible to declare a data type for each
one of these combinations. Moreover, the current solution is the one that
matches best the corresponding O'Caml code, at the point that the translation
from O'Caml to Matita is almost syntactical. In particular, we would like to
investigate the possibility of changing the code extraction procedure of
Matita to recognize this programming pattern and output the original
code based on polymorphic variants.

% Talk about extraction to O'Caml code, which hopefully will allow us to extract back to using polymorphic variants, or when extracting vectors we could extract using phantom types
% Discuss alternative approaches, i.e. Sigma types to piece together smaller types into larger ones, as opposed to using a predicate to `cut out' pieces of a larger type, which is what we did

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% SECTION                                                                      %
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\subsection{I/O and timers}
\label{subsect.i/o.timers}

% `Real clock' for I/O and timers
The O'Caml emulator has code for handling timers, asynchronous I/O and interrupts (these are not yet ported to the Matita emulator).
All three of these features interact with each other in subtle ways.
For instance, interrupts can `fire' when an input is detected on the processor's UART port, and, in certain modes, timers reset when a high signal is detected on one of the MCS-51's communication pins.

To accurately model timers and I/O, we add an unbounded integral field \texttt{clock} to the central \texttt{status} record.
This field is only logical, since it does not represent any quantity stored in the actual processor, and is used to keep track of the current processor time.
Before every execution step, \texttt{clock} is incremented by the number of processor cycles that the instruction just fetched will take to execute.
The processor then executes the instruction, followed by the code implementing the timers and I/O\footnote{Though it isn't fully specified by the manufacturer's data sheets if I/O is handled at the beginning or the end of each cycle.}. In order to model I/O, we also store in the status a
We use \emph{continuation} as a description of the behaviour of the environment:
\begin{lstlisting}
type line =
  [ `P1 of byte | `P3 of byte
  | `SerialBuff of [ `Eight of byte | `Nine of BitVectors.bit * byte ]]
type continuation =
  [`In of time * line * epsilon * continuation] option *
  [`Out of (time -> line -> time * continuation)]
\end{lstlisting}
At each moment, the second projection of the continuation $k$ describes how the environment will react to an output event performed in the future by the processor.
If the processor at time $\tau$ starts an asynchronous output $o$ either on the P1 or P3 output lines, or on the UART, then the environment will receive the output at time $\tau'$.
Moreover the status is immediately updated with the continuation $k'$ where $\pi_2(k)(\tau,o) = \langle \tau',k' \rangle$.

Further, if $\pi_1(k) = \mathtt{Some}~\langle \tau',i,\epsilon,k'\rangle$, then at time $\tau'$ the environment will send the asynchronous input $i$ to the processor and the status will be updated with the continuation $k'$.
This input will become visible to the processor only at time $\tau' + \epsilon$.

The time required to perform an I/O operation is partially specified in the data sheets of the UART module.
However, this computation is complex so we prefer to abstract over it.
We therefore leave the computation of the delay time to the environment.

We use only the P1 and P3 lines despite the MCS-51 having four output lines, P0--P3.
This is because P0 and P2 become inoperable if the processor is equipped with XRAM (which we assume it is).

The UART port can work in several modes, depending on the how the SFRs are set.
In an asyncrhonous mode, the UART transmits eight bits at a time, using a ninth line for syncrhonization.
In a syncrhonous mode the ninth line is used to transmit an additional bit.

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% SECTION                                                                      %
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsection{Computation of cost traces}
\label{subsect.computation.cost.traces}

As mentioned in Subsection~\ref{subsect.labels.pseudoinstructions} we introduced a notion of \emph{cost label}.
Cost labels are inserted by the prototype C compiler in specific locations in the object code.
Roughly, for those familiar with control flow graphs, they are inserted at the start of every basic block.

Cost labels are used to calculate a precise costing for a program by marking the location of basic blocks.
During the assembly phase, where labels and pseudoinstructions are eliminated, a map is generated associating cost labels with memory locations.
This map is later used in a separate analysis which computes the cost of a program by traversing through a program, fetching one instruction at a time, and computing the cost of blocks.
These block costings are stored in another map, and will later be passed back to the prototype compiler.

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% SECTION                                                                      %
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\section{Validation}
\label{sect.validation}

We spent considerable effort attempting to ensure that our formalisation is correct, that is, what we have formalised really is an accurate model of the MCS-51 microprocessor.

First, we made use of multiple data sheets, each from a different semiconductor manufacturer.
This helped us spot errors in the specification of the processor's instruction set, and its behaviour.

The O'Caml prototype was especially useful for validation purposes.
This is because we wrote a module for parsing and loading the Intel HEX file format.
HEX is a standard format that all compilers targetting the MCS-51, and similar processors, produce.
It is essentially a snapshot of the processor's code memory in compressed form.
Using this, we were able to compile C programs with SDCC, an open source compiler, and load the resulting program directly into our emulator's code memory, ready for execution.
Further, we are able to produce a HEX file from our emulator's code memory, for loading into third party tools.
After each step of execution, we can print out both the instruction that had been executed, along with its arguments, and a snapshot of the processor's state, including all flags and register contents.
For example:
\begin{frametxt}
\begin{verbatim}
...
08: mov 81 #07

 Processor status:                               

   ACC: 0   B: 0   PSW: 0
    with flags set as:
     CY: false  AC: false  FO: false  RS1: false
     RS0: false  OV: false UD: false  P: false
   SP: 7  IP: 0  PC: 8  DPL: 0  DPH: 0  SCON: 0
   SBUF: 0  TMOD: 0  TCON: 0
   Registers:                                    
    R0: 0  R1: 0  R2: 0  R3: 0  R4: 0  R5: 0  R6: 0  R7: 0
...
\end{verbatim}
\end{frametxt}
Here, the traces indicates that the instruction \texttt{mov 81 \#07} has just been executed by the processor, which is now in the state indicated.
These traces were useful in spotting anything that was `obviously' wrong with the execution of the program.

Further, we used MCU 8051 IDE as a reference.
Using our execution traces, we were able to step through a compiled program, one instruction at a time, in MCU 8051 IDE, and compare the resulting execution trace with the trace produced by our emulator.

Our Matita formalisation was largely copied from the O'Caml source code, apart from changes related to addressing modes already mentioned.
However, as the Matita emulator is executable, we could perform further validation by comparing the trace of a program's execution in the Matita emulator with the trace of the same program in the O'Caml emulator.

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% SECTION                                                                      %
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\section{Related work}
\label{sect.related.work}
There exists a large body of literature on the formalisation of microprocessors.
The majority of it aims to prove correctness of the implementation of the microprocessor at the microcode or gate level.
However, we are interested in providing a precise specification of the behaviour of the microprocessor in order to prove the correctness of a compiler which will target the processor.
In particular, we are interested in intensional properties of the processor; precise timings of instruction execution in clock cycles.
Moreover, in addition to formalising the interface of an MCS-51 processor, we have also built a complete MCS-51 ecosystem: the UART, the I/O lines, and hardware timers, along with an assembler.

Similar work to ours can be found in~\cite{fox:trustworthy:2010}.
Here, the authors describe the formalisation, in HOL4, of the ARMv7 instruction set architecture, and point to a good list of references to related work in the literature.
This formalisation also considers the machine code level, as opposed to only considering an abstract assembly language.
In particular, instruction decoding is explicitly modelled inside HOL4's logic.
However, we go further in also providing an assembly language, complete with assembler, to translate instructions and pseudoinstruction to machine code.

Further, in~\cite{fox:trustworthy:2010} the authors validated their formalisation by using development boards and random testing.
However, we currently rely on non-exhaustive testing against a third party emulator.
We leave similar exhaustive testing for future work.

Executability is another key difference between our work and~\cite{fox:trustworthy:2010}.
Our formalisation is executable: applying the emulation function to an input state eventually reduces to an output state that already satisfies the appropriate conditions.
This is because Matita is based on a logic that internalizes conversion.
In~\cite{fox:trustworthy:2010} the authors provide an automation layer to derive single step theorems: if the processor is in a particular state that satisfies some preconditions, then after execution of an instruction it will reside in another state satisfying some postconditions.
We do not need single step theorems of this form.

Our main difficulties resided in the non-uniformity of an old 8-bit architecture, in terms of the instruction set, addressing modes and memory models.
In contrast, the ARM instruction set and memory model is relatively uniform, simplifying any formalisation considerably.

Perhaps the closest project to CerCo is CompCert~\cite{leroy:formal:2009,leroy:formally:2009,blazy:formal:2006}.
CompCert concerns the certification of an ARM compiler and includes a formalisation in Coq of a subset of ARM.
Coq and Matita essentially share the same logic.

Despite this similarity, the two formalisations do not have much in common.
First, CompCert provides a formalisation at the assembly level (no instruction decoding), and this impels them to trust an unformalised assembler and linker, whereas we provide our own.
I/O is also not considered at all in CompCert.
Moreover an idealized abstract and uniform memory model is assumed, while we take into account the complicated overlapping memory model of the MCS-51 architecture.
Finally, around 90 instructions of the 200+ offered by the processor are formalised in CompCert, and the assembly language is augmented with macro instructions that are turned into `real' instructions only during communication with the external assembler.
Even from a technical level the two formalisations differ: while we tried to exploit dependent types as often as possible, CompCert largely sticks to the non-dependent fragment of Coq.

In~\cite{atkey:coqjvm:2007} Atkey presents an executable specification of the Java virtual machine which uses dependent types.
As we do, dependent types are used to remove spurious partiality from the model, and to lower the need for over-specifying the behaviour of the processor in impossible cases.
Our use of dependent types will also help to maintain invariants when we prove the correctness of the CerCo prototype compiler.

Finally, in~\cite{sarkar:semantics:2009} Sarkar et al provide an executable semantics for x86-CC multiprocessor machine code.
This machine code exhibits a high degree of non-uniformity similar to the MCS-51.
However, only a very small subset of the instruction set is considered, and they over-approximate the possibilities of unorthogonality of the instruction set, largely dodging the problems we had to face.

Further, it seems that the definition of the decode function is potentially error prone.
A small domain specific language of patterns is formalised in HOL4.
This is similar to the specification language of the x86 instruction set found in manufacturer's data sheets.
A decode function is implemented by copying lines from data sheets into the proof script.

We are currently considering implementing a similar domain specific language in Matita.
However, we would prefer to certify in Matita the compiler for this language.
Data sheets could then be compiled down to the efficient code that we currently provide, instead of inefficiently interpreting the data sheets every time an instruction is executed.

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% SECTION                                                                      %
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\section{Conclusions}
\label{sect.conclusions}

\CSC{Tell what is NOT formalized/formalizable: the HEX parser/pretty printer
 and/or the I/O procedure}
\CSC{Decode: two implementations}
\CSC{Discuss over-specification}

- WE FORMALIZE ALSO I/O ETC. NOT ONLY THE INSTRUCTION SELECTION (??)
  How to test it? Specify it?

\bibliography{itp-2011.bib}

\end{document}

\newpage

\appendix

\section{Listing of main O'Caml functions}
\label{sect.listing.main.ocaml.functions}

\subsubsection{From \texttt{ASMInterpret.ml(i)}}

\begin{center}
\begin{tabular*}{\textwidth}{p{3cm}@{\quad}p{9cm}}
Name & Description \\
\hline
\texttt{assembly} & Assembles an abstract syntax tree representing an 8051 assembly program into a list of bytes, its compiled form. \\
\texttt{initialize} & Initializes the emulator status. \\
\texttt{load} & Loads an assembled program into the emulator's code memory. \\
\texttt{fetch} & Fetches the next instruction, and automatically increments the program counter. \\
\texttt{execute} & Emulates the processor.  Accepts as input a function that pretty prints the emulator status after every emulation loop. \\
\end{tabular*}
\end{center}

\subsubsection{From \texttt{ASMCosts.ml(i)}}

\begin{center}
\begin{tabular*}{\textwidth}{p{3cm}@{\quad}p{9cm}}
Name & Description \\
\hline
\texttt{compute} & Computes a map associating costings to basic blocks in the program.
\end{tabular*}
\end{center}

\subsubsection{From \texttt{IntelHex.ml(i)}}

\begin{center}
\begin{tabular*}{\textwidth}{p{3cm}@{\quad}p{9cm}}
Name & Description \\
\hline
\texttt{intel\_hex\_of\_file} & Reads in a file and parses it if in Intel IHX format, otherwise raises an exception. \\
\texttt{process\_intel\_hex} & Accepts a parsed Intel IHX file and populates a hashmap (of the same type as code memory) with the contents.
\end{tabular*}
\end{center}

\subsubsection{From \texttt{Physical.ml(i)}}

\begin{center}
\begin{tabular*}{\textwidth}{p{3cm}@{\quad}p{9cm}}
Name & Description \\
\hline
\texttt{subb8\_with\_c} & Performs an eight bit subtraction on bitvectors.  The function also returns the most important PSW flags for the 8051: carry, auxiliary carry and overflow. \\
\texttt{add8\_with\_c} & Performs an eight bit addition on bitvectors.  The function also returns the most important PSW flags for the 8051: carry, auxiliary carry and overflow. \\
\texttt{dec} & Decrements an eight bit bitvector with underflow, if necessary. \\
\texttt{inc} & Increments an eight bit bitvector with overflow, if necessary.
\end{tabular*}
\end{center}

\newpage

\section{Listing of main Matita functions}
\label{sect.listing.main.matita.functions}

\subsubsection{From \texttt{Arithmetic.ma}}

\begin{center}
\begin{tabular*}{\textwidth}{p{3cm}p{9cm}}
Title & Description \\
\hline
\texttt{add\_n\_with\_carry} & Performs an $n$ bit addition on bitvectors.  The function also returns the most important PSW flags for the 8051: carry, auxiliary carry and overflow. \\
\texttt{sub\_8\_with\_carry} & Performs an eight bit subtraction on bitvectors. The function also returns the most important PSW flags for the 8051: carry, auxiliary carry and overflow. \\
\texttt{half\_add} & Performs a standard half addition on bitvectors, returning the result and carry bit. \\
\texttt{full\_add} & Performs a standard full addition on bitvectors and a carry bit, returning the result and a carry bit.
\end{tabular*}
\end{center}

\subsubsection{From \texttt{Assembly.ma}}

\begin{center}
\begin{tabular*}{\textwidth}{p{3cm}p{9cm}}
Title & Description \\
\hline
\texttt{assemble1} & Assembles a single 8051 assembly instruction into its memory representation. \\
\texttt{assemble} & Assembles an 8051 assembly program into its memory representation.\\
\texttt{assemble\_unlabelled\_program} &\\& Assembles a list of (unlabelled) 8051 assembly instructions into its memory representation.
\end{tabular*}
\end{center}

\subsubsection{From \texttt{BitVectorTrie.ma}}

\begin{center}
\begin{tabular*}{\textwidth}{p{3cm}p{9cm}}
Title & Description \\
\hline
\texttt{lookup} & Returns the data stored at the end of a particular path (a bitvector) from the trie.  If no data exists, returns a default value. \\
\texttt{insert} & Inserts data into a tree at the end of the path (a bitvector) indicated.  Automatically expands the tree (by filling in stubs) if necessary.
\end{tabular*}
\end{center}

\subsubsection{From \texttt{DoTest.ma}}

\begin{center}
\begin{tabular*}{\textwidth}{p{3cm}p{9cm}}
Title & Description \\
\hline
\texttt{execute\_trace} & Executes an assembly program for a fixed number of steps, recording in a trace which instructions were executed.
\end{tabular*}
\end{center}

\subsubsection{From \texttt{Fetch.ma}}

\begin{center}
\begin{tabular*}{\textwidth}{p{3cm}p{9cm}}
Title & Description \\
\hline
\texttt{fetch} & Decodes and returns the instruction currently pointed to by the program counter and automatically increments the program counter the required amount to point to the next instruction. \\
\end{tabular*}
\end{center}

\subsubsection{From \texttt{Interpret.ma}}

\begin{center}
\begin{tabular*}{\textwidth}{p{3cm}p{9cm}}
Title & Description \\
\hline
\texttt{execute\_1} & Executes a single step of an 8051 assembly program. \\
\texttt{execute} & Executes a fixed number of steps of an 8051 assembly program.
\end{tabular*}
\end{center}

\subsubsection{From \texttt{Status.ma}}

\begin{center}
\begin{tabular*}{\textwidth}{p{3cm}p{9cm}}
Title & Description \\
\hline
\texttt{load} & Loads an assembled 8051 assembly program into code memory.
\end{tabular*}
\end{center}
\end{document}