source: Deliverables/D4.1/ITP-Paper/itp-2011.tex @ 559

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Added picture from Brian's report on 8051 memory layout

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52\author{Dominic P. Mulligan\thanks{The project CerCo acknowledges the financial support of the Future and
53Emerging Technologies (FET) programme within the Seventh Framework
54Programme for Research of the European Commission, under FET-Open grant
55number: 243881} \and Claudio Sacerdoti Coen$^\star$}
56\authorrunning{D. P. Mulligan and C. Sacerdoti Coen}
57\title{An executable formalisation of the MCS-51 microprocessor in Matita}
58\titlerunning{An executable formalisation of the MCS-51}
59\institute{Dipartimento di Scienze dell'Informazione, Universit\`a di Bologna}
60
61\bibliographystyle{plain}
62
63\begin{document}
64
65\maketitle
66
67\begin{abstract}
68We summarise our formalisation of an emulator for the MCS-51 microprocessor in the Matita proof assistant.
69The MCS-51 is a widely used 8-bit microprocessor, especially popular in embedded devices.
70
71We proceeded in two stages, first implementing in O'Caml a prototype emulator, where bugs could be `ironed out' quickly.
72We then ported our O'Caml emulator to Matita's internal language.
73Though mostly straight-forward, this porting presented multiple problems.
74Of particular interest is how we handle the extreme non-orthoganality of the MSC-51's instruction set.
75In O'Caml, this was handled through heavy use of polymorphic variants.
76In Matita, we achieve the same effect through a non-standard use of dependent types.
77
78Both the O'Caml and Matita emulators are `executable'.
79Assembly programs may be animated within Matita, producing a trace of instructions executed.
80
81Our formalisation is a major component of the ongoing EU-funded CerCo project.
82\end{abstract}
83
84%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
85% SECTION                                                                      %
86%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
87\section{Background}
88\label{sect.introduction}
89
90Formal methods are designed to increase our confidence in the design and implementation of software (and hardware).
91Ideally, we would like all software to come equipped with a formal specification, along with a proof of correctness that the software meets this specification.
92Today the majority of programs are written in high level languages and then compiled into low level ones.
93Specifications are therefore also given at a high level and correctness can be proved by reasoning automatically or interactively on the program's source code.
94The code that is actually run, however, is not the high level source code that we reason on, but the object code that is generated by the compiler.
95A few simple questions now arise:
96\begin{itemize*}
97\item
98What properties are preserved during compilation?
99\item
100What properties are affected by the compilation strategy?
101\item
102To what extent can you trust your compiler in preserving those properties?
103\end{itemize*}
104These questions, and others like them, motivate a current `hot topic' in computer science research: \emph{compiler verification} (for instance~\cite{leroy:formal:2009,chlipala:verified:2010}, and many others).
105So far, the field has been focused on the first and last questions only.
106In particular, much attention has been placed on verifying compiler correctness with respect to extensional properties of programs, which are easily preserved during compilation; it is sufficient to completely preserve the denotational semantics of the input program.
107
108However, if we consider intensional properties of programs---such as space, time or energy spent into computation and transmission of data---the situation is more complex.
109To even be able to express these properties, and to be able to reason about them, we are forced to adopt a cost model that assigns a cost to single, or blocks, of instructions.
110Ideally, we would like to have a compositional cost model that assigns the same cost to all occurrences of one instruction.
111However, compiler optimisations are inherently non-compositional: each occurrence of a high level instruction is usually compiled in a different way according to the context it finds itself in.
112Therefore both the cost model and intensional specifications are affected by the compilation process.
113
114In the current EU project CerCo (`Certified Complexity')~\cite{cerco:2011} we approach the problem of reasoning about intensional properties of programs as follows.
115We are currently developing a compiler that induces a cost model on the high level source code.
116Costs are assigned to each block of high level instructions by considering the costs of the corresponding blocks of compiled object code.
117The cost model is therefore inherently non-compositional.
118However, the model has the potential to be extremely \emph{precise}, capturing a program's \emph{realistic} cost, by taking into account, not ignoring, the compilation process.
119A prototype compiler, where no approximation of the cost is provided, has been developed.
120(The full technical details of the CerCo cost model is explained in~\cite{amadio:certifying:2010}.)
121
122We believe that our approach is especially applicable to certifying real time programs.
123Here, a user can certify that all `deadlines' are met whilst wringing as many clock cycles from the processor---using a cost model that does not over-estimate---as possible.
124
125Further, we see our approach as being relevant to the field of compiler verification (and construction) itself.
126For instance, an optimisation specified only extensionally is only half specified; though the optimisation may preserve the denotational semantics of a program, there is no guarantee that any intensional properties of the program, such as space or time usage, will be improved.
127Another potential application is toward completeness and correctness of the compilation process in the presence of space constraints.
128Here, a compiler could potentially reject a source program targetting an embedded system when the size of the compiled code exceeds the available ROM size.
129Moreover, preservation of a program's semantics may only be required for those programs that do not exhaust the stack or heap.
130Hence the statement of completeness of the compiler must take in to account a realistic cost model.
131
132In the methodology proposed in CerCo we assume we are able to compute on the object code exact and realistic costs for sequential blocks of instructions.
133With modern processors, though possible (see~\cite{bate:wcet:2011,yan:wcet:2008} for instance), it is difficult to compute exact costs or to reasonably approximate them.
134This is because the execution of a program itself has an influence on the speed of processing.
135For instance, caching, memory effects and other advanced features such as branch prediction all have a profound effect on execution speeds.
136For this reason CerCo decided to focus on 8-bit microprocessors.
137These are still widely used in embedded systems, and have the advantage of an easily predictable cost model due to the relative sparcity of features that they possess.
138
139In particular, we have fully formalised an executable formal semantics of a family of 8 bit Freescale Microprocessors~\cite{oliboni:matita:2008}, and provided a similar executable formal semantics for the MCS-51 microprocessor.
140The latter work is what we describe in this paper.
141The main focus of the formalisation has been on capturing the intensional behaviour of the processor.
142However, the design of the MCS-51 itself has caused problems in our formalisation.
143For example, the MCS-51 has a highly unorthogonal instruction set.
144To cope with this unorthogonality, and to produce an executable specification, we have exploited the dependent type system of Matita, an interactive proof assistant.
145
146\subsection{The 8051/8052}
147\label{subsect.8051-8052}
148
149The MCS-51 is an eight bit microprocessor introduced by Intel in the late 1970s.
150Commonly called the 8051, in the three decades since its introduction the processor has become a highly popular target for embedded systems engineers.
151Further, the processor, its immediate successor the 8052, and many derivatives are still manufactured \emph{en masse} by a host of semiconductor suppliers.
152
153The 8051 is a well documented processor, and has the additional support of numerous open source and commercial tools, such as compilers for high-level languages and emulators.
154For instance, the open source Small Device C Compiler (SDCC) recognises a dialect of C~\cite{sdcc:2010}, and other compilers targeting the 8051 for BASIC, Forth and Modula-2 are also extant.
155An open source emulator for the processor, MCU-8051 IDE, is also available~\cite{mcu8051ide:2010}.
156Both MCU-8051 IDE and SDCC were used profitably in the implementation of our formalisation.
157
158\begin{figure}[t]
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225\end{picture}
226\caption{The 8051 memory model}
227\label{fig.memory.layout}
228\end{figure}
229
230The 8051 has a relatively straightforward architecture, unencumbered by advanced features of modern processors, making it an ideal target for formalisation.
231A high-level overview of the processor's memory layout, along with the ways in which different memory spaces may be addressed, is provided in Figure~\ref{fig.memory.layout}.
232
233Processor RAM is divided into numerous segments, with the most prominent division being between internal and (optional) external memory.
234Internal memory, commonly provided on the die itself with fast access, is composed of 256 bytes, but, in direct addressing mode, half of them are overloaded with 128 bytes of memory mapped Special Function Registers (SFRs) which control the operation of the processor.
235Internal RAM (IRAM) is further divided into eight general purpose bit-addressable registers (R0--R7).
236These sit in the first eight bytes of IRAM, though can be programmatically `shifted up' as needed.
237Bit memory, followed by a small amount of stack space, resides in the memory space immediately after the register banks.
238What remains of the IRAM may be treated as general purpose memory.
239A schematic view of IRAM layout is also provided in Figure~\ref{fig.memory.layout}.
240
241External RAM (XRAM), limited to a maximum size of 64 kilobytes, is optional, and may be provided on or off chip, depending on the manufacturer.
242XRAM is accessed using a dedicated instruction, and requires sixteen bits to address fully.
243External code memory (XCODE) is often stored in the form of an EPROM, and limited to 64 kilobytes in size.
244However, depending on the particular manufacturer and processor model, a dedicated on-die read-only memory area for program code (ICODE) may also be supplied.
245
246Memory may be addressed in numerous ways: immediate, direct, indirect, external direct and code indirect.
247As the latter two addressing modes hint, there are some restrictions enforced by the 8051 and its derivatives on which addressing modes may be used with specific types of memory.
248For instance, the 128 bytes of extra internal RAM that the 8052 features cannot be addressed using indirect addressing; rather, external (in)direct addressing must be used. Moreover, some memory segments are addressed using 8 bits pointers while others require 16 bits.
249
250The 8051 series possesses an eight bit Arithmetic and Logic Unit (ALU), with a wide variety of instructions for performing arithmetic and logical operations on bits and integers.
251Further, the processor possesses two eight bit general purpose accumulators, A and B.
252
253Communication with the device is facilitated by an onboard UART serial port, and associated serial controller, which can operate in numerous modes.
254Serial baud rate is determined by one of two sixteen bit timers included with the 8051, which can be set to multiple modes of operation.
255(The 8052 provides an additional sixteen bit timer.)
256As an additional method of communication, the 8051 also provides a four byte bit-addressable input-output port.
257
258The programmer may take advantage of the interrupt mechanism that the processor provides.
259This is especially useful when dealing with input or output involving the serial device, as an interrupt can be set when a whole character is sent or received via the serial port.
260
261Interrupts immediately halt the flow of execution of the processor, and cause the program counter to jump to a fixed address, where the requisite interrupt handler is stored.
262However, interrupts may be set to one of two priorities: low and high.
263The interrupt handler of an interrupt with high priority is executed ahead of the interrupt handler of an interrupt of lower priority, interrupting a currently executing handler of lower priority, if necessary.
264
265The 8051 has interrupts disabled by default.
266The programmer is free to handle serial input and output manually, by poking serial flags in the SFRs.
267Similarly, `exceptional circumstances' that would otherwise trigger an interrupt on more modern processors, for example, division by zero, are also signalled by setting flags.
268
269%\begin{figure}[t]
270%\begin{center}
271%\includegraphics[scale=0.5]{iramlayout.png}
272%\end{center}
273%\caption{Schematic view of 8051 IRAM layout}
274%\label{fig.iram.layout}
275%\end{figure}
276
277%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
278% SECTION                                                                      %
279%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
280\subsection{Overview of paper}
281\label{subsect.overview.paper}
282
283In Section~\ref{sect.design.issues.formalisation} we discuss design issues in the development of the formalisation.
284In Section~\ref{sect.validation} we discuss how we validated the design and implementation of our emulator to ensure that what we formalised was an accurate model of an MCS-51 series microprocessor.
285In Section~\ref{sect.related.work} we describe previous work, with an eye toward describing its relation with the work described herein.
286In Section~\ref{sect.conclusions} we conclude the paper.
287
288%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
289% SECTION                                                                      %
290%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
291\section{Design issues in the formalisation}
292\label{sect.design.issues.formalisation}
293
294From hereonin, we typeset O'Caml source with \texttt{\color{blue}{blue}} and Matita source with \texttt{\color{red}{red}} to distinguish the two syntaxes.
295Matita's syntax is largely straightforward to those familiar with Coq or O'Caml.
296The only subtlety is the use of `\texttt{?}' in an argument position denoting an argument that should be inferred automatically.
297
298A full account of the formalisation can be found in~\cite{cerco-report:2011}.
299
300\subsection{Development strategy}
301\label{subsect.development.strategy}
302
303Our implementation progressed in two stages.
304We began with an emulator written in O'Caml.
305We used this to `iron out' any bugs in our design and implementation within O'Caml's more permissive type system.
306O'Caml's ability to perform file input-output also eased debugging and validation.
307Once we were happy with the performance and design of the O'Caml emulator, we moved to the Matita formalisation.
308
309Matita's syntax is lexically similar to O'Caml's.
310This eased the translation, as large swathes of code were merely copy-pasted with minor modifications.
311However, several major issues had to be addresses when moving from O'Caml to Matita.
312These are now discussed.
313
314%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
315% SECTION                                                                      %
316%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
317\subsection{Representation of bytes, words, etc.}
318\label{subsect.representation.integers}
319
320\begin{figure}[t]
321\begin{minipage}[t]{0.45\textwidth}
322\vspace{0pt}
323\begin{lstlisting}
324type 'a vect = bit list
325type nibble = [`Sixteen] vect
326type byte = [`Eight] vect
327$\color{blue}{\mathtt{let}}$ split_word w = split_nth 4 w
328$\color{blue}{\mathtt{let}}$ split_byte b = split_nth 2 b
329\end{lstlisting}
330\end{minipage}
331%
332\begin{minipage}[t]{0.55\textwidth}
333\vspace{0pt}
334\begin{lstlisting}
335type 'a vect
336type word = [`Sixteen] vect
337type byte = [`Eight] vect
338val split_word: word -> byte * word
339val split_byte: byte -> nibble * nibble
340\end{lstlisting}
341\end{minipage}
342\caption{Sample of O'Caml implementation and interface for bitvectors module}
343\label{fig.ocaml.implementation.bitvectors}
344\end{figure}
345
346The formalization of MCS-51 must deal with bytes (8 bits), words (16 bits) but also with more exoteric quantities (7 bits, 3 bits, 9 bits).
347To avoid size mismatch bugs difficult to spot, we represent all of these quantities using bitvectors, i.e. fixed length vectors of booleans.
348In our O'Caml emulator, we `faked' bitvectors using phantom types~\cite{leijen:domain:1999} implemented with polymorphic variants~\cite{garrigue:programming:1998}, as in Figure~\ref{fig.ocaml.implementation.bitvectors}.
349From within the bitvector module (left column) bitvectors are just lists of bits and no guarantee is provided on sizes.
350However, the module's interface (right column) enforces the size invariants in the rest of the code.
351
352In Matita, we are able to use the full power of dependent types to always work with vectors of a known size:
353\begin{lstlisting}
354inductive Vector (A: Type[0]): nat → Type[0] ≝
355  VEmpty: Vector A O
356| VCons: ∀n: nat. A → Vector A n → Vector A (S n).
357\end{lstlisting}
358We define \texttt{BitVector} as a specialization of \texttt{Vector} to \texttt{bool}.
359We may use Matita's type system to provide precise typing for functions that are
360polymorphic in the size without having to duplicate the code as we did in O'Caml:
361\begin{lstlisting}
362let rec split (A: Type[0]) (m,n: nat) on m:
363   Vector A (plus m n) $\rightarrow$ (Vector A m) $\times$ (Vector A n) := ...
364\end{lstlisting}
365
366%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
367% SECTION                                                                      %
368%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
369\subsection{Representing memory}
370\label{subsect.representing.memory}
371
372The MCS-51 has numerous disjoint memory segments addressed by pointers of
373different sizes.
374In our prototype implementation, we simply used a map datastructure (from the O'Caml standard library) for each segment.
375Matita's standard library is relatively small, and does not contain a generic map datastructure. Therefore, we had the opportunity of crafting a dependently typed special-purpose datastructure for the job to enforce the correspondence between the size of pointers and the size of the segment .
376We also worked under the assumption that large swathes of memory would often be uninitialized, trying to represent them concisely using stubs.
377
378We picked a modified form of trie of fixed height $h$ where paths are
379represented by bitvectors of length $h$, that are already used in our
380implementation for addresses and registers:
381\begin{lstlisting}
382inductive BitVectorTrie (A: Type[0]): nat $\rightarrow$ Type[0] ≝
383  Leaf: A $\rightarrow$ BitVectorTrie A 0
384| Node: ∀n. BitVectorTrie A n $\rightarrow$ BitVectorTrie A n $\rightarrow$ BitVectorTrie A (S n)
385| Stub: ∀n. BitVectorTrie A n.
386\end{lstlisting}
387Here, \texttt{Stub} is a constructor that can appear at any point in our tries.
388It internalises the notion of `uninitialized data'.
389Performing a lookup in memory is now straight-forward.
390We merely traverse a path, and if at any point we encounter a \texttt{Stub}, we return a default value\footnote{All manufacturer data sheets that we consulted were silent on the subject of what should be returned if we attempt to access uninitialized memory.  We defaulted to simply returning zero, though our \texttt{lookup} function is parametric in this choice.  We do not believe that this is an outrageous decision, as SDCC for instance generates code which first `zeroes out' all memory in a preamble before executing the program proper.  This is in line with the C standard, which guarantees that all global variables will be zero initialized piecewise.}.
391
392%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
393% SECTION                                                                      %
394%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
395\subsection{Labels and pseudoinstructions}
396\label{subsect.labels.pseudoinstructions}
397
398Aside from implementing the core MCS-51 instruction set, we also provided \emph{pseudoinstructions}, \emph{labels} and \emph{cost labels}.
399The purpose of \emph{cost labels} will be explained in Subsection~\ref{subsect.computation.cost.traces}.
400
401Introducing pseudoinstructions had the effect of simplifying a C compiler---another component of the CerCo project---that was being implemented in parallel with our implementation.
402To understand why this is so, consider the fact that the MCS-51's instruction set has numerous instructions for unconditional and conditional jumps to memory locations.
403For instance, the instructions \texttt{AJMP}, \texttt{JMP} and \texttt{LJMP} all perform unconditional jumps.
404However, these instructions differ in how large the maximum size of the offset of the jump to be performed can be.
405Further, all jump instructions require a concrete memory address---to jump to---to be specified.
406Hence compilers that support separate compilation cannot directly compute these offsets and select the appropriate jump instructions. These operations are
407needleslly burdensome also for compilers that do not do separate compilation
408and are thus handled by the assemblers, as we decided to do.
409
410While introducing pseudo instructions we also introduced labels for locations
411for jumps and for global data.
412To specify global data via labels, we have introduced the notion of a preamble
413before the program to hold the association of labels to sizes of reserved space.
414A pseudoinstruction \texttt{Mov} moves (16-bit) data stored at a label into the (16-bit) register \texttt{DPTR}.
415
416Our pseudoinstructions and labels induce an assembly language similar to that of SDCC. All pseudoinstructions and labels are `assembled away', prior to program execution, using a preprocessing stage. Jumps are computed in two stages.
417The first stage builds a map associating memory addresses to labels, with the second stage removing pseudojumps with concrete jumps to the correct address. The algorithm currently implemented does not try to minimize the object code size by always picking the shortest possible jump instruction. The choice of an optimal algorithm is currently left as future work.
418
419%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
420% SECTION                                                                      %
421%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
422\subsection{Anatomy of the (Matita) emulator}
423\label{subsect.anatomy.matita.emulator}
424
425The internal state of our Matita emulator is represented as a record:
426\begin{lstlisting}
427record Status: Type[0] ≝
428{
429  code_memory: BitVectorTrie Byte 16;
430  low_internal_ram: BitVectorTrie Byte 7;
431  high_internal_ram: BitVectorTrie Byte 7;
432  external_ram: BitVectorTrie Byte 16;
433  program_counter: Word;
434  special_function_registers_8051: Vector Byte 19;
435  special_function_registers_8052: Vector Byte 5;
436  ...
437}.
438\end{lstlisting}
439This record neatly encapsulates the current memory contents, the program counter, the state of the current SFRs, and so on.
440One peculiarity is the packing of the 24 combined SFRs into fixed length vectors.
441This was due to a bug in Matita when we were constructing the emulator, since fixed, where the time needed to typecheck a record grew exponentially with the number of fields.
442
443Here, it appears that the MCS-51's memory spaces are completely disjoint.
444This is not so; many of them overlap with each other, and there's a many-many relationship between addressing modes and memory spaces.
445For instance, \texttt{DIRECT} addressing can be used to address low internal RAM and the SFRs, but not high internal RAM.
446
447For simplicity, we merely treat memory spaces as if they are completely disjoint in the \texttt{Status} record.
448Overlapping, and checking which addressing modes can be used to address particular memory spaces, is handled through numerous \texttt{get\_arg\_XX} and \texttt{set\_arg\_XX} (for 1, 8 and 16 bits) functions.
449
450Both the Matita and O'Caml emulators follows the classic `fetch-decode-execute' model of processor operation.
451The next instruction to be processed, indexed by the program counter, is fetched from code memory with \texttt{fetch}.
452An updated program counter, along with the concrete cost, in processor cycles for executing this instruction, is also returned.
453These costs are taken from a Siemens Semiconductor Group data sheet for the MCS-51~\cite{siemens:2011}, and will likely vary across manufacturers and particular derivatives of the processor.
454\begin{lstlisting}
455definition fetch:
456  BitVectorTrie Byte 16 $\rightarrow$ Word $\rightarrow$ instruction $\times$ Word $\times$ nat := ...
457\end{lstlisting}
458A single instruction is assembled into its corresponding bit encoding with \texttt{assembly1}:
459\begin{lstlisting}
460definition assembly1: instruction $\rightarrow$ list Byte := ...
461\end{lstlisting}
462An assembly program, consisting of a preamble containing global data, and a list of (pseudo)instructions, is assembled using \texttt{assembly}.
463Pseudoinstructions and labels are eliminated in favour of concrete instructions from the MCS-51 instruction set.
464A map associating memory locations and cost labels (see Subsection~\ref{subsect.computation.cost.traces}) is also produced.
465\begin{lstlisting}
466definition assembly:
467  assembly_program $\rightarrow$ option (list Byte $\times$ (BitVectorTrie String 16)) := ...
468\end{lstlisting}
469A single execution step of the processor is evaluated using \texttt{execute\_1}, mapping a \texttt{Status} to a \texttt{Status}:
470\begin{lstlisting}
471definition execute_1: Status $\rightarrow$ Status := ...
472\end{lstlisting}
473Multiple steps of processor execution are implemented in \texttt{execute}, which wraps \texttt{execute\_1}:
474\begin{lstlisting}
475let rec execute (n: nat) (s: Status) on n: Status := ...
476\end{lstlisting}
477This differs slightly from the design of the O'Caml emulator, which executed a program indefinitely, and also accepted a callback function as an argument, which could `witness' the execution as it happened, and providing a print-out of the processor state, and other debugging information.
478Due to Matita's requirement that all functions be strongly normalizing, \texttt{execute} cannot execute a program indefinitely, and must execute a fixed number of steps.
479
480%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
481% SECTION                                                                      %
482%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
483\subsection{Instruction set unorthogonality}
484\label{subsect.instruction.set.unorthogonality}
485
486A peculiarity of the MCS-51 is the non-orthogonality of its instruction set.
487For instance, the \texttt{MOV} instruction, can be invoked using one of sixteen combinations of addressing modes.
488
489% Show example of pattern matching with polymorphic variants
490
491Such non-orthogonality in the instruction set was handled with the use of polymorphic variants in the O'Caml emulator.
492For instance, we introduced types corresponding to each addressing mode:
493\begin{lstlisting}
494type direct = [ `DIRECT of byte ]
495type indirect = [ `INDIRECT of bit ]
496...
497\end{lstlisting}
498Which were then used in our inductive datatype for assembly instructions, as follows:
499\begin{lstlisting}
500type 'addr preinstruction =
501 [ `ADD of acc * [ reg | direct | indirect | data ]
502...
503 | `MOV of
504    (acc * [ reg | direct | indirect | data ],
505     [ reg | indirect ] * [ acc | direct | data ],
506     direct * [ acc | reg | direct | indirect | data ],
507     dptr * data16,
508     carry * bit,
509     bit * carry
510     ) union6
511...
512\end{lstlisting}
513Here, \texttt{union6} is a disjoint union type, defined as follows:
514\begin{lstlisting}
515type ('a,'b,'c,'d,'e,'f) union6 = [ `U1 of 'a | ... | `U6 of 'f ]
516\end{lstlisting}
517For our purposes, the types \texttt{union2}, \texttt{union3} and \texttt{union6} sufficed.
518
519This polymorphic variant machinery worked well: it introduced a certain level of type safety (for instance, the type of our \texttt{MOV} instruction above guarantees it cannot be invoked with arguments in the \texttt{carry} and \texttt{data16} addressing modes, respectively), and also allowed us to pattern match against instructions, when necessary.
520However, this polymorphic variant machinery is \emph{not} present in Matita.
521We needed some way to produce the same effect, which Matita supported.
522For this task, we used dependent types.
523
524We first provided an inductive data type representing all possible addressing modes, a type that functions will pattern match against:
525\begin{lstlisting}
526inductive addressing_mode: Type[0] ≝
527  DIRECT: Byte $\rightarrow$ addressing_mode
528| INDIRECT: Bit $\rightarrow$ addressing_mode
529...
530\end{lstlisting}
531We also wished to express in the type of functions the \emph{impossibility} of pattern matching against certain constructors.
532In order to do this, we introduced an inductive type of addressing mode `tags'.
533The constructors of \texttt{addressing\_mode\_tag} are in one-to-one correspondence with the constructors of \texttt{addressing\_mode}:
534\begin{lstlisting}
535inductive addressing_mode_tag : Type[0] ≝
536  direct: addressing_mode_tag
537| indirect: addressing_mode_tag
538...
539\end{lstlisting}
540A function that checks whether an \texttt{addressing\_mode} is `morally' an \texttt{addressing\_mode\_tag} is provided, as follows:
541\begin{lstlisting}
542let rec is_a (d: addressing_mode_tag) (A: addressing_mode) on d :=
543  match d with
544   [ direct $\Rightarrow$ match A with [ DIRECT _ $\Rightarrow$ true | _ $\Rightarrow$ false ]
545   | indirect $\Rightarrow$ match A with [ INDIRECT _ $\Rightarrow$ true | _ $\Rightarrow$ false ]
546...
547\end{lstlisting}
548We also extend this check to vectors of \texttt{addressing\_mode\_tag}'s in the obvious manner:
549\begin{lstlisting}
550let rec is_in (n: nat) (l: Vector addressing_mode_tag n) (A: addressing_mode) on l :=
551 match l return $\lambda$m.$\lambda$_: Vector addressing_mode_tag m. bool with
552  [ VEmpty $\Rightarrow$ false
553  | VCons m he (tl: Vector addressing_mode_tag m) $\Rightarrow$
554     is_a he A $\vee$ is_in ? tl A ].
555\end{lstlisting}
556Here $\mathtt{\vee}$ is inclusive disjunction on the \texttt{bool} datatype.
557\begin{lstlisting}
558record subaddressing_mode (n: nat) (l: Vector addressing_mode_tag (S n)): Type[0] :=
559{
560  subaddressing_modeel :> addressing_mode;
561  subaddressing_modein: bool_to_Prop (is_in ? l subaddressing_modeel)
562}.
563\end{lstlisting}
564We can now provide an inductive type of preinstructions with precise typings:
565\begin{lstlisting}
566inductive preinstruction (A: Type[0]): Type[0] ≝
567   ADD: $\llbracket$ acc_a $\rrbracket$ $\rightarrow$ $\llbracket$ register; direct; indirect; data $\rrbracket$ $\rightarrow$ preinstruction A
568 | ADDC: $\llbracket$ acc_a $\rrbracket$ $\rightarrow$ $\llbracket$ register; direct; indirect; data $\rrbracket$ $\rightarrow$ preinstruction A
569...
570\end{lstlisting}
571Here $\llbracket - \rrbracket$ is syntax denoting a vector.
572We see that the constructor \texttt{ADD} expects two parameters, the first being the accumulator A (\texttt{acc\_a}), and the second being one of a register, direct, indirect or data addressing mode.
573
574% One of these coercions opens up a proof obligation which needs discussing
575% Have lemmas proving that if an element is a member of a sub, then it is a member of a superlist, and so on
576The final, missing component is a pair of type coercions from \texttt{addressing\_mode} to \texttt{subaddressing\_mode} and from \texttt{subaddressing\_mode} to \texttt{Type$\lbrack0\rbrack$}, respectively.
577The latter coercion is largely straightforward, however the former is not:
578\begin{lstlisting}
579coercion mk_subaddressing_mode:
580  $\forall$n.  $\forall$l: Vector addressing_mode_tag (S n).
581  $\forall$a: addressing_mode.
582  $\forall$p: bool_to_Prop (is_in ? l a). subaddressing_mode n l :=
583    mk_subaddressing_mode on a: addressing_mode to subaddressing_mode ? ?.
584\end{lstlisting}
585Using this coercion opens a proof obligation wherein we must prove that the \texttt{addressing\_mode\_tag} in correspondence with the \texttt{addressing\_mode} is a member of the \texttt{Vector} of permissible \texttt{addressing\_mode\_tag}s.
586This impels us to state and prove a number of auxilliary lemmas.
587For instance, we prove that if an \texttt{addressing\_mode\_tag} is a member of a \texttt{Vector}, and we possess another vector with additional elements, then the same \texttt{addressing\_mode\_tag} is a member of this vector.
588Using these lemmas, and Matita's automation, all proof obligations are solved easily.
589(Type checking the main \texttt{execute\_1} function, for instance, opens up over 200 proof obligations.)
590
591The machinery just described allows us to state in the type of a function what addressing modes that function expects.
592For instance, consider \texttt{set\_arg\_16}, which expects only a \texttt{DPTR}:
593\begin{lstlisting}
594definition set_arg_16: Status $\rightarrow$ Word $\rightarrow$ $\llbracket$ dptr $\rrbracket$ $\rightarrow$ Status ≝
595  $\lambda$s, v, a.
596   match a return $\lambda$x. bool_to_Prop (is_in ? $\llbracket$ dptr $\rrbracket$ x) $\rightarrow$ ? with
597     [ DPTR $\Rightarrow$ $\lambda$_: True.
598       let 〈 bu, bl 〉 := split $\ldots$ eight eight v in
599       let status := set_8051_sfr s SFR_DPH bu in
600       let status := set_8051_sfr status SFR_DPL bl in
601         status
602     | _ $\Rightarrow$ $\lambda$_: False.
603       match K in False with
604       [
605       ]
606     ] (subaddressing_modein $\ldots$ a).
607\end{lstlisting}
608All other cases are discharged by the catch-all at the bottom of the match expression.
609Attempting to match against another addressing mode not indicated in the type (for example, \texttt{REGISTER}) will produce a type-error.
610
611% Talk about extraction to O'Caml code, which hopefully will allow us to extract back to using polymorphic variants, or when extracting vectors we could extract using phantom types
612% Discuss alternative approaches, i.e. Sigma types to piece together smaller types into larger ones, as opposed to using a predicate to `cut out' pieces of a larger type, which is what we did
613
614%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
615% SECTION                                                                      %
616%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
617\subsection{I/O and timers}
618\label{subsect.i/o.timers}
619
620% `Real clock' for I/O and timers
621The O'Caml emulator has code for handling timers, asynchronous I/O and interrupts (these are not yet ported to the Matita emulator).
622All three of these features interact with each other in subtle ways.
623For instance, interrupts can `fire' when an input is detected on the processor's UART port, and, in certain modes, timers reset when a high signal is detected on one of the MCS-51's communication pins.
624
625To accurately model timers and I/O, we add an unbounded integral field \texttt{clock} to the central \texttt{status} record.
626This field is only logical, since it does not represent any quantity stored in the actual processor, and is used to keep track of the current processor time.
627Before every execution step, \texttt{clock} is incremented by the number of processor cycles that the instruction just fetched will take to execute.
628The processor then executes the instruction, followed by the code implementing the timers and I/O\footnote{Though it isn't fully specified by the manufacturer's data sheets if I/O is handled at the beginning or the end of each cycle.}. In order to model I/O, we also store in the status a
629We use \emph{continuation} as a description of the behaviour of the environment:
630\begin{lstlisting}
631type line =
632  [ `P1 of byte | `P3 of byte
633  | `SerialBuff of [ `Eight of byte | `Nine of BitVectors.bit * byte ]]
634type continuation =
635  [`In of time * line * epsilon * continuation] option *
636  [`Out of (time -> line -> time * continuation)]
637\end{lstlisting}
638At each moment, the second projection of the continuation $k$ describes how the environment will react to an output event performed in the future by the processor.
639If the processor at time $\tau$ starts an asynchronous output $o$ either on the P1 or P3 output lines, or on the UART, then the environment will receive the output at time $\tau'$.
640Moreover the status is immediately updated with the continuation $k'$ where $\pi_2(k)(\tau,o) = \langle \tau',k' \rangle$.
641
642Further, if $\pi_1(k) = \mathtt{Some}~\langle \tau',i,\epsilon,k'\rangle$, then at time $\tau'$ the environment will send the asynchronous input $i$ to the processor and the status will be updated with the continuation $k'$.
643This input will become visible to the processor only at time $\tau' + \epsilon$.
644
645The time required to perform an I/O operation is partially specified in the data sheets of the UART module.
646However, this computation is complex so we prefer to abstract over it.
647We therefore leave the computation of the delay time to the environment.
648
649We use only the P1 and P3 lines despite the MCS-51 having four output lines, P0--P3.
650This is because P0 and P2 become inoperable if the processor is equipped with XRAM (which we assume it is).
651
652The UART port can work in several modes, depending on the how the SFRs are set.
653In an asyncrhonous mode, the UART transmits eight bits at a time, using a ninth line for syncrhonization.
654In a syncrhonous mode the ninth line is used to transmit an additional bit.
655
656%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
657% SECTION                                                                      %
658%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
659\subsection{Computation of cost traces}
660\label{subsect.computation.cost.traces}
661
662As mentioned in Subsection~\ref{subsect.labels.pseudoinstructions} we introduced a notion of \emph{cost label}.
663Cost labels are inserted by the prototype C compiler in specific locations in the object code.
664Roughly, for those familiar with control flow graphs, they are inserted at the start of every basic block.
665
666Cost labels are used to calculate a precise costing for a program by marking the location of basic blocks.
667During the assembly phase, where labels and pseudoinstructions are eliminated, a map is generated associating cost labels with memory locations.
668This map is later used in a separate analysis which computes the cost of a program by traversing through a program, fetching one instruction at a time, and computing the cost of blocks.
669These block costings are stored in another map, and will later be passed back to the prototype compiler.
670
671%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
672% SECTION                                                                      %
673%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
674\section{Validation}
675\label{sect.validation}
676
677We spent considerable effort attempting to ensure that our formalisation is correct, that is, what we have formalised really is an accurate model of the MCS-51 microprocessor.
678
679First, we made use of multiple data sheets, each from a different semiconductor manufacturer.
680This helped us spot errors in the specification of the processor's instruction set, and its behaviour.
681
682The O'Caml prototype was especially useful for validation purposes.
683This is because we wrote a module for parsing and loading the Intel HEX file format.
684HEX is a standard format that all compilers targetting the MCS-51, and similar processors, produce.
685It is essentially a snapshot of the processor's code memory in compressed form.
686Using this, we were able to compile C programs with SDCC, an open source compiler, and load the resulting program directly into our emulator's code memory, ready for execution.
687Further, we are able to produce a HEX file from our emulator's code memory, for loading into third party tools.
688After each step of execution, we can print out both the instruction that had been executed, along with its arguments, and a snapshot of the processor's state, including all flags and register contents.
689For example:
690\begin{frametxt}
691\begin{verbatim}
692...
693
69408: mov 81 #07
695
696 Processor status:                               
697
698   ACC : 0 (00000000) B   : 0 (00000000) PSW : 0 (00000000)
699    with flags set as:
700     CY  : false   AC  : false FO  : false
701     RS1 : false   RS0 : false OV  : false
702     UD  : false   P   : false
703   SP  : 7 (00000111) IP  : 0 (00000000)
704   PC  : 8 (0000000000001000)
705   DPL : 0 (00000000) DPH : 0 (00000000) SCON: 0 (00000000)
706   SBUF: 0 (00000000) TMOD: 0 (00000000) TCON: 0 (00000000)
707   Registers:                                   
708    R0 : 0 (00000000) R1 : 0 (00000000) R2 : 0 (00000000)
709    R3 : 0 (00000000) R4 : 0 (00000000) R5 : 0 (00000000)
710    R6 : 0 (00000000) R7 : 0 (00000000)
711
712...
713\end{verbatim}
714\end{frametxt}
715Here, the traces indicates that the instruction \texttt{mov 81 \#07} has just been executed by the processor, which is now in the state indicated.
716These traces were useful in spotting anything that was `obviously' wrong with the execution of the program.
717
718Further, we used MCU 8051 IDE as a reference.
719Using our execution traces, we were able to step through a compiled program, one instruction at a time, in MCU 8051 IDE, and compare the resulting execution trace with the trace produced by our emulator.
720
721Our Matita formalisation was largely copied from the O'Caml source code, apart from changes related to addressing modes already mentioned.
722However, as the Matita emulator is executable, we could perform further validation by comparing the trace of a program's execution in the Matita emulator with the trace of the same program in the O'Caml emulator.
723
724%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
725% SECTION                                                                      %
726%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
727\section{Related work}
728\label{sect.related.work}
729There exists a large body of literature on the formalisation of microprocessors.
730The majority of it aims to prove correctness of the implementation of the microprocessor at the microcode or gate level.
731However, we are interested in providing a precise specification of the behaviour of the microprocessor in order to prove the correctness of a compiler which will target the processor.
732In particular, we are interested in intensional properties of the processor; precise timings of instruction execution in clock cycles.
733Moreover, in addition to formalising the interface of an MCS-51 processor, we have also built a complete MCS-51 ecosystem: the UART, the I/O lines, and hardware timers, along with an assembler.
734
735Similar work to ours can be found in~\cite{fox:trustworthy:2010}.
736Here, the authors describe the formalisation, in HOL4, of the ARMv7 instruction set architecture, and point to a good list of references to related work in the literature.
737This formalisation also considers the machine code level, as opposed to only considering an abstract assembly language.
738In particular, instruction decoding is explicitly modelled inside HOL4's logic.
739However, we go further in also providing an assembly language, complete with assembler, to translate instructions and pseudoinstruction to machine code.
740
741Further, in~\cite{fox:trustworthy:2010} the authors validated their formalisation by using development boards and random testing.
742However, we currently rely on non-exhaustive testing against a third party emulator.
743We leave similar exhaustive testing for future work.
744
745Executability is another key difference between our work and~\cite{fox:trustworthy:2010}.
746Our formalisation is executable: applying the emulation function to an input state eventually reduces to an output state that already satisfies the appropriate conditions.
747This is because Matita is based on a logic that internalizes conversion.
748In~\cite{fox:trustworthy:2010} the authors provide an automation layer to derive single step theorems: if the processor is in a particular state that satisfies some preconditions, then after execution of an instruction it will reside in another state satisfying some postconditions.
749We do not need single step theorems of this form.
750
751Our main difficulties resided in the non-uniformity of an old 8-bit architecture, in terms of the instruction set, addressing modes and memory models.
752In contrast, the ARM instruction set and memory model is relatively uniform, simplifying any formalisation considerably.
753
754Perhaps the closest project to CerCo is CompCert~\cite{leroy:formal:2009,leroy:formally:2009,blazy:formal:2006}.
755CompCert concerns the certification of an ARM compiler and includes a formalisation in Coq of a subset of ARM.
756Coq and Matita essentially share the same logic.
757
758Despite this similarity, the two formalisations do not have much in common.
759First, CompCert provides a formalisation at the assembly level (no instruction decoding), and this impels them to trust an unformalised assembler and linker, whereas we provide our own.
760I/O is also not considered at all in CompCert.
761Moreover an idealized abstract and uniform memory model is assumed, while we take into account the complicated overlapping memory model of the MCS-51 architecture.
762Finally, around 90 instructions of the 200+ offered by the processor are formalised in CompCert, and the assembly language is augmented with macro instructions that are turned into `real' instructions only during communication with the external assembler.
763Even from a technical level the two formalisations differ: while we tried to exploit dependent types as often as possible, CompCert largely sticks to the non-dependent fragment of Coq.
764
765In~\cite{atkey:coqjvm:2007} Atkey presents an executable specification of the Java virtual machine which uses dependent types.
766As we do, dependent types are used to remove spurious partiality from the model, and to lower the need for over-specifying the behaviour of the processor in impossible cases.
767Our use of dependent types will also help to maintain invariants when we prove the correctness of the CerCo prototype compiler.
768
769Finally, in~\cite{sarkar:semantics:2009} Sarkar et al provide an executable semantics for x86-CC multiprocessor machine code.
770This machine code exhibits a high degree of non-uniformity similar to the MCS-51.
771However, only a very small subset of the instruction set is considered, and they over-approximate the possibilities of unorthogonality of the instruction set, largely dodging the problems we had to face.
772
773Further, it seems that the definition of the decode function is potentially error prone.
774A small domain specific language of patterns is formalised in HOL4.
775This is similar to the specification language of the x86 instruction set found in manufacturer's data sheets.
776A decode function is implemented by copying lines from data sheets into the proof script.
777
778We are currently considering implementing a similar domain specific language in Matita.
779However, we would prefer to certify in Matita the compiler for this language.
780Data sheets could then be compiled down to the efficient code that we currently provide, instead of inefficiently interpreting the data sheets every time an instruction is executed.
781
782%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
783% SECTION                                                                      %
784%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
785\section{Conclusions}
786\label{sect.conclusions}
787
788\CSC{Tell what is NOT formalized/formalizable: the HEX parser/pretty printer
789 and/or the I/O procedure}
790\CSC{Decode: two implementations}
791\CSC{Discuss over-specification}
792
793- WE FORMALIZE ALSO I/O ETC. NOT ONLY THE INSTRUCTION SELECTION (??)
794  How to test it? Specify it?
795
796\bibliography{itp-2011.bib}
797
798\end{document}
799
800\newpage
801
802\appendix
803
804\section{Listing of main O'Caml functions}
805\label{sect.listing.main.ocaml.functions}
806
807\subsubsection{From \texttt{ASMInterpret.ml(i)}}
808
809\begin{center}
810\begin{tabular*}{\textwidth}{p{3cm}@{\quad}p{9cm}}
811Name & Description \\
812\hline
813\texttt{assembly} & Assembles an abstract syntax tree representing an 8051 assembly program into a list of bytes, its compiled form. \\
814\texttt{initialize} & Initializes the emulator status. \\
815\texttt{load} & Loads an assembled program into the emulator's code memory. \\
816\texttt{fetch} & Fetches the next instruction, and automatically increments the program counter. \\
817\texttt{execute} & Emulates the processor.  Accepts as input a function that pretty prints the emulator status after every emulation loop. \\
818\end{tabular*}
819\end{center}
820
821\subsubsection{From \texttt{ASMCosts.ml(i)}}
822
823\begin{center}
824\begin{tabular*}{\textwidth}{p{3cm}@{\quad}p{9cm}}
825Name & Description \\
826\hline
827\texttt{compute} & Computes a map associating costings to basic blocks in the program.
828\end{tabular*}
829\end{center}
830
831\subsubsection{From \texttt{IntelHex.ml(i)}}
832
833\begin{center}
834\begin{tabular*}{\textwidth}{p{3cm}@{\quad}p{9cm}}
835Name & Description \\
836\hline
837\texttt{intel\_hex\_of\_file} & Reads in a file and parses it if in Intel IHX format, otherwise raises an exception. \\
838\texttt{process\_intel\_hex} & Accepts a parsed Intel IHX file and populates a hashmap (of the same type as code memory) with the contents.
839\end{tabular*}
840\end{center}
841
842\subsubsection{From \texttt{Physical.ml(i)}}
843
844\begin{center}
845\begin{tabular*}{\textwidth}{p{3cm}@{\quad}p{9cm}}
846Name & Description \\
847\hline
848\texttt{subb8\_with\_c} & Performs an eight bit subtraction on bitvectors.  The function also returns the most important PSW flags for the 8051: carry, auxiliary carry and overflow. \\
849\texttt{add8\_with\_c} & Performs an eight bit addition on bitvectors.  The function also returns the most important PSW flags for the 8051: carry, auxiliary carry and overflow. \\
850\texttt{dec} & Decrements an eight bit bitvector with underflow, if necessary. \\
851\texttt{inc} & Increments an eight bit bitvector with overflow, if necessary.
852\end{tabular*}
853\end{center}
854
855\newpage
856
857\section{Listing of main Matita functions}
858\label{sect.listing.main.matita.functions}
859
860\subsubsection{From \texttt{Arithmetic.ma}}
861
862\begin{center}
863\begin{tabular*}{\textwidth}{p{3cm}p{9cm}}
864Title & Description \\
865\hline
866\texttt{add\_n\_with\_carry} & Performs an $n$ bit addition on bitvectors.  The function also returns the most important PSW flags for the 8051: carry, auxiliary carry and overflow. \\
867\texttt{sub\_8\_with\_carry} & Performs an eight bit subtraction on bitvectors. The function also returns the most important PSW flags for the 8051: carry, auxiliary carry and overflow. \\
868\texttt{half\_add} & Performs a standard half addition on bitvectors, returning the result and carry bit. \\
869\texttt{full\_add} & Performs a standard full addition on bitvectors and a carry bit, returning the result and a carry bit.
870\end{tabular*}
871\end{center}
872
873\subsubsection{From \texttt{Assembly.ma}}
874
875\begin{center}
876\begin{tabular*}{\textwidth}{p{3cm}p{9cm}}
877Title & Description \\
878\hline
879\texttt{assemble1} & Assembles a single 8051 assembly instruction into its memory representation. \\
880\texttt{assemble} & Assembles an 8051 assembly program into its memory representation.\\
881\texttt{assemble\_unlabelled\_program} &\\& Assembles a list of (unlabelled) 8051 assembly instructions into its memory representation.
882\end{tabular*}
883\end{center}
884
885\subsubsection{From \texttt{BitVectorTrie.ma}}
886
887\begin{center}
888\begin{tabular*}{\textwidth}{p{3cm}p{9cm}}
889Title & Description \\
890\hline
891\texttt{lookup} & Returns the data stored at the end of a particular path (a bitvector) from the trie.  If no data exists, returns a default value. \\
892\texttt{insert} & Inserts data into a tree at the end of the path (a bitvector) indicated.  Automatically expands the tree (by filling in stubs) if necessary.
893\end{tabular*}
894\end{center}
895
896\subsubsection{From \texttt{DoTest.ma}}
897
898\begin{center}
899\begin{tabular*}{\textwidth}{p{3cm}p{9cm}}
900Title & Description \\
901\hline
902\texttt{execute\_trace} & Executes an assembly program for a fixed number of steps, recording in a trace which instructions were executed.
903\end{tabular*}
904\end{center}
905
906\subsubsection{From \texttt{Fetch.ma}}
907
908\begin{center}
909\begin{tabular*}{\textwidth}{p{3cm}p{9cm}}
910Title & Description \\
911\hline
912\texttt{fetch} & Decodes and returns the instruction currently pointed to by the program counter and automatically increments the program counter the required amount to point to the next instruction. \\
913\end{tabular*}
914\end{center}
915
916\subsubsection{From \texttt{Interpret.ma}}
917
918\begin{center}
919\begin{tabular*}{\textwidth}{p{3cm}p{9cm}}
920Title & Description \\
921\hline
922\texttt{execute\_1} & Executes a single step of an 8051 assembly program. \\
923\texttt{execute} & Executes a fixed number of steps of an 8051 assembly program.
924\end{tabular*}
925\end{center}
926
927\subsubsection{From \texttt{Status.ma}}
928
929\begin{center}
930\begin{tabular*}{\textwidth}{p{3cm}p{9cm}}
931Title & Description \\
932\hline
933\texttt{load} & Loads an assembled 8051 assembly program into code memory.
934\end{tabular*}
935\end{center}
936\end{document}
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