source: Deliverables/D4.1/ITP-Paper/itp-2011.tex @ 548

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Fixed English in conclusion and discussion of I/O.

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51\author{Dominic P. Mulligan\thanks{The project CerCo acknowledges the financial support of the Future and
52Emerging Technologies (FET) programme within the Seventh Framework
53Programme for Research of the European Commission, under FET-Open grant
54number: 243881} \and Claudio Sacerdoti Coen$^\star$}
55\authorrunning{D. P. Mulligan and C. Sacerdoti Coen}
56\title{An executable formalisation of the MCS-51 microprocessor in Matita}
57\titlerunning{An executable formalisation of the MCS-51}
58\institute{Dipartimento di Scienze dell'Informazione, Universit\`a di Bologna}
59
60\begin{document}
61
62\maketitle
63
64\begin{abstract}
65We summarise our formalisation of an emulator for the MCS-51 microprocessor in the Matita proof assistant.
66The MCS-51 is a widely used 8-bit microprocessor, especially popular in embedded devices.
67
68We proceeded in two stages, first implementing in O'Caml a prototype emulator, where bugs could be `ironed out' quickly.
69We then ported our O'Caml emulator to Matita's internal language.
70Though mostly straight-forward, this porting presented multiple problems.
71Of particular interest is how we handle the extreme non-orthoganality of the MSC-51's instruction set.
72In O'Caml, this was handled through heavy use of polymorphic variants.
73In Matita, we achieve the same effect through a non-standard use of dependent types.
74
75Both the O'Caml and Matita emulators are `executable'.
76Assembly programs may be animated within Matita, producing a trace of instructions executed.
77
78Our formalisation is a major component of the ongoing EU-funded CerCo project.
79\end{abstract}
80
81%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
82% SECTION                                                                      %
83%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
84\section{Background}
85\label{sect.introduction}
86
87Formal methods are designed to increase our confidence in the design and implementation of software (and hardware).
88Ideally, we would like all software to come equipped with a formal specification, along with a proof of correctness for the implementation.
89Today practically all programs are written in high level languages and then compiled into low level ones.
90Specifications are therefore also given at a high level and correctness can be proved by reasoning automatically or interactively on the program's source code.
91The code that is actually run, however, is not the high level source code that we reason on, but the object code that is generated by the compiler.
92
93A few simple questions now arise:
94\begin{itemize*}
95\item
96What properties are preserved during compilation?
97\item
98What properties are affected by the compilation strategy?
99\item
100To what extent can you trust your compiler in preserving those properties?
101\end{itemize*}
102These questions, and others like them, motivate a current `hot topic' in computer science research: \emph{compiler verification}.
103So far, the field has been focused on the first and last questions only.
104In particular, much attention has been placed on verifying compiler correctness with respect to extensional properties of programs, which are easily preserved during compilation; it is sufficient to completely preserve the denotational semantics of the input program.
105
106However, if we consider intensional properties of programs---such as space, time or energy spent into computation and transmission of data---the situation is more complex.
107To even be able to express these properties, and to be able to reason about them, we are forced to adopt a cost model that assigns a cost to single, or blocks, of instructions.
108Ideally, we would like to have a compositional cost model that assigns the same cost to all occurrences of one instruction.
109However, compiler optimisations are inherently non-compositional: each occurrence of a high level instruction is usually compiled in a different way according to the context it finds itself in.
110Therefore both the cost model and intensional specifications are affected by the compilation process.
111
112In the current EU project CerCo (`Certified Complexity') we approach the problem of reasoning about intensional properties of programs as follows.
113We are currently developing a compiler that induces a cost model on the high level source code.
114Costs are assigned to each block of high level instructions by considering the costs of the corresponding blocks of compiled object code.
115The cost model is therefore inherently non-compositional.
116However, the model has the potential to be extremely \emph{precise}, capturing a program's \emph{realistic} cost, by taking into account, not ignoring, the compilation process.
117A prototype compiler, where no approximation of the cost is provided, has been developed.
118
119We believe that our approach is especially applicable to certifying real time programs.
120Here, a user can certify that all `deadlines' are met whilst wringing as many clock cycles from the processor---using a cost model that does not over-estimate---as possible.
121
122Further, we see our approach as being relevant to the field of compiler verification (and construction) itself.
123For instance, an optimisation specified only extensionally is only half specified; though the optimisation may preserve the denotational semantics of a program, there is no guarantee that any intensional properties of the program, such as space or time usage, will be improved.
124Another potential application is toward completeness and correctness of the compilation process in the presence of space constraints.
125Here, a compiler could potentially reject a source program targetting an embedded system when the size of the compiled code exceeds the available ROM size.
126Moreover, preservation of a program's semantics may only be required for those programs that do not exhaust the stack or heap.
127Hence the statement of completeness of the compiler must take in to account a realistic cost model.
128
129In the methodology proposed in CerCo we assume we are able to compute on the object code exact and realistic costs for sequential blocks of instructions.
130With modern processors, though possible~\cite{??,??,??}, it is difficult to compute exact costs or to reasonably approximate them.
131This is because the execution of a program itself has an influence on the speed of processing.
132For instance, caching, memory effects and other advanced features such as branch prediction all have a profound effect on execution speeds.
133For this reason CerCo decided to focus on 8-bit microprocessors.
134These are still widely used in embedded systems, and have the advantage of an easily predictable cost model due to the relative sparcity of features that they possess.
135
136In particular, we have fully formalised an executable formal semantics of a family of 8 bit Freescale Microprocessors~\cite{oliboni}, and provided a similar executable formal semantics for the MCS-51 microprocessor.
137The latter work is what we describe in this paper.
138The main focus of the formalisation has been on capturing the intensional behaviour of the processor.
139However, the design of the MCS-51 itself has caused problems in our formalisation.
140For example, the MCS-51 has a highly unorthogonal instruction set.
141To cope with this unorthogonality, and to produce an executable specification, we have exploited the dependent type system of Matita, an interactive proof assistant.
142
143\subsection{The 8051/8052}
144\label{subsect.8051-8052}
145
146The MCS-51 is an eight bit microprocessor introduced by Intel in the late 1970s.
147Commonly called the 8051, in the three decades since its introduction the processor has become a highly popular target for embedded systems engineers.
148Further, the processor, its immediate successor the 8052, and many derivatives are still manufactured \emph{en masse} by a host of semiconductor suppliers.
149
150The 8051 is a well documented processor, and has the additional support of numerous open source and commercial tools, such as compilers for high-level languages and emulators.
151For instance, the open source Small Device C Compiler (SDCC) recognises a dialect of C, and other compilers targeting the 8051 for BASIC, Forth and Modula-2 are also extant.
152An open source emulator for the processor, MCU-8051 IDE, is also available.
153Both MCU-8051 IDE and SDCC were used profitably in the implementation of our formalisation.
154
155\begin{figure}[t]
156\begin{center}
157\includegraphics[scale=0.5]{memorylayout.png}
158\end{center}
159\caption{High level overview of the 8051 memory layout}
160\label{fig.memory.layout}
161\end{figure}
162
163The 8051 has a relatively straightforward architecture, unencumbered by advanced features of modern processors, making it an ideal target for formalisation.
164A high-level overview of the processor's memory layout is provided in Figure~\ref{fig.memory.layout}.
165
166Processor RAM is divided into numerous segments, with the most prominent division being between internal and (optional) external memory.
167Internal memory, commonly provided on the die itself with fast access, is further divided into 128 bytes of internal RAM and numerous Special Function Registers (SFRs) which control the operation of the processor.
168Internal RAM (IRAM) is further divided into eight general purpose bit-addressable registers (R0--R7).
169These sit in the first eight bytes of IRAM, though can be programmatically `shifted up' as needed.
170Bit memory, followed by a small amount of stack space, resides in the memory space immediately after the register banks.
171What remains of the IRAM may be treated as general purpose memory.
172A schematic view of IRAM layout is provided in Figure~\ref{fig.iram.layout}.
173
174External RAM (XRAM), limited to a maximum size of 64 kilobytes, is optional, and may be provided on or off chip, depending on the manufacturer.
175XRAM is accessed using a dedicated instruction, and requires sixteen bits to address fully.
176External code memory (XCODE) is often stored in the form of an EPROM, and limited to 64 kilobytes in size.
177However, depending on the particular manufacturer and processor model, a dedicated on-die read-only memory area for program code (ICODE) may also be supplied.
178
179Memory may be addressed in numerous ways: immediate, direct, indirect, external direct and code indirect.
180As the latter two addressing modes hint, there are some restrictions enforced by the 8051 and its derivatives on which addressing modes may be used with specific types of memory.
181For instance, the 128 bytes of extra internal RAM that the 8052 features cannot be addressed using indirect addressing; rather, external (in)direct addressing must be used.
182
183The 8051 series possesses an eight bit Arithmetic and Logic Unit (ALU), with a wide variety of instructions for performing arithmetic and logical operations on bits and integers.
184Further, the processor possesses two eight bit general purpose accumulators, A and B.
185
186Communication with the device is facilitated by an onboard UART serial port, and associated serial controller, which can operate in numerous modes.
187Serial baud rate is determined by one of two sixteen bit timers included with the 8051, which can be set to multiple modes of operation.
188(The 8052 provides an additional sixteen bit timer.)
189As an additional method of communication, the 8051 also provides a four byte bit-addressable input-output port.
190
191The programmer may take advantage of the interrupt mechanism that the processor provides.
192This is especially useful when dealing with input or output involving the serial device, as an interrupt can be set when a whole character is sent or received via the serial port.
193
194Interrupts immediately halt the flow of execution of the processor, and cause the program counter to jump to a fixed address, where the requisite interrupt handler is stored.
195However, interrupts may be set to one of two priorities: low and high.
196The interrupt handler of an interrupt with high priority is executed ahead of the interrupt handler of an interrupt of lower priority, interrupting a currently executing handler of lower priority, if necessary.
197
198The 8051 has interrupts disabled by default.
199The programmer is free to handle serial input and output manually, by poking serial flags in the SFRs.
200Similarly, `exceptional circumstances' that would otherwise trigger an interrupt on more modern processors, for example, division by zero, are also signalled by setting flags.
201
202\begin{figure}[t]
203\begin{center}
204\includegraphics[scale=0.5]{iramlayout.png}
205\end{center}
206\caption{Schematic view of 8051 IRAM layout}
207\label{fig.iram.layout}
208\end{figure}
209
210%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
211% SECTION                                                                      %
212%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
213\subsection{Overview of paper}
214\label{subsect.overview.paper}
215
216In Section~\ref{sect.design.issues.formalisation} we discuss design issues in the development of the formalisation.
217In Section~\ref{sect.validation} we discuss how we validated the design and implementation of our emulator to ensure that what we formalised was an accurate model of an MCS-51 series microprocessor.
218In Section~\ref{sect.related.work} we describe previous work, with an eye toward describing its relation with the work described herein.
219In Section~\ref{sect.conclusions} we conclude the paper.
220
221In Appendices~\ref{sect.listing.main.ocaml.functions} and~\ref{sect.listing.main.matita.functions} we provide a brief overview of the main functions in our implementation, and describe at a high level what they do.
222
223%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
224% SECTION                                                                      %
225%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
226\section{Design issues in the formalisation}
227\label{sect.design.issues.formalisation}
228
229From hereonin, we typeset O'Caml source with \texttt{\color{blue}{blue}} and Matita source with \texttt{\color{red}{red}} to distinguish the two syntaxes.
230Matita's syntax is largely straightforward to those familiar with Coq or O'Caml.
231The only subtlety is the use of `\texttt{?}' in an argument position denoting an argument that should be inferred automatically, if possible.
232
233\subsection{Development strategy}
234\label{subsect.development.strategy}
235
236Our implementation progressed in two stages.
237We began with an emulator written in O'Caml.
238We used this to `iron out' any bugs in our design and implementation within O'Caml's more permissive type system.
239O'Caml's ability to perform file input-output also eased debugging and validation.
240Once we were happy with the performance and design of the O'Caml emulator, we moved to the Matita formalisation.
241
242Matita's syntax is lexically similar to O'Caml's.
243This eased the translation, as large swathes of code were merely copy-pasted with minor modifications.
244However, several major issues had to be addresses when moving from O'Caml to Matita.
245These are now discussed.
246
247%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
248% SECTION                                                                      %
249%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
250\subsection{Representation of integers}
251\label{subsect.representation.integers}
252
253\begin{figure}[t]
254\begin{minipage}[t]{0.45\textwidth}
255\vspace{0pt}
256\begin{lstlisting}
257type 'a vect = bit list
258type word = [`Sixteen] vect
259type byte = [`Eight] vect
260$\color{blue}{\mathtt{let}}$ from_nibble =
261 function
262    [b1;b2;b3;b4] -> b1,b2,b3,b4
263  | _ -> assert false
264\end{lstlisting}
265\end{minipage}
266%
267\begin{minipage}[t]{0.55\textwidth}
268\vspace{0pt}
269\begin{lstlisting}
270type 'a vect
271type word = [`Sixteen] vect
272type byte = [`Eight] vect
273val from_nibble: nibble -> bit*bit*bit*bit
274\end{lstlisting}
275\end{minipage}
276\caption{Sample of O'Caml implementation and interface for bitvectors module}
277\label{fig.ocaml.implementation.bitvectors}
278\end{figure}
279
280Integers are represented using bitvectors, i.e. fixed length vectors of booleans.
281In our O'Caml emulator, we `faked' bitvectors using phantom types and polymorphic variants, as in Figure~\ref{fig.ocaml.implementation.bitvectors}.
282From within the bitvector module (left column) bitvectors are just lists of bits.
283However, the module's interface (right column) hides this implementation completely.
284
285In Matita, we are able to use the full power of dependent types to define `real' bitvectors:
286\begin{lstlisting}
287inductive Vector (A: Type[0]): nat → Type[0] ≝
288  VEmpty: Vector A O
289| VCons: ∀n: nat. A → Vector A n → Vector A (S n).
290\end{lstlisting}
291We define \texttt{BitVector} as a specialization of \texttt{Vector} to \texttt{bool}.
292We may use Matita's type system to provide even stronger guarantees, here on a function that splits a vector into two pieces at any index, providing that the index is smaller than the length of the \texttt{Vector} to be split:
293\begin{lstlisting}
294let rec split (A: Type[0]) (m,n: nat) on m:
295   Vector A (plus m n) $\rightarrow$ (Vector A m) $\times$ (Vector A n) := ...
296\end{lstlisting}
297
298%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
299% SECTION                                                                      %
300%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
301\subsection{Representing memory}
302\label{subsect.representing.memory}
303
304The MCS-51 has numerous different types of memory.
305In our prototype implementation, we simply used a map datastructure from the O'Caml standard library.
306Matita's standard library is relatively small, and does not contain a generic map datastructure.
307Therefore, we had the opportunity of crafting a special-purpose datastructure for the job.
308
309We worked under the assumption that large swathes of memory would often be uninitialized.
310Na\"ively, using a complete binary tree, for instance, would be extremely memory inefficient.
311Instead, we chose to use a modified form of trie, where paths are represented by bitvectors.
312As bitvectors were widely used in our implementation already for representing integers, this worked well:
313\begin{lstlisting}
314inductive BitVectorTrie (A: Type[0]): nat $\rightarrow$ Type[0] ≝
315  Leaf: A $\rightarrow$ BitVectorTrie A 0
316| Node: ∀n. BitVectorTrie A n $\rightarrow$ BitVectorTrie A n $\rightarrow$ BitVectorTrie A (S n)
317| Stub: ∀n. BitVectorTrie A n.
318\end{lstlisting}
319Here, \texttt{Stub} is a constructor that can appear at any point in our tries.
320It internalises the notion of `uninitialized data'.
321Performing a lookup in memory is now straight-forward.
322We merely traverse a path, and if at any point we encounter a \texttt{Stub}, we return a default value\footnote{All manufacturer data sheets that we consulted were silent on the subject of what should be returned if we attempt to access uninitialized memory.  We defaulted to simply returning zero, though our \texttt{lookup} function is parametric in this choice.  We do not believe that this is an outrageous decision, as SDCC for instance generates code which first `zeroes out' all memory in a preamble before executing the program proper.  This is in line with the C standard, which guarantees that all global variables will be zero initialized piecewise.}.
323As we are using bitvectors, we may make full use of dependent types and ensure that our bitvector paths are of the same length as the height of the tree.
324
325%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
326% SECTION                                                                      %
327%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
328\subsection{Labels and pseudoinstructions}
329\label{subsect.labels.pseudoinstructions}
330
331Aside from implementing the core MCS-51 instruction set, we also provided \emph{pseudoinstructions}, \emph{labels} and \emph{cost labels}.
332The purpose of \emph{cost labels} will be explained in Subsection~\ref{subsect.computation.cost.traces}.
333
334Introducing pseudoinstructions had the effect of simplifying a C compiler---another component of the CerCo project---that was being implemented in parallel with our implementation.
335To understand why this is so, consider the fact that the MCS-51's instruction set has numerous instructions for unconditional and conditional jumps to memory locations.
336For instance, the instructions \texttt{AJMP}, \texttt{JMP} and \texttt{LJMP} all perform unconditional jumps.
337However, these instructions differ in how large the maximum size of the offset of the jump to be performed can be.
338Further, all jump instructions require a concrete memory address---to jump to---to be specified.
339Requiring the compiler to compute these offsets, and select appropriate jump instructions, was seen as needleslly burdensome.
340
341Introducing labels also had a simplifying effect on the design of the compiler.
342Instead of jumping to a concrete address, the compiler could `just' jump to a label.
343In this vein, we introduced pseudoinstructions for both unconditional and conditional jumps to a label.
344
345Further, we also introduced labels for storing global data in a preamble before the program.
346A pseudoinstruction \texttt{Mov} moves (16-bit) data stored at a label into the (16-bit) register \texttt{DPTR}.
347We believe this facility, of storing global data in a preamble referenced by a label, will also make any future extension considering separate compilation much simpler.
348
349Our pseudoinstructions and labels induce an assembly language similar to that of SDCC.
350All pseudoinstructions and labels are `assembled away', prior to program execution, using a preprocessing stage.
351Jumps are computed in two stages.
352The first stage builds a map associating memory addresses to labels, with the second stage removing pseudojumps with concrete jumps to the correct address.
353
354%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
355% SECTION                                                                      %
356%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
357\subsection{Anatomy of the (Matita) emulator}
358\label{subsect.anatomy.matita.emulator}
359
360The internal state of our Matita emulator is represented as a record:
361\begin{lstlisting}
362record Status: Type[0] ≝
363{
364  code_memory: BitVectorTrie Byte 16;
365  low_internal_ram: BitVectorTrie Byte 7;
366  high_internal_ram: BitVectorTrie Byte 7;
367  external_ram: BitVectorTrie Byte 16;
368  program_counter: Word;
369  special_function_registers_8051: Vector Byte 19;
370  special_function_registers_8052: Vector Byte 5;
371  ...
372}.
373\end{lstlisting}
374This record neatly encapsulates the current memory contents, the program counter, the state of the current SFRs, and so on.
375One peculiarity is the packing of the 24 combined SFRs into fixed length vectors.
376This was due to a bug in Matita when we were constructing the emulator, since fixed, where the time needed to typecheck a record grew exponentially with the number of fields.
377
378Here, it appears that the MCS-51's memory spaces are completely disjoint.
379This is not so; many of them overlap with each other, and there's a many-many relationship between addressing modes and memory spaces.
380For instance, \texttt{DIRECT} addressing can be used to address low internal RAM and the SFRs, but not high internal RAM.
381
382For simplicity, we merely treat memory spaces as if they are completely disjoint in the \texttt{Status} record.
383Overlapping, and checking which addressing modes can be used to address particular memory spaces, is handled through numerous \texttt{get\_arg\_XX} and \texttt{set\_arg\_XX} (for 1, 8 and 16 bits) functions.
384
385Both the Matita and O'Caml emulators follows the classic `fetch-decode-execute' model of processor operation.
386The next instruction to be processed, indexed by the program counter, is fetched from code memory with \texttt{fetch}.
387An updated program counter, along with the concrete cost, in processor cycles for executing this instruction, is also returned.
388These costs are taken from a Siemen's data sheet for the MCS-51, and will likely vary across manufacturers and particular derivatives of the processor.
389\begin{lstlisting}
390definition fetch:
391  BitVectorTrie Byte 16 $\rightarrow$ Word $\rightarrow$ instruction $\times$ Word $\times$ nat := ...
392\end{lstlisting}
393A single instruction is assembled into its corresponding bit encoding with \texttt{assembly1}:
394\begin{lstlisting}
395definition assembly1: instruction $\rightarrow$ list Byte := ...
396\end{lstlisting}
397An assembly program, consisting of a preamble containing global data, and a list of (pseudo)instructions, is assembled using \texttt{assembly}.
398Pseudoinstructions and labels are eliminated in favour of concrete instructions from the MCS-51 instruction set.
399A map associating memory locations and cost labels (see Subsection~\ref{subsect.computation.cost.traces}) is also produced.
400\begin{lstlisting}
401definition assembly:
402  assembly_program $\rightarrow$ option (list Byte $\times$ (BitVectorTrie String 16)) := ...
403\end{lstlisting}
404A single execution step of the processor is evaluated using \texttt{execute\_1}, mapping a \texttt{Status} to a \texttt{Status}:
405\begin{lstlisting}
406definition execute_1: Status $\rightarrow$ Status := ...
407\end{lstlisting}
408Multiple steps of processor execution are implemented in \texttt{execute}, which wraps \texttt{execute\_1}:
409\begin{lstlisting}
410let rec execute (n: nat) (s: Status) on n: Status := ...
411\end{lstlisting}
412This differs slightly from the design of the O'Caml emulator, which executed a program indefinitely, and also accepted a callback function as an argument, which could `witness' the execution as it happened, and providing a print-out of the processor state, and other debugging information.
413Due to Matita's requirement that all functions be strongly normalizing, \texttt{execute} cannot execute a program indefinitely, and must execute a fixed number of steps.
414
415%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
416% SECTION                                                                      %
417%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
418\subsection{Instruction set unorthogonality}
419\label{subsect.instruction.set.unorthogonality}
420
421A peculiarity of the MCS-51 is the non-orthogonality of its instruction set.
422For instance, the \texttt{MOV} instruction, can be invoked using one of sixteen combinations of addressing modes.
423
424% Show example of pattern matching with polymorphic variants
425
426Such non-orthogonality in the instruction set was handled with the use of polymorphic variants in the O'Caml emulator.
427For instance, we introduced types corresponding to each addressing mode:
428\begin{lstlisting}
429type direct = [ `DIRECT of byte ]
430type indirect = [ `INDIRECT of bit ]
431...
432\end{lstlisting}
433Which were then used in our inductive datatype for assembly instructions, as follows:
434\begin{lstlisting}
435type 'addr preinstruction =
436 [ `ADD of acc * [ reg | direct | indirect | data ]
437...
438 | `MOV of
439    (acc * [ reg | direct | indirect | data ],
440     [ reg | indirect ] * [ acc | direct | data ],
441     direct * [ acc | reg | direct | indirect | data ],
442     dptr * data16,
443     carry * bit,
444     bit * carry
445     ) union6
446...
447\end{lstlisting}
448Here, \texttt{union6} is a disjoint union type, defined as follows:
449\begin{lstlisting}
450type ('a,'b,'c,'d,'e,'f) union6 = [ `U1 of 'a | ... | `U6 of 'f ]
451\end{lstlisting}
452For our purposes, the types \texttt{union2}, \texttt{union3} and \texttt{union6} sufficed.
453
454This polymorphic variant machinery worked well: it introduced a certain level of type safety (for instance, the type of our \texttt{MOV} instruction above guarantees it cannot be invoked with arguments in the \texttt{carry} and \texttt{data16} addressing modes, respectively), and also allowed us to pattern match against instructions, when necessary.
455However, this polymorphic variant machinery is \emph{not} present in Matita.
456We needed some way to produce the same effect, which Matita supported.
457For this task, we used dependent types.
458
459We first provided an inductive data type representing all possible addressing modes, a type that functions will pattern match against:
460\begin{lstlisting}
461inductive addressing_mode: Type[0] ≝
462  DIRECT: Byte $\rightarrow$ addressing_mode
463| INDIRECT: Bit $\rightarrow$ addressing_mode
464...
465\end{lstlisting}
466We also wished to express in the type of functions the \emph{impossibility} of pattern matching against certain constructors.
467In order to do this, we introduced an inductive type of addressing mode `tags'.
468The constructors of \texttt{addressing\_mode\_tag} are in one-to-one correspondence with the constructors of \texttt{addressing\_mode}:
469\begin{lstlisting}
470inductive addressing_mode_tag : Type[0] ≝
471  direct: addressing_mode_tag
472| indirect: addressing_mode_tag
473...
474\end{lstlisting}
475A function that checks whether an \texttt{addressing\_mode} is `morally' an \texttt{addressing\_mode\_tag} is provided, as follows:
476\begin{lstlisting}
477let rec is_a (d: addressing_mode_tag) (A: addressing_mode) on d :=
478  match d with
479   [ direct $\Rightarrow$ match A with [ DIRECT _ $\Rightarrow$ true | _ $\Rightarrow$ false ]
480   | indirect $\Rightarrow$ match A with [ INDIRECT _ $\Rightarrow$ true | _ $\Rightarrow$ false ]
481...
482\end{lstlisting}
483We also extend this check to vectors of \texttt{addressing\_mode\_tag}'s in the obvious manner:
484\begin{lstlisting}
485let rec is_in (n: nat) (l: Vector addressing_mode_tag n) (A: addressing_mode) on l :=
486 match l return $\lambda$m.$\lambda$_: Vector addressing_mode_tag m. bool with
487  [ VEmpty $\Rightarrow$ false
488  | VCons m he (tl: Vector addressing_mode_tag m) $\Rightarrow$
489     is_a he A $\vee$ is_in ? tl A ].
490\end{lstlisting}
491Here $\mathtt{\vee}$ is inclusive disjunction on the \texttt{bool} datatype.
492\begin{lstlisting}
493record subaddressing_mode (n: nat) (l: Vector addressing_mode_tag (S n)): Type[0] :=
494{
495  subaddressing_modeel :> addressing_mode;
496  subaddressing_modein: bool_to_Prop (is_in ? l subaddressing_modeel)
497}.
498\end{lstlisting}
499We can now provide an inductive type of preinstructions with precise typings:
500\begin{lstlisting}
501inductive preinstruction (A: Type[0]): Type[0] ≝
502   ADD: $\llbracket$ acc_a $\rrbracket$ $\rightarrow$ $\llbracket$ register; direct; indirect; data $\rrbracket$ $\rightarrow$ preinstruction A
503 | ADDC: $\llbracket$ acc_a $\rrbracket$ $\rightarrow$ $\llbracket$ register; direct; indirect; data $\rrbracket$ $\rightarrow$ preinstruction A
504...
505\end{lstlisting}
506Here $\llbracket - \rrbracket$ is syntax denoting a vector.
507We see that the constructor \texttt{ADD} expects two parameters, the first being the accumulator A (\texttt{acc\_a}), and the second being one of a register, direct, indirect or data addressing mode.
508
509% One of these coercions opens up a proof obligation which needs discussing
510% Have lemmas proving that if an element is a member of a sub, then it is a member of a superlist, and so on
511The final, missing component is a pair of type coercions from \texttt{addressing\_mode} to \texttt{subaddressing\_mode} and from \texttt{subaddressing\_mode} to \texttt{Type$\lbrack0\rbrack$}, respectively.
512The latter coercion is largely straightforward, however the former is not:
513\begin{lstlisting}
514coercion mk_subaddressing_mode:
515  $\forall$n.  $\forall$l: Vector addressing_mode_tag (S n).
516  $\forall$a: addressing_mode.
517  $\forall$p: bool_to_Prop (is_in ? l a). subaddressing_mode n l :=
518    mk_subaddressing_mode on a: addressing_mode to subaddressing_mode ? ?.
519\end{lstlisting}
520Using this coercion opens a proof obligation wherein we must prove that the \texttt{addressing\_mode\_tag} in correspondence with the \texttt{addressing\_mode} is a member of the \texttt{Vector} of permissible \texttt{addressing\_mode\_tag}s.
521This impels us to state and prove a number of auxilliary lemmas.
522For instance, we prove that if an \texttt{addressing\_mode\_tag} is a member of a \texttt{Vector}, and we possess another vector with additional elements, then the same \texttt{addressing\_mode\_tag} is a member of this vector.
523Using these lemmas, and Matita's automation, all proof obligations are solved easily.
524(Type checking the main \texttt{execute\_1} function, for instance, opens up over 200 proof obligations.)
525
526The machinery just described allows us to state in the type of a function what addressing modes that function expects.
527For instance, consider \texttt{set\_arg\_16}, which expects only a \texttt{DPTR}:
528\begin{lstlisting}
529definition set_arg_16: Status $\rightarrow$ Word $\rightarrow$ $\llbracket$ dptr $\rrbracket$ $\rightarrow$ Status ≝
530  $\lambda$s, v, a.
531   match a return $\lambda$x. bool_to_Prop (is_in ? $\llbracket$ dptr $\rrbracket$ x) $\rightarrow$ ? with
532     [ DPTR $\Rightarrow$ $\lambda$_: True.
533       let 〈 bu, bl 〉 := split $\ldots$ eight eight v in
534       let status := set_8051_sfr s SFR_DPH bu in
535       let status := set_8051_sfr status SFR_DPL bl in
536         status
537     | _ $\Rightarrow$ $\lambda$_: False.
538       match K in False with
539       [
540       ]
541     ] (subaddressing_modein $\ldots$ a).
542\end{lstlisting}
543All other cases are discharged by the catch-all at the bottom of the match expression.
544Attempting to match against another addressing mode not indicated in the type (for example, \texttt{REGISTER}) will produce a type-error.
545
546% Talk about extraction to O'Caml code, which hopefully will allow us to extract back to using polymorphic variants, or when extracting vectors we could extract using phantom types
547% Discuss alternative approaches, i.e. Sigma types to piece together smaller types into larger ones, as opposed to using a predicate to `cut out' pieces of a larger type, which is what we did
548
549%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
550% SECTION                                                                      %
551%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
552\subsection{I/O and timers}
553\label{subsect.i/o.timers}
554
555% `Real clock' for I/O and timers
556The O'Caml emulator has code for handling timers, asynchronous I/O and interrupts (these are not yet ported to the Matita emulator).
557All three of these features interact with each other in subtle ways.
558For instance, interrupts can `fire' when an input is detected on the processor's UART port, and, in certain modes, timers reset when a high signal is detected on one of the MCS-51's communication pins.
559
560To accurately model timers and I/O, we add an unbounded integral field \texttt{clock} to the central \texttt{status} record.
561This field is only logical, since it does not represent any quantity stored in the actual processor, and is used to keep track of the current processor time.
562Before every execution step, \texttt{clock} is incremented by the number of processor cycles that the instruction just fetched will take to execute.
563The processor then executes the instruction, followed by the code implementing the timers and I/O\footnote{Though it isn't fully specified by the manufacturer's data sheets if I/O is handled at the beginning or the end of each cycle.}. In order to model I/O, we also store in the status a
564We use \emph{continuation} as a description of the behaviour of the environment:
565\begin{lstlisting}
566type line =
567  [ `P1 of byte | `P3 of byte
568  | `SerialBuff of [ `Eight of byte | `Nine of BitVectors.bit * byte ]]
569type continuation =
570  [`In of time * line * epsilon * continuation] option *
571  [`Out of (time -> line -> time * continuation)]
572\end{lstlisting}
573At each moment, the second projection of the continuation $k$ describes how the environment will react to an output event performed in the future by the processor.
574If the processor at time $\tau$ starts an asynchronous output $o$ either on the P1 or P3 output lines, or on the UART, then the environment will receive the output at time $\tau'$.
575Moreover the status is immediately updated with the continuation $k'$ where $\pi_2(k)(\tau,o) = \langle \tau',k' \rangle$.
576
577Further, if $\pi_1(k) = \mathtt{Some}~\langle \tau',i,\epsilon,k'\rangle$, then at time $\tau'$ the environment will send the asynchronous input $i$ to the processor and the status will be updated with the continuation $k'$.
578This input will become visible to the processor only at time $\tau' + \epsilon$.
579
580The time required to perform an I/O operation is partially specified in the data sheets of the UART module.
581However, this computation is complex so we prefer to abstract over it.
582We therefore leave the computation of the delay time to the environment.
583
584We use only the P1 and P3 lines despite the MCS-51 having four output lines, P0--P3.
585This is because P0 and P2 become inoperable if the processor is equipped with XRAM (which we assume it is).
586
587The UART port can work in several modes, depending on the how the SFRs are set.
588In an asyncrhonous mode, the UART transmits eight bits at a time, using a ninth line for syncrhonization.
589In a syncrhonous mode the ninth line is used to transmit an additional bit.
590
591%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
592% SECTION                                                                      %
593%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
594\subsection{Computation of cost traces}
595\label{subsect.computation.cost.traces}
596
597As mentioned in Subsection~\ref{subsect.labels.pseudoinstructions} we introduced a notion of \emph{cost label}.
598Cost labels are inserted by the prototype C compiler in specific locations in the object code.
599Roughly, for those familiar with control flow graphs, they are inserted at the start of every basic block.
600
601Cost labels are used to calculate a precise costing for a program by marking the location of basic blocks.
602During the assembly phase, where labels and pseudoinstructions are eliminated, a map is generated associating cost labels with memory locations.
603This map is later used in a separate analysis which computes the cost of a program by traversing through a program, fetching one instruction at a time, and computing the cost of blocks.
604These block costings are stored in another map, and will later be passed back to the prototype compiler.
605
606%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
607% SECTION                                                                      %
608%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
609\section{Validation}
610\label{sect.validation}
611
612We spent considerable effort attempting to ensure that our formalisation is correct, that is, what we have formalised really is an accurate model of the MCS-51 microprocessor.
613
614First, we made use of multiple data sheets, each from a different semiconductor manufacturer.
615This helped us spot errors in the specification of the processor's instruction set, and its behaviour.
616
617The O'Caml prototype was especially useful for validation purposes.
618This is because we wrote a module for parsing and loading the Intel HEX file format.
619HEX is a standard format that all compilers targetting the MCS-51, and similar processors, produce.
620It is essentially a snapshot of the processor's code memory in compressed form.
621Using this, we were able to compile C programs with SDCC, an open source compiler, and load the resulting program directly into our emulator's code memory, ready for execution.
622Further, we are able to produce a HEX file from our emulator's code memory, for loading into third party tools.
623After each step of execution, we can print out both the instruction that had been executed, along with its arguments, and a snapshot of the processor's state, including all flags and register contents.
624For example:
625\begin{frametxt}
626\begin{verbatim}
627...
628
62908: mov 81 #07
630
631 Processor status:                               
632
633   ACC : 0 (00000000) B   : 0 (00000000) PSW : 0 (00000000)
634    with flags set as:
635     CY  : false   AC  : false FO  : false
636     RS1 : false   RS0 : false OV  : false
637     UD  : false   P   : false
638   SP  : 7 (00000111) IP  : 0 (00000000)
639   PC  : 8 (0000000000001000)
640   DPL : 0 (00000000) DPH : 0 (00000000) SCON: 0 (00000000)
641   SBUF: 0 (00000000) TMOD: 0 (00000000) TCON: 0 (00000000)
642   Registers:                                   
643    R0 : 0 (00000000) R1 : 0 (00000000) R2 : 0 (00000000)
644    R3 : 0 (00000000) R4 : 0 (00000000) R5 : 0 (00000000)
645    R6 : 0 (00000000) R7 : 0 (00000000)
646
647...
648\end{verbatim}
649\end{frametxt}
650Here, the traces indicates that the instruction \texttt{mov 81 \#07} has just been executed by the processor, which is now in the state indicated.
651These traces were useful in spotting anything that was `obviously' wrong with the execution of the program.
652
653Further, we made use of an open source emulator for the MCS-51, \texttt{mcu8051ide}.
654Using our execution traces, we were able to step through a compiled program, one instruction at a time, in \texttt{mcu8051ide}, and compare the resulting execution trace with the trace produced by our emulator.
655
656Our Matita formalisation was largely copied from the O'Caml source code, apart from changes related to addressing modes already mentioned.
657However, as the Matita emulator is executable, we could perform further validation by comparing the trace of a program's execution in the Matita emulator with the trace of the same program in the O'Caml emulator.
658
659%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
660% SECTION                                                                      %
661%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
662\section{Related work}
663\label{sect.related.work}
664There exists a large body of literature on the formalisation of microprocessors.
665The majority of it aims to prove correctness of the implementation of the microprocessor at the microcode or gate level.
666However, we are interested in providing a precise specification of the behaviour of the microprocessor in order to prove the correctness of a compiler which will target the processor.
667In particular, we are interested in intensional properties of the processor; precise timings of instruction execution in clock cycles.
668Moreover, in addition to formalising the interface of an MCS-51 processor, we have also built a complete MCS-51 ecosystem: the UART, the I/O lines, and hardware timers, along with an assembler.
669
670Similar work to ours can be found in~\cite{A Trustworthy Monadic Formalization of the ARMv7 Instruction Set Architecture Anthony Fox and Magnus O. Myreen}.
671Here, the authors describe the formalisation, in HOL4, of the ARMv7 instruction set architecture, and point to a good list of references to related work in the literature.
672This formalisation also considers the machine code level, as opposed to only considering an abstract assembly language.
673In particular, instruction decoding is explicitly modelled inside HOL4's logic.
674However, we go further in also providing an assembly language, complete with assembler, to translate instructions and pseudoinstruction to machine code.
675
676Further, in~\cite{again} the authors validated their formalisation by using development boards and random testing.
677However, we currently rely on non-exhaustive testing against a third party emulator.
678We leave similar exhaustive testing for future work.
679
680Executability is another key difference between our work and~\cite{again}.
681In~\cite{again} the authors provide an automation layer to derive single step theorems: if the processor is in a particular state that satisfies some preconditions, then after execution of an instruction it will reside in another state satisfying some postconditions.
682We do not need single step theorems of this form.
683This is because Matita is based on a logic that internalizes conversion.
684As a result, our formalisation is executable: applying the emulation function to an input state eventually reduces to an output state that already satisfies the appropriate conditions.
685
686Our main difficulties resided in the non-uniformity of an old 8-bit architecture, in terms of the instruction set, addressing modes and memory models.
687In contrast, the ARM instruction set and memory model is relatively uniform, simplifying any formalisation considerably.
688
689Perhaps the closest project to CerCo is CompCert~\cite{compcert}.
690CompCert concerns the certification of an ARM compiler and includes a formalisation in Coq of a subset of ARM.
691Coq and Matita essentially share the same logic.
692
693Despite this similarity, the two formalisations do not have much in common.
694First, CompCert provides a formalisation at the assembly level (no instruction decoding), and this impels them to trust an unformalised assembler and linker, whereas we provide our own.
695I/O is also not considered at all in CompCert.
696Moreover an idealized abstract and uniform memory model is assumed, while we take into account the complicated overlapping memory model of the MCS-51 architecture.
697Finally, around 90 instructions of the 200+ offered by the processor are formalised in CompCert, and the assembly language is augmented with macro instructions that are turned into `real' instructions only during communication with the external assembler.
698Even from a technical level the two formalisations differ: while we tried to exploit dependent types as often as possible, CompCert largely sticks to the non-dependent fragment of Coq.
699
700In~\cite{Robert Atkey. CoqJVM: An executable specification of the Java virtual machine using dependent types. In Marino Miculan, Ivan Scagnetto, and Furio Honsell, editors, TYPES, volume 4941 of Lecture Notes in Computer Science, pages 18-32.  Springer, 2007.} Atkey presents an executable specification of the Java virtual machine which uses dependent types.
701As we do, dependent types are used to remove spurious partiality from the model, and to lower the need for over-specifying the behaviour of the processor in impossible cases.
702Our use of dependent types will also help to maintain invariants when we prove the correctness of the CerCo prototype compiler.
703
704Finally, in~\cite{Susmit Sarkar, Pater Sewell, Francesco Zappa Nardelli, Scott Owens, Tom Ridge, Thomas Braibant Magnus O. Myreen, and Jade Alglave. The semantics of x86-CC multiprocessor machine code. In Principles of Programming Languages (POPL). ACM, 2009.} Sarkar et al provide an executable semantics for x86-CC multiprocessor machine code.
705This machine code exhibits a high degree of non-uniformity similar to the MCS-51.
706However, only a very small subset of the instruction set is considered, and they over-approximate the possibilities of unorthogonality of the instruction set, largely dodging the problems we had to face.
707
708Further, it seems that the definition of the decode function is potentially error prone.
709A small domain specific language of patterns is formalised in HOL4.
710This is similar to the specification language of the x86 instruction set found in manufacturer's data sheets.
711A decode function is implemented by copying lines from data sheets into the proof script.
712
713We are currently considering implementing a similar domain specific language in Matita.
714However, we would prefer to certify in Matita the compiler for this language.
715Data sheets could then be compiled down to the efficient code that we currently provide, instead of inefficiently interpreting the data sheets every time an instruction is executed.
716
717%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
718% SECTION                                                                      %
719%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
720\section{Conclusions}
721\label{sect.conclusions}
722
723\CSC{Tell what is NOT formalized/formalizable: the HEX parser/pretty printer
724 and/or the I/O procedure}
725\CSC{Decode: two implementations}
726\CSC{Discuss over-specification}
727
728- WE FORMALIZE ALSO I/O ETC. NOT ONLY THE INSTRUCTION SELECTION (??)
729  How to test it? Specify it?
730
731\newpage
732
733\appendix
734
735\section{Listing of main O'Caml functions}
736\label{sect.listing.main.ocaml.functions}
737
738\subsubsection{From \texttt{ASMInterpret.ml(i)}}
739
740\begin{center}
741\begin{tabular*}{\textwidth}{p{3cm}@{\quad}p{9cm}}
742Name & Description \\
743\hline
744\texttt{assembly} & Assembles an abstract syntax tree representing an 8051 assembly program into a list of bytes, its compiled form. \\
745\texttt{initialize} & Initializes the emulator status. \\
746\texttt{load} & Loads an assembled program into the emulator's code memory. \\
747\texttt{fetch} & Fetches the next instruction, and automatically increments the program counter. \\
748\texttt{execute} & Emulates the processor.  Accepts as input a function that pretty prints the emulator status after every emulation loop. \\
749\end{tabular*}
750\end{center}
751
752\subsubsection{From \texttt{ASMCosts.ml(i)}}
753
754\begin{center}
755\begin{tabular*}{\textwidth}{p{3cm}@{\quad}p{9cm}}
756Name & Description \\
757\hline
758\texttt{compute} & Computes a map associating costings to basic blocks in the program.
759\end{tabular*}
760\end{center}
761
762\subsubsection{From \texttt{IntelHex.ml(i)}}
763
764\begin{center}
765\begin{tabular*}{\textwidth}{p{3cm}@{\quad}p{9cm}}
766Name & Description \\
767\hline
768\texttt{intel\_hex\_of\_file} & Reads in a file and parses it if in Intel IHX format, otherwise raises an exception. \\
769\texttt{process\_intel\_hex} & Accepts a parsed Intel IHX file and populates a hashmap (of the same type as code memory) with the contents.
770\end{tabular*}
771\end{center}
772
773\subsubsection{From \texttt{Physical.ml(i)}}
774
775\begin{center}
776\begin{tabular*}{\textwidth}{p{3cm}@{\quad}p{9cm}}
777Name & Description \\
778\hline
779\texttt{subb8\_with\_c} & Performs an eight bit subtraction on bitvectors.  The function also returns the most important PSW flags for the 8051: carry, auxiliary carry and overflow. \\
780\texttt{add8\_with\_c} & Performs an eight bit addition on bitvectors.  The function also returns the most important PSW flags for the 8051: carry, auxiliary carry and overflow. \\
781\texttt{dec} & Decrements an eight bit bitvector with underflow, if necessary. \\
782\texttt{inc} & Increments an eight bit bitvector with overflow, if necessary.
783\end{tabular*}
784\end{center}
785
786\newpage
787
788\section{Listing of main Matita functions}
789\label{sect.listing.main.matita.functions}
790
791\subsubsection{From \texttt{Arithmetic.ma}}
792
793\begin{center}
794\begin{tabular*}{\textwidth}{p{3cm}p{9cm}}
795Title & Description \\
796\hline
797\texttt{add\_n\_with\_carry} & Performs an $n$ bit addition on bitvectors.  The function also returns the most important PSW flags for the 8051: carry, auxiliary carry and overflow. \\
798\texttt{sub\_8\_with\_carry} & Performs an eight bit subtraction on bitvectors. The function also returns the most important PSW flags for the 8051: carry, auxiliary carry and overflow. \\
799\texttt{half\_add} & Performs a standard half addition on bitvectors, returning the result and carry bit. \\
800\texttt{full\_add} & Performs a standard full addition on bitvectors and a carry bit, returning the result and a carry bit.
801\end{tabular*}
802\end{center}
803
804\subsubsection{From \texttt{Assembly.ma}}
805
806\begin{center}
807\begin{tabular*}{\textwidth}{p{3cm}p{9cm}}
808Title & Description \\
809\hline
810\texttt{assemble1} & Assembles a single 8051 assembly instruction into its memory representation. \\
811\texttt{assemble} & Assembles an 8051 assembly program into its memory representation.\\
812\texttt{assemble\_unlabelled\_program} &\\& Assembles a list of (unlabelled) 8051 assembly instructions into its memory representation.
813\end{tabular*}
814\end{center}
815
816\subsubsection{From \texttt{BitVectorTrie.ma}}
817
818\begin{center}
819\begin{tabular*}{\textwidth}{p{3cm}p{9cm}}
820Title & Description \\
821\hline
822\texttt{lookup} & Returns the data stored at the end of a particular path (a bitvector) from the trie.  If no data exists, returns a default value. \\
823\texttt{insert} & Inserts data into a tree at the end of the path (a bitvector) indicated.  Automatically expands the tree (by filling in stubs) if necessary.
824\end{tabular*}
825\end{center}
826
827\subsubsection{From \texttt{DoTest.ma}}
828
829\begin{center}
830\begin{tabular*}{\textwidth}{p{3cm}p{9cm}}
831Title & Description \\
832\hline
833\texttt{execute\_trace} & Executes an assembly program for a fixed number of steps, recording in a trace which instructions were executed.
834\end{tabular*}
835\end{center}
836
837\subsubsection{From \texttt{Fetch.ma}}
838
839\begin{center}
840\begin{tabular*}{\textwidth}{p{3cm}p{9cm}}
841Title & Description \\
842\hline
843\texttt{fetch} & Decodes and returns the instruction currently pointed to by the program counter and automatically increments the program counter the required amount to point to the next instruction. \\
844\end{tabular*}
845\end{center}
846
847\subsubsection{From \texttt{Interpret.ma}}
848
849\begin{center}
850\begin{tabular*}{\textwidth}{p{3cm}p{9cm}}
851Title & Description \\
852\hline
853\texttt{execute\_1} & Executes a single step of an 8051 assembly program. \\
854\texttt{execute} & Executes a fixed number of steps of an 8051 assembly program.
855\end{tabular*}
856\end{center}
857
858\subsubsection{From \texttt{Status.ma}}
859
860\begin{center}
861\begin{tabular*}{\textwidth}{p{3cm}p{9cm}}
862Title & Description \\
863\hline
864\texttt{load} & Loads an assembled 8051 assembly program into code memory.
865\end{tabular*}
866\end{center}
867\end{document}
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