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50
51\author{Claudio Sacerdoti Coen \and Dominic P. Mulligan}
52\authorrunning{C. Sacerdoti Coen and D. P. Mulligan}
53\title{An executable formalisation of the MCS-51 microprocessor in Matita}
54\titlerunning{An executable formalisation of the MCS-51}
55\institute{Dipartimento di Scienze dell'Informazione, University of Bologna}
56
57\begin{document}
58
59\maketitle
60
61\begin{abstract}
62We summarise our formalisation of an emulator for the MCS-51 microprocessor in the Matita proof assistant.
63The MCS-51 is a widely used 8-bit microprocessor, especially popular in embedded devices.
64
65We proceeded in two stages, first implementing in O'Caml a prototype emulator, where bugs could be `ironed out' quickly.
66We then ported our O'Caml emulator to Matita's internal language.
67Though mostly straight-forward, this porting presented multiple problems.
68Of particular interest is how we handle the extreme non-orthoganality of the MSC-51's instruction set.
69In O'Caml, this was handled through heavy use of polymorphic variants.
70In Matita, we achieve the same effect through a non-standard use of dependent types.
71
72Both the O'Caml and Matita emulators are `executable'.
73Assembly programs may be animated within Matita, producing a trace of instructions executed.
74
75Our formalisation is a major component of the ongoing EU-funded CerCo project.
76\end{abstract}
77
78%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
79% SECTION                                                                      %
80%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
81\section{Background}
82\label{sect.introduction}
83
84Formal methods are designed to increase our confidence in the design and implementation of software (and hardware).
85Ideally, we would like all software to come equipped with a formal specification, along with a proof of correctness for the implementation.
86Today practically all programs are written in high level languages and then compiled into low level ones.
87Specifications are therefore also given at a high level and correctness can be proved by reasoning automatically or interactively on the program's source code.
88The code that is actually run, however, is not the high level source code that we reason on, but the object code that is generated by the compiler.
89
90A few simple questions now arise:
91\begin{itemize*}
92\item
93What properties are preserved during compilation?
94\item
95What properties are affected by the compilation strategy?
96\item
97To what extent can you trust your compiler in preserving those properties?
98\end{itemize*}
99These questions, and others like them, motivate a current `hot topic' in computer science research: \emph{compiler verification}.
100So far, the field has been focused on the first and last questions only.
101In particular, much attention has been placed on verifying compiler correctness with respect to extensional properties of programs, which are easily preserved during compilation; it is sufficient to completely preserve the denotational semantics of the input program.
102
103However, if we consider intensional properties of programs---such as space, time or energy spent into computation and transmission of data---the situation is more complex.
104To express even be able to express these properties, and to be able to reason about them, we are forced to adopt a cost model that assigns a cost to single, or blocks, of instructions.
105Ideally, we would like to have a compositional cost model that assigns the same cost to all occurrences of one instruction.
106However, compiler optimizations are inherently non-compositional: each occurrence of a high level instruction is usually compiled in a different way according to the context it finds itself in.
107Therefore both the cost model and intensional specifications are affected by the compilation process.
108
109In the current EU Project CerCo (`Certified Complexity') we approach the problem of reasoning about intensional properties of programs as follows.
110We are currently developing a compiler that induces a cost model on the high level source code.
111Costs are assigned to each block of high level instructions by considering the costs of the corresponding blocks of compiled object code.
112The cost model is therefore inherently non compositional.
113However, the model has the potential to be extremely \emph{precise}, capturing a program's \emph{realistic} cost, by taking into account, not ignoring, the compilation process.
114A prototype compiler, where no approximation of the cost is provided, has been developed.
115
116We believe that our approach is especially applicable to certifying real time programs.
117Here, a user can certify that all `deadlines' are met whilst wringing as many clock cycles from the processor---using a cost model that does not over-estimate---as possible.
118
119Other applications of our approach are in the domain of compiler verification
120itself. For instance, an extensional specification of an optimization is useless
121since it grants preservation of the semantics without stating that the cost
122(in space or time) of the optimized code should be lower. Another example is
123completeness and correctness of the compilation process in presence of
124space constraints: the compiler could refuse a source
125program for an embedded system when the size of the compiled code exceeds the
126available ROM size. Moreover, preservation of the semantics must be required
127only for those programs that do not exhausts their stack/heap space. Hence the
128statement of completeness of the compiler must take in account the realistic
129cost model.
130
131In the methodology proposed in CerCo we assume to be able to compute on the
132object code exact and realistic costs for sequential blocks of instructions.
133With modern processors, it is possible~\cite{??,??,??}, but difficult,
134to compute exact costs or to reasonably approximate them, since the execution
135of the program itself has an influence on the speed of processing. This is due
136mainly to caching effects and memory effects in the processor, used, for
137instance, to perform branch prediction. For this reason, at the current stage
138of CerCo we decided to focus on 8-bits microprocessors that are still widely
139used in embedded systems and whose cost model is easily predictable.
140
141In particular, we have fully formalized an executable formal semantics of
142the Family of 8 bits Freescale Microprocessors~\cite{oliboni} and a similar
143one for the MCS-51 microprocessors. The latter is the one described in this
144paper. The main focus of the formalization has been on capturing the
145intensional behaviour of the processor. The main problems we have faced,
146however, are mainly due to the extreme unorthogonality of the memory model
147and instruction sets of the MCS-51 microprocessors. To cope with this
148unorthogonality and to have executability, we have exploited the dependent
149type system of the interactive theorem prover Matita.
150
151%Compiler verification, as of late, is a `hot topic' in computer science research.
152%This rapidly growing field is motivated by one simple question: `to what extent can you trust your compiler?'
153%Existing verification efforts have broadly focussed on \emph{semantic correctness}, that is, creating a compiler that is guaranteed to preserve the semantics of a program during the compilation process.
154%However, there is another important facet of correctness that has not garnered much attention, that is, correctness with respect to some intensional properties of the program to be compiled.
155
156\subsection{The 8051/8052}
157\label{subsect.8051-8052}
158
159The MCS-51 is an eight bit microprocessor introduced by Intel in the late 1970s.
160Commonly called the 8051, in the three decades since its introduction the processor has become a highly popular target for embedded systems engineers.
161Further, the processor and its immediate successor, the 8052, is still manufactured by a host of semiconductor suppliers---many of them European---including Atmel, Siemens Semiconductor, NXP (formerly Phillips Semiconductor), Texas Instruments, and Maxim (formerly Dallas Semiconductor).
162
163The 8051 is a well documented processor, and has the additional support of numerous open source and commercial tools, such as compilers for high-level languages and emulators.
164For instance, the open source Small Device C Compiler (SDCC) recognises a dialect of C, and other compilers targeting the 8051 for BASIC, Forth and Modula-2 are also extant.
165An open source emulator for the processor, MCU8051 IDE, is also available.
166
167\begin{figure}[t]
168\begin{center}
169\includegraphics[scale=0.5]{memorylayout.png}
170\end{center}
171\caption{High level overview of the 8051 memory layout}
172\label{fig.memory.layout}
173\end{figure}
174
175The 8051 has a relatively straightforward architecture, unencumbered by advanced features of modern processors, making it an ideal target for formalisation.
176A high-level overview of the processor's memory layout is provided in Figure~\ref{fig.memory.layout}.
177
178Processor RAM is divided into numerous segments, with the most prominent division being between internal and (optional) external memory.
179Internal memory, commonly provided on the die itself with fast access, is further divided into 128 bytes of internal RAM and numerous Special Function Registers (SFRs) which control the operation of the processor.
180Internal RAM (IRAM) is further divided into a eight general purpose bit-addressable registers (R0--R7).
181These sit in the first eight bytes of IRAM, though can be programmatically `shifted up' as needed.
182Bit memory, followed by a small amount of stack space resides in the memory space immediately after the register banks.
183What remains of the IRAM may be treated as general purpose memory.
184A schematic view of IRAM layout is provided in Figure~\ref{fig.iram.layout}.
185
186External RAM (XRAM), limited to 64 kilobytes, is optional, and may be provided on or off chip, depending on the manufacturer.
187XRAM is accessed using a dedicated instruction.
188External code memory (XCODE) is often stored in the form of an EPROM, and limited to 64 kilobytes in size.
189However, depending on the particular manufacturer and processor model, a dedicated on-die read-only memory area for program code (ICODE) may also be supplied.
190
191Memory may be addressed in numerous ways: immediate, direct, indirect, external direct and code indirect.
192As the latter two addressing modes hint, there are some restrictions enforced by the 8051 and its derivatives on which addressing modes may be used with specific types of memory.
193For instance, the 128 bytes of extra internal RAM that the 8052 features cannot be addressed using indirect addressing; rather, external (in)direct addressing must be used.
194
195The 8051 series possesses an eight bit Arithmetic and Logic Unit (ALU), with a wide variety of instructions for performing arithmetic and logical operations on bits and integers.
196Further, the processor possesses two eight bit general purpose accumulators, A and B.
197
198Communication with the device is facilitated by an onboard UART serial port, and associated serial controller, which can operate in numerous modes.
199Serial baud rate is determined by one of two sixteen bit timers included with the 8051, which can be set to multiple modes of operation.
200(The 8052 provides an additional sixteen bit timer.)
201As an additional method of communication, the 8051 also provides a four byte bit-addressable input-output port.
202
203The programmer may take advantage of the interrupt mechanism that the processor provides.
204This is especially useful when dealing with input or output involving the serial device, as an interrupt can be set when a whole character is sent or received via the serial port.
205
206Interrupts immediately halt the flow of execution of the processor, and cause the program counter to jump to a fixed address, where the requisite interrupt handler is stored.
207However, interrupts may be set to one of two priorities: low and high.
208The interrupt handler of an interrupt with high priority is executed ahead of the interrupt handler of an interrupt of lower priority, interrupting a currently executing handler of lower priority, if necessary.
209
210The 8051 has interrupts disabled by default.
211The programmer is free to handle serial input and output manually, by poking serial flags in the SFRs.
212Similarly, `exceptional circumstances' that would otherwise trigger an interrupt on more modern processors, for example, division by zero, are also signalled by setting flags.
213
214\begin{figure}[t]
215\begin{center}
216\includegraphics[scale=0.5]{iramlayout.png}
217\end{center}
218\caption{Schematic view of 8051 IRAM layout}
219\label{fig.iram.layout}
220\end{figure}
221
222%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
223% SECTION                                                                      %
224%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
225\subsection{Overview of paper}
226\label{subsect.overview.paper}
227
228In Section~\ref{sect.development.strategy} we provide a brief overview of how we designed and implemented the formalised microprocessor emulator.
229In Section~\ref{sect.design.issues.formalisation} we describe how we made use of dependent types to handle some of the idiosyncracies of the microprocessor.
230In Section~\ref{sect.related.work} we describe the relation our work has to
231
232%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
233% SECTION                                                                      %
234%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
235\section{From O'Caml prototype to Matita formalisation}
236\label{sect.from.o'caml.prototype.matita.formalisation}
237
238Our implementation progressed in two stages:
239
240\paragraph{O'Caml prototype}
241We began with an emulator written in O'Caml.
242We used this to `iron out' any bugs in our design and implementation within O'Caml's more permissive type system.
243O'Caml's ability to perform file input-output also eased debugging and validation.
244Once we were happy with the performance and design of the O'Caml emulator, we moved to the Matita formalisation.
245
246\paragraph{Matita formalisation}
247Matita's syntax is lexically similar to O'Caml's.
248This eased the translation, as large swathes of code were merely copy-pasted with minor modifications.
249However, several major issues had to be addresses when moving from O'Caml to Matita.
250These are now discussed.
251
252%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
253% SECTION                                                                      %
254%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
255\section{Design issues in the formalisation}
256\label{sect.design.issues.formalisation} 
257
258%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
259% SECTION                                                                      %
260%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
261\subsection{Labels and pseudoinstructions}
262\label{subsect.labels.pseudoinstructions}
263
264As part of the CerCo project, a prototype compiler was being developed in parallel with the emulator.
265Easing the design of the compiler was a key objective in implementing the emulator.
266For this reason, we introduced notion of \emph{pseudoinstruction} and \emph{label}.
267
268The MCS-51's instruction set has numerous instructions for unconditional and conditional jumps to memory locations, calling procedures and moving data between memory spaces.
269For instance, the instructions \texttt{AJMP}, \texttt{JMP} and \texttt{LJMP} all perform unconditional jumps.
270However, these instructions differ in how large the maximum size of the offset of the jump to be performed can be.
271Further, all jump instructions require a concrete memory address, to jump to, to be specified.
272Requiring the compiler to compute these offsets, and select appropriate jump instructions, was seen as needleslly burdensome.
273
274Instead, we introduced generic \texttt{Jump}, \texttt{Call} and \texttt{Move} instructions.
275These are expanded into MCS-51 assembly instructions with an assembly phase, prior to program execution.
276Further, we introduced a notion of label (represented by strings), and introduced pseudoinstructions that allow conditional jumps to jump to labels.
277These are also removed during the assembly phase, and replaced by concrete memory addresses and offsets.
278
279%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
280% SECTION                                                                      %
281%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
282\subsection{Representing memory}
283\label{subsect.representing.memory}
284
285%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
286% SECTION                                                                      %
287%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
288\subsection{Putting dependent types to work}
289\label{subsect.putting.dependent.types.to.work}
290
291We typeset O'Caml source with blue, and Matita source with red.
292
293A peculiarity of the MCS-51 is the non-orthogonality of its instruction set.
294For instance, the \texttt{MOV} instruction, can be invoked using one of sixteen combinations of addressing modes.
295
296Such non-orthogonality in the instruction set was handled with the use of polymorphic variants in the O'Caml emulator.
297For instance, we introduced types corresponding to each addressing mode:
298\begin{quote}
299\begin{lstlisting}
300type direct = [ `DIRECT of byte ]
301type indirect = [ `INDIRECT of bit ]
302...
303\end{lstlisting}
304\end{quote}
305Which were then used in our inductive datatype for assembly instructions, as follows:
306\begin{quote}
307\begin{lstlisting}
308type 'addr preinstruction =
309 [ `ADD of acc * [ reg | direct | indirect | data ]
310...
311 | `MOV of
312    (acc * [ reg | direct | indirect | data ],
313     [ reg | indirect ] * [ acc | direct | data ],
314     direct * [ acc | reg | direct | indirect | data ],
315     dptr * data16,
316     carry * bit,
317     bit * carry
318     ) union6
319...
320\end{lstlisting}
321\end{quote}
322Here, \texttt{union6} is a disjoint union type, defined as follows:
323\begin{quote}
324\begin{lstlisting}
325type ('a,'b,'c,'d,'e,'f) union6 = [ `U1 of 'a | ... | `U6 of 'f ]
326\end{lstlisting}
327\end{quote}
328For our purposes, the types \texttt{union2}, \texttt{union3} and \texttt{union6} sufficed.
329
330This polymorphic variant machinery worked well: it introduced a certain level of type safety (for instance, the type of our \texttt{MOV} instruction above guarantees it cannot be invoked with arguments in the \texttt{carry} and \texttt{data16} addressing modes, respectively), and also allowed us to pattern match against instructions, when necessary.
331However, this polymorphic variant machinery is \emph{not} present in Matita.
332We needed some way to produce the same effect, which Matita supported.
333For this task, we used dependent types.
334
335We first provided an inductive data type representing all possible addressing modes, a type that functions will pattern match against:
336\begin{quote}
337\begin{lstlisting}
338inductive addressing_mode: Type[0] ≝
339  DIRECT: Byte $\rightarrow$ addressing_mode
340| INDIRECT: Bit $\rightarrow$ addressing_mode
341...
342\end{lstlisting}
343\end{quote}
344We also wished to express in the type of functions the \emph{impossibility} of pattern matching against certain constructors.
345In order to do this, we introduced an inductive type of addressing mode `tags'.
346The constructors of \texttt{addressing\_mode\_tag} are in one-to-one correspondence with the constructors of \texttt{addressing\_mode}:
347\begin{quote}
348\begin{lstlisting}
349inductive addressing_mode_tag : Type[0] ≝
350  direct: addressing_mode_tag
351| indirect: addressing_mode_tag
352...
353\end{lstlisting}
354\end{quote}
355A function that checks whether an \texttt{addressing\_mode} is `morally' an \texttt{addressing\_mode\_tag} is provided, as follows:
356\begin{quote}
357\begin{lstlisting}
358let rec is_a (d: addressing_mode_tag) (A: addressing_mode) on d ≝
359  match d with
360   [ direct $\Rightarrow$ match A with [ DIRECT _ $\Rightarrow$ true | _ $\Rightarrow$ false ]
361   | indirect $\Rightarrow$ match A with [ INDIRECT _ $\Rightarrow$ true | _ $\Rightarrow$ false ]
362...
363\end{lstlisting}
364\end{quote}
365We also extend this check to vectors of \texttt{addressing\_mode\_tag}'s in the obvious manner:
366\begin{quote}
367\begin{lstlisting}
368let rec is_in (n) (l: Vector addressing_mode_tag n) (A: addressing_mode) on l ≝
369 match l return $\lambda$m.$\lambda$_: Vector addressing_mode_tag m. bool with
370  [ VEmpty $\Rightarrow$ false
371  | VCons m he (tl: Vector addressing_mode_tag m) $\Rightarrow$
372     is_a he A $\vee$ is_in ? tl A ].
373\end{lstlisting}
374\end{quote}
375Here \texttt{VEmpty} and \texttt{VCons} are the two constructors of the \texttt{Vector} data type, and $\mathtt{\vee}$ is inclusive disjunction on Booleans.
376\begin{quote}
377\begin{lstlisting}
378record subaddressing_mode (n: Nat) (l: Vector addressing_mode_tag (S n)) : Type[0] ≝
379{
380  subaddressing_modeel :> addressing_mode;
381  subaddressing_modein: bool_to_Prop (is_in ? l subaddressing_modeel)
382}.
383\end{lstlisting}
384\end{quote}
385We can now provide an inductive type of preinstructions with precise typings:
386\begin{quote}
387\begin{lstlisting}
388inductive preinstruction (A: Type[0]): Type[0] ≝
389   ADD: $\llbracket$ acc_a $\rrbracket$ $\rightarrow$ $\llbracket$ register; direct; indirect; data $\rrbracket$ $\rightarrow$ preinstruction A
390 | ADDC: $\llbracket$ acc_a $\rrbracket$ $\rightarrow$ $\llbracket$ register; direct; indirect; data $\rrbracket$ $\rightarrow$ preinstruction A
391...
392\end{lstlisting}
393\end{quote}
394Here $\llbracket - \rrbracket$ is syntax denoting a vector.
395We see that the constructor \texttt{ADD} expects two parameters, the first being the accumulator A (\texttt{acc\_a}), and the second being one of a register, direct, indirect or data addressing mode.
396
397The final, missing component is a pair of type coercions from \texttt{addressing\_mode} to \texttt{subaddressing\_mode} and from \texttt{subaddressing\_mode} to \texttt{Type$\lbrack0\rbrack$}, respectively.
398The previous machinery allows us to state in the type of a function what addressing modes that function expects.
399For instance, consider \texttt{set\_arg\_16}, which expects only a \texttt{DPTR}:
400\begin{quote}
401\begin{lstlisting}
402definition set_arg_16: Status $\rightarrow$ Word $\rightarrow$ $\llbracket$ dptr $\rrbracket$ $\rightarrow$ Status ≝
403  $\lambda$s, v, a.
404   match a return $\lambda$x. bool_to_Prop (is_in ? $\llbracket$ dptr $\rrbracket$ x) $\rightarrow$ ? with
405     [ DPTR $\Rightarrow$ $\lambda$_: True.
406       let 〈 bu, bl 〉 := split $\ldots$ eight eight v in
407       let status := set_8051_sfr s SFR_DPH bu in
408       let status := set_8051_sfr status SFR_DPL bl in
409         status
410     | _ $\Rightarrow$ $\lambda$_: False.
411       match K in False with
412       [
413       ]
414     ] (subaddressing_modein $\ldots$ a).
415\end{lstlisting}
416\end{quote}
417All other cases are discharged by the catch-all at the bottom of the match expression.
418Attempting to match against another addressing mode not indicated in the type (for example, \texttt{REGISTER}) will produce a type-error.
419
420%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
421% SECTION                                                                      %
422%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
423\section{Validation}
424\label{sect.validation}
425
426We spent considerable effort attempting to ensure that our formalisation is correct, that is, what we have formalised really is an accurate model of the MCS-51 microprocessor.
427
428First, we made use of multiple data sheets, each from a different semiconductor manufacturer.
429This helped us spot errors in the specification of the processor's instruction set, and its behaviour.
430
431The O'Caml prototype was especially useful for validation purposes.
432This is because we wrote a module for parsing and loading the Intel HEX file format.
433HEX is a standard format that all compilers targetting the MCS-51, and similar processors, produce.
434It is essentially a snapshot of the processor's code memory in compressed form.
435Using this, we were able to compile C programs with SDCC, an open source compiler, and load the resulting program directly into our emulator's code memory, ready for execution.
436Further, we are able to produce a HEX file from our emulator's code memory, for loading into third party tools.
437After each step of execution, we can print out both the instruction that had been executed, along with its arguments, and a snapshot of the processor's state, including all flags and register contents.
438For example:
439\begin{frametxt}
440\begin{verbatim}
441...
442
44308: mov 81 #07
444
445 Processor status:                               
446
447   ACC : 0 (00000000) B   : 0 (00000000)
448   PSW : 0 (00000000) with flags set as:
449     CY  : false   AC  : false
450     FO  : false   RS1 : false
451     RS0 : false   OV  : false
452     UD  : false   P   : false
453   SP  : 7 (00000111) IP  : 0 (00000000)
454   PC  : 8 (0000000000001000)
455   DPL : 0 (00000000) DPH : 0 (00000000)
456   SCON: 0 (00000000) SBUF: 0 (00000000)
457   TMOD: 0 (00000000) TCON: 0 (00000000)
458   Registers:                                   
459    R0 : 0 (00000000) R1 : 0 (00000000)
460    R2 : 0 (00000000) R3 : 0 (00000000)
461    R4 : 0 (00000000) R5 : 0 (00000000)
462    R6 : 0 (00000000) R7 : 0 (00000000)
463
464...
465\end{verbatim}
466\end{frametxt}
467Here, the traces indicates that the instruction \texttt{mov 81 \#07} has just been executed by the processor, which is now in the state indicated.
468These traces were useful in spotting anything that was `obviously' wrong with the execution of the program.
469
470Further, we made use of an open source emulator for the MCS-51, \texttt{mcu8051ide}.
471Using our execution traces, we were able to step through a compiled program, one instruction at a time, in \texttt{mcu8051ide}, and compare the resulting execution trace with the trace produced by our emulator.
472
473Our Matita formalisation was largely copied from the O'Caml source code, apart from changes related to addressing modes already mentioned.
474However, as the Matita emulator is executable, we could perform further validation by comparing the trace of a program's execution in the Matita emulator with the trace of the same program in the O'Caml emulator.
475
476%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
477% SECTION                                                                      %
478%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
479\section{Related work}
480\label{sect.related.work}
481
482%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
483% SECTION                                                                      %
484%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
485\section{Conclusions}
486\label{sect.conclusions}
487
488\end{document}
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