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1\documentclass[10pt, a4paper]{llncs}
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61\author{Dominic P. Mulligan \and Claudio Sacerdoti Coen}
62\authorrunning{D. P. Mulligan \and C. Sacerdoti Coen}
64% \institute{Dipartimento di Scienze dell'Informazione,\\ Universit\`a di Bologna}
68\title{An executable formalisation of the MCS-51 microprocessor in Matita
69 \thanks{The project CerCo acknowledges the financial support of the Future and Emerging Technologies (FET) programme within the Seventh Framework Programme for Research of the European Commission, under FET-Open grant number: 243881}}
74We summarise the formalisation of emulators for the MCS-51 microprocessor in O'Caml and the Matita proof assistant.
75The MCS-51 is a widely used microprocessor, especially popular in embedded devices.
77The O'Caml emulator is intended to be `feature complete' with respect to the MCS-51 device.
78However, the Matita emulator is intended to be used as a target for a certified, complexity preserving C compiler, as part of the EU-funded CerCo project.
79As a result, not all features of the MCS-51 are formalised in the Matita emulator.
80Both the O'Caml and Matita emulators are `executable'.
81Assembly programs may be animated within Matita, producing a trace of instructions executed.
85%Hardware formalisation, Matita, dependent types, CerCo
89% SECTION                                                                      %
94Formal methods aim to increase our confidence in the design and implementation of software.
95Ideally, all software should come equipped with a formal specification and a proof of correctness for the corresponding implementation.
96The majority of programs are written in high level languages and then compiled into low level ones.
97Specifications are therefore also given at a high level and correctness can be proved by reasoning on the program's source code.
98The code that is actually run is not the high level source code that we reason on, but low level code generated by the compiler.
99A few questions now arise:
102What properties are preserved during compilation?
104What properties are affected by the compilation strategy?
106To what extent can you trust your compiler in preserving those properties?
108These and other questions motivate a current `hot topic' in computer science research: \emph{compiler verification} (e.g.~\cite{chlipala:verified:2010,leroy:formal:2009}, and so on).
109So far, the field has only been focused on the first and last questions.
110Much attention has been placed on verifying compiler correctness with respect to extensional properties of programs.
111These are `easily' preserved during compilation.
113If we consider intentional properties of programs---space, time, and so forth---the situation is more complex.
114To express these properties, and reason about them, we must adopt a cost model that assigns a cost to single, or blocks, of instructions.
115A compositional cost model, assigning the same cost to all occurrences of one instruction, would be ideal.
116However, compiler optimisations are inherently non-compositional: each occurrence of a high level instruction may be compiled in a different way depending on its context.
117Therefore both the cost model and intentional specifications are affected by the compilation process.
119In the CerCo project (`Certified Complexity')~\cite{cerco:2011} we approach the problem of reasoning about intentional properties of programs as follows.
120We are currently developing a compiler that induces a cost model on high level source code.
121Costs are assigned to each block of high level instructions by considering the costs of the corresponding blocks of compiled code.
122The cost model is therefore inherently non-compositional, but has the potential to be extremely \emph{precise}, capturing a program's \emph{realistic} cost.
123That is, the compilation process is taken into account, not ignored.
124A prototype compiler, where no approximation of the cost is provided, has been developed.
125(The technical details of the cost model is explained in~\cite{amadio:certifying:2010}.)
127We believe that our approach is applicable to certifying real time programs.
128A user can certify that `deadlines' are met whilst wringing as many clock cycles from the processor---using a cost model that does not over-estimate---as possible.
130Our approach is also relevant to compiler verification and construction.
131\emph{An optimisation specified only extensionally is only half specified}; the optimisation may preserve the denotational semantics of a program, but there is no guarantee that intentional properties of the program improve.
133Another potential application is the completeness and correctness of the compilation process in the presence of space constraints.
134A compiler could reject a source program targetting an embedded system when the size of the compiled code exceeds available ROM size.
135Preservation of semantics may only be required for those programs that do not exhaust the stack or heap.
136The statement of completeness of the compiler must take into account a realistic cost model.
138With the CerCo methodology, we assume we can assign to object code exact and realistic costs for sequential blocks of instructions.
139The WCET community has developed complex tools for bounding the worst-case execution times of sequential blocks on modern processors.
140WCET analysis takes place at the object code level.
141However, it is more convenient to reason about programs at a much higher-level of abstraction.
142Therefore, the analysis must be reflected back onto the original source code.
143This reflection process is completely `untrusted' and makes strong assumptions about the internal design and correctness of the compiler.
144For example, some WCET analysis tools, to maximise precision, require a programmer-provided strict upper bound on the number of loop iterations.
145Compiler optimizations could rearrange code in such a manner that the upper bound is no longer strict.
146The certified CerCo C compiler validates such strong assumptions, and a certified analysis tool could be obtained by combining the CerCo compiler with any certified WCET tool.
148We are interested in building a fully certified tool.
149However we are not able to build a certified WCET tool \emph{and} certified C compiler within the confines of the CerCo project.
150We therefore focus on certifying the compiler by targetting a microprocessor where complex WCET analyses are not required.
152Caching, memory effects, and advanced features such as branch prediction all have an effect on the complexity of WCET analyses (see~\cite{bate:wcet:2011,yan:wcet:2008}, and so on).
153CerCo therefore decided to focus on 8-bit microprocessors, which are still used in embedded systems.
154These have a predictable, precise cost model due to their relative paucity of features.
155Manufacturer timesheets provide \emph{exact guarantees} for the number of processor cycles each instruction will take to execute.
157We have fully formalised an executable formal semantics of a family of 8-bit Freescale microprocessors~\cite{oliboni:matita:2008}, and provided a similar executable formal semantics for the MCS-51 microprocessor.
158The latter is what we describe in this paper.
159The focus of the formalisation has been on capturing the intentional behaviour of the processor; this is not novel.
160However, the design of the MCS-51 itself has caused problems in the formalisation.
161For example, the MCS-51 has a highly unorthogonal instruction set.
162To cope with this unorthogonality, and to produce an executable specification, we rely on the dependent types of Matita, an interactive proof assistant~\cite{asperti:user:2007}.
163The manner in which we combined dependent types and coercions to handle this problem is novel.
165\paragraph*{The MCS-51}\quad
166The MCS-51 is an 8-bit microprocessor.
167Commonly called the 8051, since its introduction by Intel the processor has become a popular component of embedded systems.
168Despite being manufactured \emph{en masse}, there is not yet a formal model of the MCS-51.
170The 8051 is a well documented processor, with very few underspecified behaviours (almost all of these correspond to erroneous usage of the processor).
171The processor also has the support of numerous open source and commercial tools, such as compilers and emulators.
172For instance, the open source Small Device C Compiler (SDCC) recognises a dialect of C~\cite{sdcc:2010}, and other compilers for BASIC, Forth and Modula-2 are also extant.
173An open source emulator for the processor, MCU 8051 IDE, is also available~\cite{mcu8051ide:2010}.
174Both MCU 8051 IDE and SDCC were used in for validating the formalisation.
182\put(12,410){\makebox(80,0)[b]{Internal (256B)}}
186\put(12,400){\makebox(0,0)[r]{0h}}  \put(14,400){\makebox(0,0)[l]{Register bank 0}}
188\put(12,386){\makebox(0,0)[r]{8h}}  \put(14,386){\makebox(0,0)[l]{Register bank 1}}
190\put(12,372){\makebox(0,0)[r]{10h}}  \put(14,372){\makebox(0,0)[l]{Register bank 2}}
192\put(12,358){\makebox(0,0)[r]{18h}} \put(14,358){\makebox(0,0)[l]{Register bank 3}}
194\put(12,344){\makebox(0,0)[r]{20h}} \put(14,344){\makebox(0,0)[l]{Bit addressable}}
197  \put(14,309){\makebox(0,0)[l]{\quad \vdots}}
200  \put(14,263){\makebox(0,0)[l]{\quad \vdots}}
217% bit access to sfrs?
225\put(164,410){\makebox(80,0)[b]{External (64kB)}}
231\put(164,324){\makebox(80,0){Paged access}}
232  \put(164,310){\makebox(80,0){Direct/indirect}}
234  \put(164,228){\makebox(80,0){\vdots}}
235  \put(164,210){\makebox(80,0){Direct/indirect}}
237\put(264,410){\makebox(80,0)[b]{Code (64kB)}}
242  \put(264,228){\makebox(80,0){\vdots}}
243  \put(264,324){\makebox(80,0){Direct}}
244  \put(264,310){\makebox(80,0){PC relative}}
246\caption{The 8051 memory model}
250The 8051 has a relatively straightforward architecture.
251A high-level overview of the processor's memory layout, along with the ways in which different memory spaces may be addressed, is provided in Figure~\ref{fig.memory.layout}.
253Processor RAM is divided into numerous segments, with the most prominent division being between internal and (optional) external memory.
254Internal memory, commonly provided on the die itself with fast access, is composed of 256 bytes, but, in direct addressing mode, half of them are overloaded with 128 bytes of memory-mapped Special Function Registers (SFRs).
255SFRs control the operation of the processor.
256Internal RAM (IRAM) is divided again into 8 general purpose bit-addressable registers (R0--R7).
257These sit in the first 8 bytes of IRAM, though can be programmatically `shifted up' as needed.
258Bit memory, followed by a small amount of stack space, resides in the memory space immediately following the register banks.
259What remains of IRAM may be treated as general purpose memory.
260A schematic view of IRAM is also provided in Figure~\ref{fig.memory.layout}.
262External RAM (XRAM), limited to a maximum size of 64 kilobytes, is optional, and may be provided on or off chip, depending on the vendor.
263XRAM is accessed using a dedicated instruction, and requires 16 bits to address fully.
264External code memory (XCODE) is often stored as an EPROM, and limited to 64 kilobytes in size.
265However, depending on the particular processor model, a dedicated on-die read-only memory area for program code (ICODE) may be supplied.
267Memory may be addressed in numerous ways: immediate, direct, indirect, external direct and code indirect.
268As the latter two addressing modes hint, there are some restrictions enforced by the 8051, and its derivatives, on which addressing modes may be used with specific types of memory.
269For instance, the extra 128 bytes of IRAM of the 8052 cannot be addressed using indirect addressing; rather, external (in)direct addressing must be used. Moreover, some memory segments are addressed using 8-bit pointers while others require 16-bits.
271The 8051 possesses an 8-bit Arithmetic and Logic Unit (ALU), with a variety of instructions for performing arithmetic and logical operations on bits and integers.
272Two 8-bit general purpose accumulators, A and B, are provided.
274Communication with the device is handled by a UART serial port and controller.
275This can operate in numerous modes.
276Serial baud rate is determined by one of two 16-bit timers included with the 8051, which can be set to multiple modes of operation.
277(The 8052 provides an additional 16-bit timer.)
278The 8051 also provides a 4 byte bit-addressable I/O port.
280The programmer may take advantage of an interrupt mechanism.
281This is especially useful when dealing with I/O involving the serial device, as an interrupt can be set when a whole character is sent or received via the UART.
283Interrupts immediately halt the flow of execution of the processor, and cause the program counter to jump to a fixed address, where the requisite interrupt handler is stored.
284However, interrupts may be set to one of two priorities: low and high.
285The interrupt handler of an interrupt with high priority is executed ahead of the interrupt handler of an interrupt of lower priority, interrupting a currently executing handler of lower priority, if necessary.
287The 8051 has interrupts disabled by default.
288The programmer is free to handle serial input and output manually, by poking serial flags in the SFRs.
289`Exceptional circumstances' that would otherwise trigger an interrupt on more modern processors, (e.g. division by zero) are also signalled by setting flags.
295%\caption{Schematic view of 8051 IRAM layout}
299\paragraph*{Overview of paper}\quad
300In Section~\ref{} we discuss design issues in the development of the formalisation.
301In Section~\ref{sect.validation} we discuss validation of the emulator to ensure that what we formalised was an accurate model of an MCS-51 series microprocessor.
302In Section~\ref{} we describe previous work, with an eye toward describing its relation with the work described herein.
303In Section~\ref{sect.conclusions} we conclude.
306% SECTION                                                                      %
308\section{Design issues in the formalisation}
311We implemented two emulators, one in O'Caml and one in Matita.
312The O'Caml emulator is intended to be `feature complete' with respect to the MCS-51 device.
313However, the Matita emulator is intended to be used as a target for a certified, complexity preserving C compiler.
314As a result, not all features of the MCS-51 are formalised in the Matita emulator.
316We designed the O'Caml emulator to be as efficient as possible, under the constraint that it would be eventually translated into Matita.
317One performance drain in the O'Caml emulator is the use of purely functional map datastructures to represent memory spaces, used to maintain the close correspondence between the Matita and O'Caml emulators.
319Matita~\cite{asperti:user:2007} is a proof assistant based on the Calculus of Coinductive constructions, similar to Coq.
320As a programming language, Matita corresponds to the functional fragment of O'Caml extended with dependent types.
321Matita also features a rich higher-order logic for reasoning about programs, including a universe hierarchy with a single impredicative universe, \texttt{Prop}, and potentially infinitely many predicative universes \texttt{Type[i]} for $0 \geq i$.
322Unlike O'Caml, all recursive functions admitted by the Matita typechecker must be structurally recursive and total.
324We box Matita code to distinguish it from O'Caml code.
325In Matita `\texttt{$?$}' and  `\texttt{$\ldots$}' are arguments to be inferred automatically.
327A full account of the formalisation can be found in~\cite{cerco-report-code:2011}.
328All source code is available from the CerCo project website~\cite{cerco-report-code:2011}.
331% SECTION                                                                      %
333\subsection{Representation of bytes, words, etc.}
340type 'a vect = bit list
341type nibble = [`Sixteen] vect
342type byte = [`Eight] vect
343let split_word w = split_nth 4 w
344let split_byte b = split_nth 2 b
351type 'a vect
352type word = [`Sixteen] vect
353type byte = [`Eight] vect
354val split_word: word -> byte * word
355val split_byte: byte -> nibble * nibble
358\caption{Sample of O'Caml implementation and interface for bitvectors module}
362The formalization of MCS-51 must deal with bytes (8-bits), words (16-bits), and also more esoteric quantities (7, 3 and 9-bits).
363To avoid difficult-to-trace size mismatch bugs, we represented all quantities using bitvectors, i.e. fixed length vectors of booleans.
364In the O'Caml emulator, we `faked' bitvectors using phantom types~\cite{leijen:domain:1999} implemented with polymorphic variants~\cite{garrigue:programming:1998}, as in Figure~\ref{fig.ocaml.implementation.bitvectors}.
365From within the bitvector module (top) bitvectors are just lists of bits and no guarantee is provided on sizes.
366However, the module's interface (bottom) enforces size invariants in the rest of the code.
368In Matita, we are able to use the full power of dependent types to always work with vectors of a known size:
370inductive Vector (A: Type[0]): nat $\rightarrow$ Type[0] ≝
371  VEmpty: Vector A O
372| VCons: $\forall$n: nat. A $\rightarrow$ Vector A n $\rightarrow$ Vector A (S n).
374\texttt{BitVector} is a specialization of \texttt{Vector} to \texttt{bool}.
375We may use Matita's type system to provide precise typings for functions that are polymorphic in the size without code duplication:
377let rec split (A: Type[0]) (m,n: nat) on m: Vector A (m+n) $\rightarrow$ (Vector A m)$\times$(Vector A n) := ...
381% SECTION                                                                      %
383\subsection{Representing memory}
386The MCS-51 has numerous disjoint memory spaces addressed by differently sized pointers.
387In the O'Caml implementation, we use a map data structure (from the standard library) for each space.
388In Matita, we exploited dependent types to design a data structure which enforced the correspondence between the size of pointer and the size of the memory space.
389Further, we assumed that large swathes of memory would often be uninitialized (an assumption on the behaviour of the programmer, not the processor!)
391We use a modified form of trie of fixed height $h$.
392Paths are represented by bitvectors (used also for addresses and registers) of length $h$:
394inductive BitVectorTrie(A: Type[0]):nat $\rightarrow$ Type[0] :=
395  Leaf: A $\rightarrow$ BitVectorTrie A 0
396| Node: ∀n. BitVectorTrie A n $\rightarrow$ BitVectorTrie A n $\rightarrow$ BitVectorTrie A (S n)
397| Stub: ∀n. BitVectorTrie A n.
399\texttt{Stub} is a constructor that can appear at any point in a trie.
400It represents `uninitialized data'.
401Performing a lookup in memory is now straight-forward.
402The only subtlety over normal trie lookup is how we handle \texttt{Stub}.
403We traverse a path, and upon encountering \texttt{Stub}, we return a default value.
404All manufacturer data sheets that we consulted were silent on the subject of what should be returned if we attempt to access uninitialized memory.
405We defaulted to simply returning zero, though our \texttt{lookup} function is parametric in this choice.
406This is reasonable, as SDCC for instance generates code which first `zeroes' memory in a preamble before executing the program proper.
407This is in line with the C standard, which guarantees that all global variables will be zero initialized piecewise.
409\texttt{BitVectorTrie} and \texttt{Vector}, and related functions, can be used in the formalisation of other microprocessors.
412% SECTION                                                                      %
414\subsection{Labels and pseudoinstructions}
417Aside from implementing the core MCS-51 instruction set, we also provided \emph{pseudoinstructions}, \emph{labels} and \emph{cost labels}.
418The purpose of \emph{cost labels} will be explained in Subsection~\ref{subsect.computation.cost.traces}.
420Introducing pseudoinstructions had the effect of simplifying a C compiler---another component of the CerCo project---that was being implemented in parallel with our implementation.
421To see why, consider the fact that the MCS-51's instruction set has numerous instructions for unconditional and conditional jumps to memory locations.
422For instance, the instructions \texttt{AJMP}, \texttt{JMP} and \texttt{LJMP} all perform unconditional jumps.
423However, these instructions differ in how large the maximum size of the offset of the jump to be performed can be.
424Further, all jump instructions require a concrete memory address---to jump to---to be specified.
425Compilers that support separate compilation cannot directly compute these offsets and select the appropriate jump instructions.
426These operations are also burdensome for compilers that do not do separate compilation and are handled by assemblers.
427We followed suit.
429While introducing pseudoinstructions, we also introduced labels for locations to jump to, and for global data.
430To specify global data via labels, we introduced a preamble before the program where labels and the size of reserved space for data is stored.
431A pseudoinstruction \texttt{Mov} moves (16-bit) data stored at a label into the MCS-51's 16-bit register, \texttt{DPTR}.
432(This register is used for indirect addressing of data stored in external memory.)
434The pseudoinstructions and labels induce an assembly language similar to that of SDCC's.
435All pseudoinstructions and labels are `assembled away' prior to program execution.
436Jumps are computed in two stages.
437A map associating memory addresses to labels is built, before replacing pseudojumps with concrete jumps to the correct address.
438The algorithm currently implemented does not try to minimize object code size by picking the shortest possible jump instruction.
439A better algorithm is left for future work.
442% SECTION                                                                      %
444\subsection{Anatomy of the (Matita) emulator}
447The Matita emulator's internal state is a record:
449record Status: Type[0] := {
450  code_memory: BitVectorTrie Byte 16;
451  low_internal_ram: BitVectorTrie Byte 7;
452  high_internal_ram: BitVectorTrie Byte 7;
453  external_ram: BitVectorTrie Byte 16;
454  program_counter: Word;
455  special_function_registers_8051: Vector Byte 19;
456  ... }.
458This record encapsulates the current memory contents, the program counter, the state of the current SFRs, and so on.
460Here the MCS-51's memory model is implemented using four disjoint memory spaces, plus SFRs.
461From the programmer's point of view, what \emph{really} matters are the addressing modes that are in a many-to-many relationship with the spaces.
462\texttt{DIRECT} addressing can be used to address either lower IRAM (if the first bit is 0) or the SFRs (if the first bit is 1), for instance.
463That's why DIRECT uses 8-bit addresses but pointers to lower IRAM only use 7 bits.
464The complexity of the memory model is captured in a pair of functions, \texttt{get\_arg\_XX} and \texttt{set\_arg\_XX}, that `get' and `set' data of size \texttt{XX} from memory.
466%Overlapping, and checking which addressing modes can be used to address particular memory spaces, is handled through numerous \texttt{get\_arg\_XX} and \texttt{set\_arg\_XX} (for 1, 8 and 16 bits) functions.
468Both the Matita and O'Caml emulators follow the classic `fetch-decode-execute' model of processor operation.
469The next instruction to be processed, indexed by the program counter, is fetched from code memory with \texttt{fetch}.
470An updated program counter, along with its concrete cost in processor cycles, is also returned.
471These costs are taken from a Siemens Semiconductor Group data sheet for the MCS-51~\cite{siemens:2011}, and will likely vary between particular implementations.
473definition fetch: BitVectorTrie Byte 16 $\rightarrow$ Word $\rightarrow$ instruction $\times$ Word $\times$ nat
475Instruction are assembled to bit encodings by \texttt{assembly1}:
477definition assembly1: instruction $\rightarrow$ list Byte
479An assembly program---comprising a preamble containing global data and a list of pseudoinstructions---is assembled using \texttt{assembly}.
480Pseudoinstructions and labels are eliminated in favour of instructions from the MCS-51 instruction set.
481A map associating memory locations and cost labels (see Subsection~\ref{subsect.computation.cost.traces}) is produced.
483definition assembly: assembly_program $\rightarrow$ option (list Byte $\times$ (BitVectorTrie String 16))
485A single fetch-decode-execute cycle is performed by \texttt{execute\_1}:
487definition execute_1: Status $\rightarrow$ Status
489The \texttt{execute} functions performs a fixed number of cycles by iterating
492let rec execute (n: nat) (s: Status): Status := ...
494This differs from the O'Caml emulator, which executed a program indefinitely.
495A callback function was also accepted as an argument, which `witnessed' the execution as it happened.
496Due to Matita's termination requirement, \texttt{execute} cannot execute a program indefinitely.
497An alternative would be to produce an infinite stream of statuses representing an execution trace using Matita's co-inductive types.
500% SECTION                                                                      %
502\subsection{Instruction set unorthogonality}
505A peculiarity of the MCS-51 is its unorthogonal instruction set; \texttt{MOV} can be invoked using one of 16 combinations of addressing modes out of a total of 361, for instance.
507% Show example of pattern matching with polymorphic variants
509Such unorthogonality in the instruction set was handled with the use of polymorphic variants in O'Caml~\cite{garrigue:programming:1998}.
510For instance, we introduced types corresponding to each addressing mode:
512type direct = [ `DIRECT of byte ]
513type indirect = [ `INDIRECT of bit ]
516Which were then combined in the inductive datatype for assembly preinstructions using the union operator `$|$':
518type 'addr preinstruction =
519[ `ADD of acc * [ reg | direct | indirect | data ]
521| `MOV of (acc * [ reg| direct | indirect | data ],
522   [ reg | indirect ] * [ acc | direct | data ],
523   direct * [ acc | reg | direct | indirect | data ],
524   dptr * data16,
525   carry * bit,
526   bit * carry
527   ) union6
530Here, \texttt{union6} is a disjoint union type, defined as follows:
532type ('a,'b,'c,'d,'e,'f) union6 = [ `U1 of 'a | ... | `U6 of 'f ]
534The types \texttt{union2}, \texttt{union3} and \texttt{union6} sufficed.
536This polymorphic variant machinery worked well: it introduced a certain level of type safety (the type of \texttt{MOV} above guarantees it cannot be invoked with arguments in the \texttt{carry} and \texttt{data16} addressing modes), and also allowed us to pattern match against instructions, when necessary.
537However, this polymorphic variant machinery is \emph{not} present in Matita.
538We needed some way to produce the same effect, which Matita supported.
539We used dependent types.
541We provided an inductive data type representing all addressing modes, a type that functions will pattern match against:
543inductive addressing_mode: Type[0] :=
544  DIRECT: Byte $\rightarrow$ addressing_mode
545| INDIRECT: Bit $\rightarrow$ addressing_mode
548We also wished to express in the type of functions the \emph{impossibility} of pattern matching against certain constructors.
549In order to do this, we introduced an inductive type of addressing mode `tags'.
550The constructors of \texttt{addressing\_mode\_tag} are in one-to-one correspondence with the constructors of \texttt{addressing\_mode}:
552inductive addressing_mode_tag : Type[0] :=
553  direct: addressing_mode_tag
554| indirect: addressing_mode_tag
557The \texttt{is\_a} function checks if an \texttt{addressing\_mode} matches an \texttt{addressing\_mode\_tag}:
559definition is_a :=
560  $\lambda$d: addressing_mode_tag. $\lambda$A: addressing_mode.
561match d with
562[ direct $\Rightarrow$ match A with [ DIRECT _ $\Rightarrow$ true | _ $\Rightarrow$ false ]
563| indirect $\Rightarrow$ match A with [ INDIRECT _ $\Rightarrow$ true | _ $\Rightarrow$ false ]
566The \texttt{is\_in} function checks if an \texttt{addressing\_mode} matches a set of tags represented as a vector.
567It simply extends the \texttt{is\_a} function in the obvious manner.
569A \texttt{subaddressing\_mode} is an \emph{ad hoc} non-empty $\Sigma$-type of \texttt{addressing\_mode}s in a set of tags:
571record subaddressing_mode (n: nat) (l: Vector addressing_mode_tag (S n)): Type[0] := {
572  subaddressing_modeel :> addressing_mode;
573  subaddressing_modein: bool_to_Prop (is_in $\ldots$ l subaddressing_modeel)
576An implicit coercion~\cite{luo:coercive:1999} is provided to promote vectors of tags (denoted with $\llbracket - \rrbracket$) to the corresponding \texttt{subaddressing\_mode} so that we can use a syntax close to that of O'Caml to specify \texttt{preinstruction}s:
578inductive preinstruction (A: Type[0]): Type[0] ≝
579  ADD: $\llbracket$acc_a$\rrbracket$ $\rightarrow$ $\llbracket$register;direct;indirect;data$\rrbracket$ $\rightarrow$ preinstruction A
580| ADDC: $\llbracket$acc_a$\rrbracket$ $\rightarrow$ $\llbracket$register;direct;indirect;data$\rrbracket$ $\rightarrow$ preinstruction A
583The constructor \texttt{ADD} expects two parameters, the first being the accumulator A (\texttt{acc\_a}), the second being a register, direct, indirect or data addressing mode.
585% One of these coercions opens up a proof obligation which needs discussing
586% Have lemmas proving that if an element is a member of a sub, then it is a member of a superlist, and so on
587Finally, type coercions from \texttt{addressing\_mode} to \texttt{subaddressing\_mode} and from \texttt{Vector addressing\_mode\_tag} to \texttt{Type$\lbrack0\rbrack$}, are required.
588The first opens a proof obligation wherein we must prove that the provided value is in the admissible set, simulating PVS subset types~\cite{shankar:principles:1999}.
589%PVS introduced subset types, and these later featured in Coq as part of Russell~\cite{sozeau:subset:2006}.
590%All coercions in Matita can open proof obligations.
592Proof obligations require us to state and prove a few auxilliary lemmas related to the transitivity of subtyping.
593For instance, an \texttt{addressing\_mode} that belongs to an allowed set also belongs to any one of its supersets.
594At the moment, Matita's automation exploits these lemmas to completely solve all the proof obligations opened in the formalisation.
595The \texttt{execute\_1} function, for instance, opens over 200 proof obligations during type checking.
597The machinery just described allows us to restrict the set of \texttt{addressing\_mode}s expected by a function and use this information during pattern matching.
598This allows us to skip impossible cases.
599For instance, consider \texttt{set\_arg\_16}, which expects only a \texttt{DPTR}:
601definition set_arg_16: Status $\rightarrow$ Word $\rightarrow$ $\llbracket$dptr$\rrbracket$ $\rightarrow$ Status := $~\lambda$s, v, a.
602match a return $\lambda$x. bool_to_Prop (is_in ? $\llbracket$dptr$\rrbracket$ x) $\rightarrow$ ? with
603  [ DPTR $\Rightarrow$ $\lambda$_: True.
604    let $\langle$bu, bl$\rangle$ := split $\ldots$ eight eight v in
605    let status := set_8051_sfr s SFR_DPH bu in
606    let status := set_8051_sfr status SFR_DPL bl in
607      status
608  | _ $\Rightarrow$ $\lambda$_: False. $\bot$
609  ] $~$(subaddressing_modein $\ldots$ a).
611We give a proof (the expression \texttt{(subaddressing\_modein} $\ldots$ \texttt{a)}) that the argument $a$ is in the set $\llbracket$ \texttt{dptr} $\rrbracket$ to the \texttt{match} expression.
612In every case but \texttt{DPTR}, the proof is a proof of \texttt{False}, and the system opens a proof obligation $\bot$ that can be discarded using \emph{ex falso}.
613Attempting to match against a disallowed addressing mode (replacing \texttt{False} with \texttt{True} in the branch) produces a type error.
615We tried other dependently and non-dependently typed solutions before settling on this approach.
616As we need a large number of different combinations of addressing modes to describe the instruction set, it is infeasible to declare a datatype for each one of these combinations.
617The current solution is closest to the corresponding O'Caml code, to the point that the translation from O'Caml to Matita is almost syntactical.
618% We would like to investigate the possibility of changing the code extraction procedure of Matita so that it recognises this programming pattern and outputs O'Caml code using polymorphic variants.
620% Talk about extraction to O'Caml code, which hopefully will allow us to extract back to using polymorphic variants, or when extracting vectors we could extract using phantom types
621% Discuss alternative approaches, i.e. Sigma types to piece together smaller types into larger ones, as opposed to using a predicate to `cut out' pieces of a larger type, which is what we did
624% SECTION                                                                      %
626\subsection{I/O and timers}
629% `Real clock' for I/O and timers
630The O'Caml emulator has code for handling timers, asynchronous I/O and interrupts (these are not in the Matita emulator as they are not relevant to CerCo).
631All three of these features interact with each other in subtle ways.
632Interrupts can `fire' when an input is detected on the processor's UART port, and, in certain modes, timers reset when a high signal is detected on one of the MCS-51's communication pins.
634To accurately model timers and I/O, we add an unbounded integral field \texttt{clock} to the central \texttt{status} record.
635This field is only logical, since it does not represent any quantity stored in the physical processor, and is used to keep track of the current `processor time'.
636Before every execution step, \texttt{clock} is incremented by the number of processor cycles that the instruction just fetched will take to execute.
637The emulator executes the instruction then the code implementing timers and I/O (it isn't specified by the data sheets if I/O is handled at the beginning or the end of each cycle.)
638To model I/O, we store in \texttt{status} a \emph{continuation} which is a description of the behaviour of the environment:
640type line =
641[ `P1 of byte | `P3 of byte
642| `SerialBuff of [ `Eight of byte | `Nine of BitVectors.bit * byte ]  ]
644type continuation =
645[`In of time * line * epsilon * continuation] option *
646[`Out of (time -> line -> time * continuation)]
648The second projection of the continuation $k$ describes how the environment will react to an output event performed in the future by the processor.
649Suppose $\pi_2(k)(\tau,o) = \langle \tau',k' \rangle$.
650If the emulator at time $\tau$ starts an asynchronous output $o$ either on the P1 or P3 output lines, or on the UART, then the environment will receive the output at time $\tau'$.
651Moreover \texttt{status} is immediately updated with the continuation $k'$.
653Further, if $\pi_1(k) = \mathtt{Some}~\langle \tau',i,\epsilon,k'\rangle$, then at time $\tau'$ the environment will send the asynchronous input $i$ to the emulator and \texttt{status} is updated with the continuation $k'$.
654This input is visible to the emulator only at time $\tau' + \epsilon$.
656The time required to perform an I/O operation is partially specified in the data sheets of the UART module.
657This computation is complex so we prefer to abstract over it.
658We leave the computation of the delay time to the environment.
660We use only the P1 and P3 lines despite the MCS-51 having~4 output lines, P0--P3.
661This is because P0 and P2 become inoperable if XRAM is present (we assume it is).
663The UART port can work in several modes, depending on the how the SFRs are set.
664In an asyncrhonous mode, the UART transmits 8 bits at a time, using a ninth line for synchronisation.
665In a synchronous mode the ninth line is used to transmit an additional bit.
666All UART modes are formalised.
669% SECTION                                                                      %
671\subsection{Computation of cost traces}
674As mentioned in Subsection~\ref{subsect.labels.pseudoinstructions} we introduced a notion of \emph{cost label}.
675Cost labels are inserted by the prototype C compiler at specific locations in the object code.
677Cost labels are used to calculate a precise costing for a program by marking the start of basic blocks.
678During the assembly phase, where labels and pseudoinstructions are eliminated, a map is generated associating cost labels with memory locations.
679This map is later used in a separate analysis which computes the cost of a program by traversing through a program, fetching one instruction at a time, and computing the cost of blocks.
680When targetting more complex processors, this simple analysis will need to be replaced by a more sophisticated WCET analysis.
681These block costings are stored in another map, and will later be passed back to the prototype compiler.
684% SECTION                                                                      %
692%08: mov 81 #07
694% Processor status:                               
696%   ACC: 0   B: 0   PSW: 0
697%    with flags set as:
698%     CY: false    AC: false   FO: false   RS1: false
699%     RS0: false   OV: false   UD: false   P: false
700%   SP: 7   IP: 0   PC: 8   DPL: 0   DPH: 0   SCON: 0
701%   SBUF: 0   TMOD: 0   TCON: 0
702%   Registers:                                   
703%    R0: 0   R1: 0   R2: 0   R3: 0
704%    R4: 0   R5: 0   R6: 0   R7: 0
707%\caption{An example snippet from an emulator execution trace}
711We attempted to ensure that what we have formalised is an accurate model of the MCS-51 microprocessor.
713We made use of multiple data sheets, each from a different manufacturer.
714This helped us triangulate errors in the specification of the processor's instruction set, and its behaviour, for instance, in a data sheet from Philips Semiconductor.
716The O'Caml emulator was especially useful for validation purposes.
717We wrote a module for parsing and loading Intel HEX format files.
718Intel HEX is a standard format that all compilers targetting the MCS-51, and similar processors, produce.
719It is essentially a snapshot of the processor's code memory in compressed form.
720Using this we were able to compile C programs with SDCC and load the resulting program directly into the emulator's code memory, ready for execution.
721Further, we can produce a HEX file from the emulator's code memory for loading into third party tools.
722After each step of execution, we can print out both the instruction that had been executed and a snapshot of the processor's state, including all flags and register contents.
723These traces were useful in spotting anything that was `obviously' wrong with the execution of the program.
725We further used MCU 8051 IDE as a reference, which allows a user to step through an assembly program one instruction at a time.
726With these execution traces, we could step through a compiled program in MCU 8051 IDE and compare the resulting execution trace with the trace produced by our emulator.
728We partially validated the assembler by proving in Matita that on all defined opcodes the \texttt{assembly\_1} and \texttt{fetch} functions are inverse.
730The Matita formalisation was largely copied from the O'Caml source code apart from the changes already mentioned.
731As the Matita emulator is executable we could perform further validation by comparing the trace of a program's execution in the Matita and O'Caml emulators.
734% SECTION                                                                      %
736\section{Related work}
738A large body of literature on the formalisation of microprocessors exists.
739The majority of it deals with proving correctness of implementations of microprocessors at the microcode or gate level, with many considering `cycle accurate' models.
740We are interested in providing a precise specification of the behaviour of the microprocessor in order to prove the correctness of a compiler which will target the processor.
741In particular, we are interested in intentional properties of the processor; precise timings of instruction execution in clock cycles.
742Moreover, in addition to formalising the interface of an MCS-51 processor, we have also built a complete MCS-51 ecosystem: UART, I/O lines, and hardware timers, complete with an assembler.
744Work closely related to our own can be found in~\cite{fox:trustworthy:2010}.
745Here, the authors describe the formalisation, in HOL4, of the ARMv7 instruction set architecture.
746They further point to an excellent list of references to related work in the literature.
747This formalisation also considers the machine code level, opposed to their formalisation, which only considering an abstract assembly language.
748Instruction decoding is explicitly modeled inside HOL4's logic.
749We go further in also providing an assembly language, complete with assembler, to translate instructions and pseudoinstruction into machine code.
751Further, in~\cite{fox:trustworthy:2010} the authors validated their formalisation by using development boards and random testing.
752We currently rely on non-exhaustive testing against a third party emulator.
753We recognise the importance of this exhaustive testing, but currently leave it for future work.
755Executability is another key difference between our work and that of~\cite{fox:trustworthy:2010}.
756Our formalisation is executable: applying the emulation function to an input state eventually reduces to an output state.
757This is because Matita is based on a logic, CIC, which internalizes conversion.
758In~\cite{fox:trustworthy:2010} the authors provide an automation layer to derive single step theorems: if the processor is in a state that satisfies some preconditions, then after execution of an instruction it will reside in a state satisfying some postconditions.
759We will not need single step theorems of this form to prove properties of the assembly code.
761Our main difficulties resided in the non-uniformity of an old 8-bit architecture, in terms of the instruction set, addressing modes and memory models.
762In contrast, the various ARM instruction sets and memory models are relatively uniform.
764Two close projects to CerCo are CompCert~\cite{leroy:formally:2009} and the CLI Stack.
765CompCert concerns the certification of a C compiler and includes a formalisation in Coq of a subset of PowerPC.
766The CLI Stack consists of the design and verification of a whole chain of artifacts including a 32-bit microprocessor, the Piton assembler and two compilers for high-level languages.
767Like CerCo, the CLI Stack compilers gave the cost of high-level instructions in processor cycles.
768However, unlike CerCo, both the CLI Stack high-level languages ($\mu$Gypsy and Nqthm Lisp) and FM9001 microprocessor were not commercial products, but designs created for the purpose of verification (see~\cite{moore:grand:2005}).
770The CompCert C compiler is extracted to O'Caml using Coq's code extraction facility.
771Many other formalised emulators/compilers have also been extracted from proof assistants using similar technology (e.g. see~\cite{blanqui:designing:2010}).
772We aim to make use of a similar code extraction facility in Matita, but only if the extracted code exhibits the same degree of type safety, provided by polymorphic variants, and human readability that the O'Caml emulator posseses.
773This is because we aim to use the emulator as a library for non-certified software written directly in O'Caml.
774How we have used Matita's dependent types to handle the instruction set (Subsection~\ref{subsect.instruction.set.unorthogonality}) could enable code extraction to make use of polymorphic variants.
775Using Coq's current code extraction algorithm we could write assembly programs that would generate runtime errors when emulated.
776We leave this for future work.
778Despite the apparent similarity between CerCo and CompCert, the two formalisations do not have much in common.
779First, CompCert provides a formalisation at the assembly level (no instruction decoding).
780This impels them to trust an unformalised assembler and linker, whereas we provide our own.
781Our formalisation is \emph{directly} executable, while the one in CompCert only provides a relation that describes execution.
782In CompCert I/O is only described as a synchronous external function call and there is no I/O at the processor level.
783Moreover an idealized abstract and uniform memory model is assumed, while we take into account the complicated overlapping memory model of the MCS-51 architecture.
784Finally, 82 instructions of the more than 200 offered by the processor are formalised in CompCert, and the assembly language is augmented with macro instructions that are turned into `real' instructions only during communication with the external assembler.
785Even from a technical level the two formalisations differ: we tried to exploit dependent types whilst CompCert largely sticks to a non-dependent fragment of Coq.
787In~\cite{atkey:coqjvm:2007} an executable specification of the Java Virtual Machine, using dependent types, is presented.
788As we do, dependent types there are used to remove spurious partiality from the model.
789They also lower the need for over-specifying the behaviour of the processor in impossible cases.
790Our use of dependent types will also help to maintain invariants when we prove the correctness of the CerCo prototype C compiler.
792Finally~\cite{sarkar:semantics:2009} provides an executable semantics for x86-CC multiprocessor machine code.
793This machine code exhibits a degree of non-uniformity similar to the MCS-51.
794Only a small subset of the instruction set is considered, and they over-approximate the possibilities of unorthogonality of the instruction set, largely dodging the problems we had to face.
796Further, it seems that the definition of the decode function is potentially error prone.
797A domain specific language of patterns is formalised in HOL4, similar to the specification language of the x86 instruction set found in manufacturer's data sheets.
798A decode function is implemented by copying lines from data sheets into the proof script, which are then partially evaluated to obtain a compiler.
799We are currently considering implementing a similar domain specific language in Matita.
802% SECTION                                                                      %
807In CerCo, we are interested in the certification of a compiler for C that induces a precise cost model on the source code.
808Our cost model assigns costs to blocks of instructions by tracing the way that blocks are compiled, and by computing exact costs on generated machine language.
809To perform this accurately, we have provided an executable semantics for the MCS-51 family of processors.
810An O'Caml and Matita formalisation was provided, and both capture the exact timings of the MCS-51 (according to a Siemen's data sheet).
811The O'Caml formalisation also considers timers and I/O.
812Adding support for I/O and timers in Matita is on-going work that will not present any problem, and was delayed only because the addition is not immediately useful for the formalisation of the CerCo compiler.
814The formalisation is done at machine level and not at assembly level; we also formalise fetching and decoding.
815We separately provide an assembly language, enhanched with labels and pseudoinstructions, and an assembler from this language to machine code.
816This assembly language is similar to those found in `industrial strength' compilers, such as SDCC.
817We introduce cost labels in the machine language to relate the data flow of the assembly program to that of the C source language, in order to associate costs to the C program.
818For the O'Caml version, we provide a parser and pretty printer from code memory to Intel HEX.
819Hence we can perform testing on programs compiled using any free or commercial compiler.
821Our main difficulty in formalising the MCS-51 was the unorthogonality of its memory model and instruction set.
822These problems are handled in O'Caml by using language features like polymorphic variants and phantom types, simulating Generalized Abstract Data Types~\cite{xi:guarded:2003}.
823Importantly, we searched for a manner of using dependent types to recover the same flexibility, reduce spurious partiality, and grant invariants that will be later useful in other formalisations in CerCo.
825The formalisation has been partially verified by computing execution traces on selected programs and comparing them with an existing emulator.
826All instructions have been tested at least once, but we have not yet pushed testing further, for example with random testing or by using development boards.
827I/O in particular has not been tested yet, and it is currently unclear how to provide exhaustive testing in the presence of I/O.
828Finally, we are aware of having over-specified the processor in several places, by fixing a behaviour hopefully consistent with the real machine, where manufacturer data sheets are ambiguous or under-specified.
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