source: Deliverables/D4.1/ITP-Paper/itp-2011.tex @ 568

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[543]52\author{Dominic P. Mulligan\thanks{The project CerCo acknowledges the financial support of the Future and
53Emerging Technologies (FET) programme within the Seventh Framework
54Programme for Research of the European Commission, under FET-Open grant
55number: 243881} \and Claudio Sacerdoti Coen$^\star$}
[527]56\authorrunning{D. P. Mulligan and C. Sacerdoti Coen}
[501]57\title{An executable formalisation of the MCS-51 microprocessor in Matita}
58\titlerunning{An executable formalisation of the MCS-51}
[544]59\institute{Dipartimento di Scienze dell'Informazione, Universit\`a di Bologna}
[495]68We summarise our formalisation of an emulator for the MCS-51 microprocessor in the Matita proof assistant.
69The MCS-51 is a widely used 8-bit microprocessor, especially popular in embedded devices.
71We proceeded in two stages, first implementing in O'Caml a prototype emulator, where bugs could be `ironed out' quickly.
72We then ported our O'Caml emulator to Matita's internal language.
73Though mostly straight-forward, this porting presented multiple problems.
74Of particular interest is how we handle the extreme non-orthoganality of the MSC-51's instruction set.
75In O'Caml, this was handled through heavy use of polymorphic variants.
[501]76In Matita, we achieve the same effect through a non-standard use of dependent types.
78Both the O'Caml and Matita emulators are `executable'.
79Assembly programs may be animated within Matita, producing a trace of instructions executed.
[568]80The formalisation is a major component of the ongoing EU-funded CerCo project.
84% SECTION                                                                      %
[512]89Formal methods are designed to increase our confidence in the design and implementation of software (and hardware).
[551]90Ideally, we would like all software to come equipped with a formal specification, along with a proof of correctness that the software meets this specification.
91Today the majority of programs are written in high level languages and then compiled into low level ones.
[512]92Specifications are therefore also given at a high level and correctness can be proved by reasoning automatically or interactively on the program's source code.
93The code that is actually run, however, is not the high level source code that we reason on, but the object code that is generated by the compiler.
[565]94A few questions now arise:
[509]97What properties are preserved during compilation?
[509]99What properties are affected by the compilation strategy?
[509]101To what extent can you trust your compiler in preserving those properties?
[555]103These questions, and others like them, motivate a current `hot topic' in computer science research: \emph{compiler verification} (for instance~\cite{leroy:formal:2009,chlipala:verified:2010}, and many others).
[565]104So far, the field has only been focused on the first and last questions.
105Much attention has been placed on verifying compiler correctness with respect to extensional properties of programs, which are easily preserved during compilation; it is sufficient to completely preserve the denotational semantics of the input program.
[565]107If we consider intensional properties of programs---space, time, and so forth---the situation is more complex.
108To express these properties, and reason about them, we must adopt a cost model that assigns a cost to single, or blocks, of instructions.
109A compositional cost model---assigning the same cost to all occurrences of one instruction---would be ideal.
110However, compiler optimisations are inherently non-compositional: each occurrence of a high level instruction may be compiled in a different way depending on its context.
[513]111Therefore both the cost model and intensional specifications are affected by the compilation process.
[565]113In the CerCo project (`Certified Complexity')~\cite{cerco:2011} we approach the problem of reasoning about intensional properties of programs as follows.
114We are currently developing a compiler that induces a cost model on high level source code.
115Costs are assigned to each block of high level instructions by considering the costs of the corresponding blocks of compiled code.
116The cost model is therefore inherently non-compositional, but has the potential to be extremely \emph{precise}, capturing a program's \emph{realistic} cost.
117That is, the compilation process is taken into account, not ignored.
[514]118A prototype compiler, where no approximation of the cost is provided, has been developed.
[565]119(The technical details of the cost model is explained in~\cite{amadio:certifying:2010}.)
[565]121We believe that our approach is applicable to certifying real time programs.
122A user can certify that `deadlines' are met whilst wringing as many clock cycles from the processor---using a cost model that does not over-estimate---as possible.
[565]124We also see our approach as being relevant to the compiler verification (and construction) itself.
125An optimisation specified only extensionally is only half specified; though the optimisation may preserve the denotational semantics of a program, there is no guarantee that any intensional properties of the program will be improved.
[515]126Another potential application is toward completeness and correctness of the compilation process in the presence of space constraints.
[565]127A compiler could potentially reject a source program targetting an embedded system when the size of the compiled code exceeds the available ROM size.
128Preservation of a program's semantics may only be required for those programs that do not exhaust the stack or heap.
[515]129Hence the statement of completeness of the compiler must take in to account a realistic cost model.
[565]131With the CerCo methodology, we assume we can assign to the object code exact and realistic costs for sequential blocks of instructions.
132This is possible with modern processors (see~\cite{bate:wcet:2011,yan:wcet:2008} for instance) but difficult, as the execution of a program has an influence on the speed of processing.
133Caching, memory effects, and other advanced features such as branch prediction all have a profound effect on execution speeds.
[515]134For this reason CerCo decided to focus on 8-bit microprocessors.
[565]135These are still widely used in embedded systems, with the advantage of an easily predictable cost model due to their relative paucity of features.
[568]137We have fully formalised an executable formal semantics of a family of 8-bit Freescale Microprocessors~\cite{oliboni:matita:2008}, and provided a similar executable formal semantics for the MCS-51 microprocessor.
[565]138The latter is what we describe in this paper.
139The focus of the formalisation has been on capturing the intensional behaviour of the processor.
[515]140However, the design of the MCS-51 itself has caused problems in our formalisation.
141For example, the MCS-51 has a highly unorthogonal instruction set.
[565]142To cope with this unorthogonality, and to produce an executable specification, we have Matita's dependent types.
[493]144\subsection{The 8051/8052}
[568]147The MCS-51 is an 8-bit microprocessor introduced by Intel in the late 1970s.
[493]148Commonly called the 8051, in the three decades since its introduction the processor has become a highly popular target for embedded systems engineers.
[515]149Further, the processor, its immediate successor the 8052, and many derivatives are still manufactured \emph{en masse} by a host of semiconductor suppliers.
151The 8051 is a well documented processor, and has the additional support of numerous open source and commercial tools, such as compilers for high-level languages and emulators.
[550]152For instance, the open source Small Device C Compiler (SDCC) recognises a dialect of C~\cite{sdcc:2010}, and other compilers targeting the 8051 for BASIC, Forth and Modula-2 are also extant.
153An open source emulator for the processor, MCU-8051 IDE, is also available~\cite{mcu8051ide:2010}.
[515]154Both MCU-8051 IDE and SDCC were used profitably in the implementation of our formalisation.
160\put(12,410){\makebox(80,0)[b]{Internal (256B)}}
164\put(12,400){\makebox(0,0)[r]{0h}}  \put(14,400){\makebox(0,0)[l]{Register bank 0}}
166\put(12,386){\makebox(0,0)[r]{8h}}  \put(14,386){\makebox(0,0)[l]{Register bank 1}}
168\put(12,372){\makebox(0,0)[r]{10h}}  \put(14,372){\makebox(0,0)[l]{Register bank 2}}
170\put(12,358){\makebox(0,0)[r]{18h}} \put(14,358){\makebox(0,0)[l]{Register bank 3}}
172\put(12,344){\makebox(0,0)[r]{20h}} \put(14,344){\makebox(0,0)[l]{Bit addressable}}
175  \put(14,309){\makebox(0,0)[l]{\quad \vdots}}
178  \put(14,263){\makebox(0,0)[l]{\quad \vdots}}
195% bit access to sfrs?
203\put(164,410){\makebox(80,0)[b]{External (64kB)}}
209\put(164,324){\makebox(80,0){Paged access}}
210  \put(164,310){\makebox(80,0){Direct/indirect}}
212  \put(164,228){\makebox(80,0){\vdots}}
213  \put(164,210){\makebox(80,0){Direct/indirect}}
215\put(264,410){\makebox(80,0)[b]{Code (64kB)}}
220  \put(264,228){\makebox(80,0){\vdots}}
221  \put(264,324){\makebox(80,0){Direct}}
222  \put(264,310){\makebox(80,0){PC relative}}
224\caption{The 8051 memory model}
228The 8051 has a relatively straightforward architecture, unencumbered by advanced features of modern processors, making it an ideal target for formalisation.
[559]229A high-level overview of the processor's memory layout, along with the ways in which different memory spaces may be addressed, is provided in Figure~\ref{fig.memory.layout}.
231Processor RAM is divided into numerous segments, with the most prominent division being between internal and (optional) external memory.
[552]232Internal memory, commonly provided on the die itself with fast access, is composed of 256 bytes, but, in direct addressing mode, half of them are overloaded with 128 bytes of memory mapped Special Function Registers (SFRs) which control the operation of the processor.
[516]233Internal RAM (IRAM) is further divided into eight general purpose bit-addressable registers (R0--R7).
[493]234These sit in the first eight bytes of IRAM, though can be programmatically `shifted up' as needed.
[516]235Bit memory, followed by a small amount of stack space, resides in the memory space immediately after the register banks.
[493]236What remains of the IRAM may be treated as general purpose memory.
[559]237A schematic view of IRAM layout is also provided in Figure~\ref{fig.memory.layout}.
[516]239External RAM (XRAM), limited to a maximum size of 64 kilobytes, is optional, and may be provided on or off chip, depending on the manufacturer.
[568]240XRAM is accessed using a dedicated instruction, and requires 16 bits to address fully.
[493]241External code memory (XCODE) is often stored in the form of an EPROM, and limited to 64 kilobytes in size.
242However, depending on the particular manufacturer and processor model, a dedicated on-die read-only memory area for program code (ICODE) may also be supplied.
244Memory may be addressed in numerous ways: immediate, direct, indirect, external direct and code indirect.
245As the latter two addressing modes hint, there are some restrictions enforced by the 8051 and its derivatives on which addressing modes may be used with specific types of memory.
[568]246For instance, the 128 bytes of extra internal RAM that the 8052 features cannot be addressed using indirect addressing; rather, external (in)direct addressing must be used. Moreover, some memory segments are addressed using 8-bit pointers while others require 16-bits.
[568]248The 8051 possesses an 8-bit Arithmetic and Logic Unit (ALU), with a variety of instructions for performing arithmetic and logical operations on bits and integers.
249Two 8-bit general purpose accumulators, A and B, are provided.
251Communication with the device is facilitated by an onboard UART serial port, and associated serial controller, which can operate in numerous modes.
[568]252Serial baud rate is determined by one of two 16-bit timers included with the 8051, which can be set to multiple modes of operation.
253(The 8052 provides an additional 16-bit timer.)
[493]254As an additional method of communication, the 8051 also provides a four byte bit-addressable input-output port.
256The programmer may take advantage of the interrupt mechanism that the processor provides.
257This is especially useful when dealing with input or output involving the serial device, as an interrupt can be set when a whole character is sent or received via the serial port.
259Interrupts immediately halt the flow of execution of the processor, and cause the program counter to jump to a fixed address, where the requisite interrupt handler is stored.
260However, interrupts may be set to one of two priorities: low and high.
261The interrupt handler of an interrupt with high priority is executed ahead of the interrupt handler of an interrupt of lower priority, interrupting a currently executing handler of lower priority, if necessary.
263The 8051 has interrupts disabled by default.
264The programmer is free to handle serial input and output manually, by poking serial flags in the SFRs.
[565]265`Exceptional circumstances' that would otherwise trigger an interrupt on more modern processors, (e.g. division by zero) are also signalled by setting flags.
271%\caption{Schematic view of 8051 IRAM layout}
276% SECTION                                                                      %
278\subsection{Overview of paper}
[538]281In Section~\ref{} we discuss design issues in the development of the formalisation.
282In Section~\ref{sect.validation} we discuss how we validated the design and implementation of our emulator to ensure that what we formalised was an accurate model of an MCS-51 series microprocessor.
283In Section~\ref{} we describe previous work, with an eye toward describing its relation with the work described herein.
[565]284In Section~\ref{sect.conclusions} we conclude.
287% SECTION                                                                      %
[527]289\section{Design issues in the formalisation}
[540]292From hereonin, we typeset O'Caml source with \texttt{\color{blue}{blue}} and Matita source with \texttt{\color{red}{red}} to distinguish the two syntaxes.
293Matita's syntax is largely straightforward to those familiar with Coq or O'Caml.
[554]294The only subtlety is the use of `\texttt{?}' in an argument position denoting an argument that should be inferred automatically.
[557]296A full account of the formalisation can be found in~\cite{cerco-report:2011}.
[527]298\subsection{Development strategy}
[538]301Our implementation progressed in two stages.
[565]302We began with an emulator written in O'Caml to `iron out' any bugs in our design and implementation.
303O'Caml's ability to perform file I/O also eased debugging and validation.
[568]304Once we were happy with the design of the O'Caml emulator, we moved Matita.
[506]306Matita's syntax is lexically similar to O'Caml's.
[565]307This eased the translation, as code was merely copied with minor modifications.
308However, several major issues had to be addresses when moving from to Matita.
[506]309These are now discussed.
312% SECTION                                                                      %
[554]314\subsection{Representation of bytes, words, etc.}
321type 'a vect = bit list
[554]322type nibble = [`Sixteen] vect
[527]323type byte = [`Eight] vect
[554]324$\color{blue}{\mathtt{let}}$ split_word w = split_nth 4 w
325$\color{blue}{\mathtt{let}}$ split_byte b = split_nth 2 b
[532]332type 'a vect
333type word = [`Sixteen] vect
334type byte = [`Eight] vect
[554]335val split_word: word -> byte * word
336val split_byte: byte -> nibble * nibble
339\caption{Sample of O'Caml implementation and interface for bitvectors module}
[568]343The formalization of MCS-51 must deal with bytes (8-bits), words (16-bits) but also with more exoteric quantities (7-bits, 3-bits, 9-bits).
[555]344To avoid size mismatch bugs difficult to spot, we represent all of these quantities using bitvectors, i.e. fixed length vectors of booleans.
[557]345In our O'Caml emulator, we `faked' bitvectors using phantom types~\cite{leijen:domain:1999} implemented with polymorphic variants~\cite{garrigue:programming:1998}, as in Figure~\ref{fig.ocaml.implementation.bitvectors}.
[555]346From within the bitvector module (left column) bitvectors are just lists of bits and no guarantee is provided on sizes.
347However, the module's interface (right column) enforces the size invariants in the rest of the code.
[554]349In Matita, we are able to use the full power of dependent types to always work with vectors of a known size:
351inductive Vector (A: Type[0]): nat → Type[0] ≝
352  VEmpty: Vector A O
353| VCons: ∀n: nat. A → Vector A n → Vector A (S n).
355We define \texttt{BitVector} as a specialization of \texttt{Vector} to \texttt{bool}.
[554]356We may use Matita's type system to provide precise typing for functions that are
357polymorphic in the size without having to duplicate the code as we did in O'Caml:
359let rec split (A: Type[0]) (m,n: nat) on m:
360   Vector A (plus m n) $\rightarrow$ (Vector A m) $\times$ (Vector A n) := ...
364% SECTION                                                                      %
[511]366\subsection{Representing memory}
[565]369The MCS-51 has numerous disjoint memory spaces addressed by pointers of different sizes.
370In our prototype implementation, we use a map data structure (from O'Caml's standard library) for each space.
371Matita's standard library is small, and does not contain a generic map data structure.
372We had the opportunity of crafting a dependently typed special-purpose data structure for the job to enforce the correspondence between the size of pointer and the size of the memory space.
373We assumed that large swathes of memory would often be uninitialized.
[565]375We picked a modified form of trie of fixed height $h$.
376Paths are represented by bitvectors (already used in our implementation for addresses and registers) of length $h$:
378inductive BitVectorTrie (A: Type[0]): nat $\rightarrow$ Type[0] ≝
379  Leaf: A $\rightarrow$ BitVectorTrie A 0
380| Node: ∀n. BitVectorTrie A n $\rightarrow$ BitVectorTrie A n $\rightarrow$ BitVectorTrie A (S n)
381| Stub: ∀n. BitVectorTrie A n.
[565]383\texttt{Stub} is a constructor that can appear at any point in a trie.
384It represents `uninitialized data'.
[516]385Performing a lookup in memory is now straight-forward.
[565]386We traverse a path, and if we encounter \texttt{Stub}, we return a default value\footnote{All manufacturer data sheets that we consulted were silent on the subject of what should be returned if we attempt to access uninitialized memory.  We defaulted to simply returning zero, though our \texttt{lookup} function is parametric in this choice.  We do not believe that this is an outrageous decision, as SDCC for instance generates code which first `zeroes out' all memory in a preamble before executing the program proper.  This is in line with the C standard, which guarantees that all global variables will be zero initialized piecewise.}.
389% SECTION                                                                      %
[519]391\subsection{Labels and pseudoinstructions}
[523]394Aside from implementing the core MCS-51 instruction set, we also provided \emph{pseudoinstructions}, \emph{labels} and \emph{cost labels}.
395The purpose of \emph{cost labels} will be explained in Subsection~\ref{subsect.computation.cost.traces}.
[522]397Introducing pseudoinstructions had the effect of simplifying a C compiler---another component of the CerCo project---that was being implemented in parallel with our implementation.
[565]398To see why, consider the fact that the MCS-51's instruction set has numerous instructions for unconditional and conditional jumps to memory locations.
[519]399For instance, the instructions \texttt{AJMP}, \texttt{JMP} and \texttt{LJMP} all perform unconditional jumps.
400However, these instructions differ in how large the maximum size of the offset of the jump to be performed can be.
[522]401Further, all jump instructions require a concrete memory address---to jump to---to be specified.
[565]402Compilers that support separate compilation cannot directly compute these offsets and select the appropriate jump instructions.
403These operations are also burdensome for compilers that do not do separate compilation and are handled by the assemblers, as we decided to do.
[565]405While introducing pseudoinstructions, we also introduced labels for locations to jump to, and for global data.
406To specify global data via labels, we introduced a preamble before the program where labels and the size of reserved space for data is associated.
[522]407A pseudoinstruction \texttt{Mov} moves (16-bit) data stored at a label into the (16-bit) register \texttt{DPTR}.
[565]409Our pseudoinstructions and labels induce an assembly language similar to that of SDCC.
410All pseudoinstructions and labels are `assembled away' prior to program execution.
411Jumps are computed in two stages.
412A map associating memory addresses to labels is built, before removing pseudojumps with concrete jumps to the correct address.
413The algorithm currently implemented does not try to minimize the object code size by always picking the shortest possible jump instruction.
414A better algorithm is currently left for future work.
417% SECTION                                                                      %
[524]419\subsection{Anatomy of the (Matita) emulator}
[517]422The internal state of our Matita emulator is represented as a record:
[561]424record Status: Type[0] ≝ {
[517]425  code_memory: BitVectorTrie Byte 16;
426  low_internal_ram: BitVectorTrie Byte 7;
427  high_internal_ram: BitVectorTrie Byte 7;
428  external_ram: BitVectorTrie Byte 16;
429  program_counter: Word;
430  special_function_registers_8051: Vector Byte 19;
431  special_function_registers_8052: Vector Byte 5;
[561]432  ...  }.
434This record neatly encapsulates the current memory contents, the program counter, the state of the current SFRs, and so on.
[565]436Here the MCS-51 memory model is implemented using four disjoint memory spaces plus the SFRs.
437From the programmer's point of view, what matters are addressing modes that are in a many-to-many relation with the spaces.
438\texttt{DIRECT} addressing can be used to address either low internal RAM (if the first bit is 0) or the SFRs (if the first bit is 1), for instance.
439That's why DIRECT uses 8-bit addresses but pointers to the low internal RAM only use 7 bits.
440The complexity of the memory model is captured in the \texttt{get\_arg\_XX} and \texttt{set\_arg\_XX} functions that get and set data of size \texttt{XX} from memory, considering all addressing modes
[561]442%Overlapping, and checking which addressing modes can be used to address particular memory spaces, is handled through numerous \texttt{get\_arg\_XX} and \texttt{set\_arg\_XX} (for 1, 8 and 16 bits) functions.
[524]444Both the Matita and O'Caml emulators follows the classic `fetch-decode-execute' model of processor operation.
[532]445The next instruction to be processed, indexed by the program counter, is fetched from code memory with \texttt{fetch}.
[524]446An updated program counter, along with the concrete cost, in processor cycles for executing this instruction, is also returned.
[555]447These costs are taken from a Siemens Semiconductor Group data sheet for the MCS-51~\cite{siemens:2011}, and will likely vary across manufacturers and particular derivatives of the processor.
[561]449definition fetch: BitVectorTrie Byte 16 $\rightarrow$ Word $\rightarrow$ instruction $\times$ Word $\times$ nat
[561]451Instruction are assembled to bit encodings by \texttt{assembly1}:
[561]453definition assembly1: instruction $\rightarrow$ list Byte
[565]455An assembly program---comprising a preamble containing global data and a list of pseudoinstructions---is assembled using \texttt{assembly}.
456Pseudoinstructions and labels are eliminated in favour of instructions from the MCS-51 instruction set.
457A map associating memory locations and cost labels (see Subsection~\ref{subsect.computation.cost.traces}) is produced.
[532]459definition assembly:
[561]460  assembly_program $\rightarrow$ option (list Byte $\times$ (BitVectorTrie String 16))
[561]462A single fetch-decode-execute cycle is performed by \texttt{execute\_1}:
[561]464definition execute_1: Status $\rightarrow$ Status
[561]466The \texttt{execute} functions performs a fixed number of cycles by iterating
469let rec execute (n: nat) (s: Status) on n: Status := ...
[565]471This differs from the O'Caml emulator, which executed a program indefinitely.
472A callback function was also accepted as an argument, which could `witness' the execution as it happened, providing a print-out of the processor state.
473Due to Matita's termination requirement, \texttt{execute} cannot execute a program indefinitely.
474An alternative would be to produce an infinite stream of statuses representing an execution trace.
475Matita supports infinite streams through co-inductive types.
478% SECTION                                                                      %
480\subsection{Instruction set unorthogonality}
[508]483A peculiarity of the MCS-51 is the non-orthogonality of its instruction set.
[568]484For instance, the \texttt{MOV} instruction, can be invoked using one of 16 combinations of addressing modes out of a possible 361.
[520]486% Show example of pattern matching with polymorphic variants
[508]488Such non-orthogonality in the instruction set was handled with the use of polymorphic variants in the O'Caml emulator.
489For instance, we introduced types corresponding to each addressing mode:
491type direct = [ `DIRECT of byte ]
492type indirect = [ `INDIRECT of bit ]
[561]495Which were then combined in our inductive datatype for assembly instructions using the union operator `$|$':
497type 'addr preinstruction =
498 [ `ADD of acc * [ reg | direct | indirect | data ]
500 | `MOV of
501    (acc * [ reg | direct | indirect | data ],
502     [ reg | indirect ] * [ acc | direct | data ],
503     direct * [ acc | reg | direct | indirect | data ],
504     dptr * data16,
505     carry * bit,
506     bit * carry
507     ) union6
510Here, \texttt{union6} is a disjoint union type, defined as follows:
512type ('a,'b,'c,'d,'e,'f) union6 = [ `U1 of 'a | ... | `U6 of 'f ]
[510]514For our purposes, the types \texttt{union2}, \texttt{union3} and \texttt{union6} sufficed.
[510]516This polymorphic variant machinery worked well: it introduced a certain level of type safety (for instance, the type of our \texttt{MOV} instruction above guarantees it cannot be invoked with arguments in the \texttt{carry} and \texttt{data16} addressing modes, respectively), and also allowed us to pattern match against instructions, when necessary.
517However, this polymorphic variant machinery is \emph{not} present in Matita.
518We needed some way to produce the same effect, which Matita supported.
519For this task, we used dependent types.
[510]521We first provided an inductive data type representing all possible addressing modes, a type that functions will pattern match against:
[510]523inductive addressing_mode: Type[0] ≝
[495]524  DIRECT: Byte $\rightarrow$ addressing_mode
525| INDIRECT: Bit $\rightarrow$ addressing_mode
[510]528We also wished to express in the type of functions the \emph{impossibility} of pattern matching against certain constructors.
529In order to do this, we introduced an inductive type of addressing mode `tags'.
530The constructors of \texttt{addressing\_mode\_tag} are in one-to-one correspondence with the constructors of \texttt{addressing\_mode}:
[510]532inductive addressing_mode_tag : Type[0] ≝
[495]533  direct: addressing_mode_tag
534| indirect: addressing_mode_tag
[561]537The \texttt{is\_a} function checks if an \texttt{addressing\_mode} matches an \texttt{addressing\_mode\_tag}:
[539]539let rec is_a (d: addressing_mode_tag) (A: addressing_mode) on d :=
[495]540  match d with
541   [ direct $\Rightarrow$ match A with [ DIRECT _ $\Rightarrow$ true | _ $\Rightarrow$ false ]
542   | indirect $\Rightarrow$ match A with [ INDIRECT _ $\Rightarrow$ true | _ $\Rightarrow$ false ]
[561]545The \texttt{is\_in} function checks if an \texttt{addressing\_mode} matches a set of tags represented as a vector. It simply extends the \texttt{is\_a} function in the obvious manner.
547Finally, a \texttt{subaddressing\_mode} is an ad-hoc non empty $\Sigma$-type of addressing
548modes constrained to be in a given set of tags:
[561]550record subaddressing_mode n (l: Vector addressing_mode_tag (S n)): Type[0] :=
551 { subaddressing_modeel :> addressing_mode;
552   subaddressing_modein: bool_to_Prop (is_in ? l subaddressing_modeel) }.
[561]554An implicit coercion is provided to promote vectors of tags (denoted with
555$\llbracket - \rrbracket$)
556to the
557corresponding \texttt{subaddressing\_mode} so that we can use a syntax
558close to the O'Caml one to specify preinstructions:
[510]560inductive preinstruction (A: Type[0]): Type[0] ≝
[495]561   ADD: $\llbracket$ acc_a $\rrbracket$ $\rightarrow$ $\llbracket$ register; direct; indirect; data $\rrbracket$ $\rightarrow$ preinstruction A
562 | ADDC: $\llbracket$ acc_a $\rrbracket$ $\rightarrow$ $\llbracket$ register; direct; indirect; data $\rrbracket$ $\rightarrow$ preinstruction A
[568]565The constructor \texttt{ADD} expects two parameters, the first being the accumulator A (\texttt{acc\_a}), the second being a register, direct, indirect or data addressing mode.
[520]567% One of these coercions opens up a proof obligation which needs discussing
568% Have lemmas proving that if an element is a member of a sub, then it is a member of a superlist, and so on
[495]569The final, missing component is a pair of type coercions from \texttt{addressing\_mode} to \texttt{subaddressing\_mode} and from \texttt{subaddressing\_mode} to \texttt{Type$\lbrack0\rbrack$}, respectively.
[565]570The first is a forgetful coercion, while the second opens a proof obligation wherein we must prove that the provided value is in the admissible set.
[568]571These coercions were first introduced by PVS to implement subset types~\cite{shankar:principles:1999}, and later in Coq as an addition~\cite{sozeau:subset:2006}.
[565]572In Matita all coercions can open proof obligations.
[561]574Proof obligations impels us to state and prove a few auxilliary lemmas related
575to transitivity of subtyping. For instance, an addressing mode that belongs
576to an allowed set also belongs to any one of its super-set. At the moment,
577Matita's automation exploits these lemmas to completely solve all the proof
578obligations opened in our formalization, comprising the 200 proof obligations
579related to the main \texttt{execute\_1} function.
581The machinery just described allows us to restrict the set of addressing
582modes expected by a function and use this information during pattern matching
583to skip impossible cases.
[495]584For instance, consider \texttt{set\_arg\_16}, which expects only a \texttt{DPTR}:
[561]586definition set_arg_16: Status $\rightarrow$ Word $\rightarrow$ $\llbracket$ dptr $\rrbracket$ $\rightarrow$ Status ≝ $~\lambda$s, v, a.
[495]587   match a return $\lambda$x. bool_to_Prop (is_in ? $\llbracket$ dptr $\rrbracket$ x) $\rightarrow$ ? with
588     [ DPTR $\Rightarrow$ $\lambda$_: True.
589       let 〈 bu, bl 〉 := split $\ldots$ eight eight v in
590       let status := set_8051_sfr s SFR_DPH bu in
591       let status := set_8051_sfr status SFR_DPL bl in
592         status
[561]593     | _ $\Rightarrow$ $\lambda$_: False. $\bot$ ] $~$(subaddressing_modein $\ldots$ a).
[565]595We give a proof (the expression \texttt{(subaddressing\_modein} $\ldots$ \texttt{a)}) that the argument $a$ is in the set $\llbracket$ \texttt{dptr} $\rrbracket$ to the match expression.
596In every case but \texttt{DPTR}, the proof is a proof of \texttt{False}, and the system opens a proof obligation $\bot$ that can be discarded using \emph{ex falso}.
597Attempting to match against a disallowed addressing mode (replacing \texttt{False} with \texttt{True} in the branch) produces a type-error.
[565]599Other dependently and non-dependently typed solutions we tried were clumsy in practice.
600As we need a large number of different combinations of addressing modes to describe the whole instruction set, it is unfeasible to declare a data type for each one of these combinations.
601The current solution is the one that best matches the corresponding O'Caml code, to the point that the translation from O'Caml to Matita is almost syntactical.
602We would like to investigate the possibility of changing the code extraction procedure of Matita to recognise this programming pattern and output O'Caml code using polymorphic variants.
[520]604% Talk about extraction to O'Caml code, which hopefully will allow us to extract back to using polymorphic variants, or when extracting vectors we could extract using phantom types
605% Discuss alternative approaches, i.e. Sigma types to piece together smaller types into larger ones, as opposed to using a predicate to `cut out' pieces of a larger type, which is what we did
608% SECTION                                                                      %
[521]610\subsection{I/O and timers}
613% `Real clock' for I/O and timers
[545]614The O'Caml emulator has code for handling timers, asynchronous I/O and interrupts (these are not yet ported to the Matita emulator).
[525]615All three of these features interact with each other in subtle ways.
[565]616Interrupts can `fire' when an input is detected on the processor's UART port, and, in certain modes, timers reset when a high signal is detected on one of the MCS-51's communication pins.
[548]618To accurately model timers and I/O, we add an unbounded integral field \texttt{clock} to the central \texttt{status} record.
619This field is only logical, since it does not represent any quantity stored in the actual processor, and is used to keep track of the current processor time.
620Before every execution step, \texttt{clock} is incremented by the number of processor cycles that the instruction just fetched will take to execute.
621The processor then executes the instruction, followed by the code implementing the timers and I/O\footnote{Though it isn't fully specified by the manufacturer's data sheets if I/O is handled at the beginning or the end of each cycle.}. In order to model I/O, we also store in the status a
[562]622\emph{continuation} which is a description of the behaviour of the environment:
624type line =
625  [ `P1 of byte | `P3 of byte
626  | `SerialBuff of [ `Eight of byte | `Nine of BitVectors.bit * byte ]]
627type continuation =
628  [`In of time * line * epsilon * continuation] option *
629  [`Out of (time -> line -> time * continuation)]
[562]631At each moment, the second projection of the continuation $k$ describes how the environment will react to an output event performed in the future by the processor. Let $\pi_2(k)(\tau,o) = \langle \tau',k' \rangle$.
[548]632If the processor at time $\tau$ starts an asynchronous output $o$ either on the P1 or P3 output lines, or on the UART, then the environment will receive the output at time $\tau'$.
[562]633Moreover the status is immediately updated with the continuation $k'$.
[548]635Further, if $\pi_1(k) = \mathtt{Some}~\langle \tau',i,\epsilon,k'\rangle$, then at time $\tau'$ the environment will send the asynchronous input $i$ to the processor and the status will be updated with the continuation $k'$.
[565]636This input is visible to the processor only at time $\tau' + \epsilon$.
[548]638The time required to perform an I/O operation is partially specified in the data sheets of the UART module.
[565]639This computation is complex so we prefer to abstract over it.
640We leave the computation of the delay time to the environment.
[548]642We use only the P1 and P3 lines despite the MCS-51 having four output lines, P0--P3.
643This is because P0 and P2 become inoperable if the processor is equipped with XRAM (which we assume it is).
[548]645The UART port can work in several modes, depending on the how the SFRs are set.
[568]646In an asyncrhonous mode, the UART transmits 8 bits at a time, using a ninth line for syncrhonization.
[548]647In a syncrhonous mode the ninth line is used to transmit an additional bit.
650% SECTION                                                                      %
652\subsection{Computation of cost traces}
[529]655As mentioned in Subsection~\ref{subsect.labels.pseudoinstructions} we introduced a notion of \emph{cost label}.
656Cost labels are inserted by the prototype C compiler in specific locations in the object code.
657Roughly, for those familiar with control flow graphs, they are inserted at the start of every basic block.
[529]659Cost labels are used to calculate a precise costing for a program by marking the location of basic blocks.
660During the assembly phase, where labels and pseudoinstructions are eliminated, a map is generated associating cost labels with memory locations.
661This map is later used in a separate analysis which computes the cost of a program by traversing through a program, fetching one instruction at a time, and computing the cost of blocks.
662These block costings are stored in another map, and will later be passed back to the prototype compiler.
665% SECTION                                                                      %
[565]670We spent considerable effort attempting to ensure that what we have formalised is an accurate model of the MCS-51 microprocessor.
[562]672First, we made use of multiple data sheets, each from a different semiconductor manufacturer.  This helped us spot errors in the specification of the processor's instruction set, and its behaviour, for instance, in a datasheet from Philips.
674The O'Caml prototype was especially useful for validation purposes.
675This is because we wrote a module for parsing and loading the Intel HEX file format.
676HEX is a standard format that all compilers targetting the MCS-51, and similar processors, produce.
677It is essentially a snapshot of the processor's code memory in compressed form.
678Using this, we were able to compile C programs with SDCC, an open source compiler, and load the resulting program directly into our emulator's code memory, ready for execution.
679Further, we are able to produce a HEX file from our emulator's code memory, for loading into third party tools.
680After each step of execution, we can print out both the instruction that had been executed, along with its arguments, and a snapshot of the processor's state, including all flags and register contents.
681For example:
68608: mov 81 #07
688 Processor status:                               
[560]690   ACC: 0   B: 0   PSW: 0
[546]691    with flags set as:
[560]692     CY: false  AC: false  FO: false  RS1: false
693     RS0: false  OV: false UD: false  P: false
694   SP: 7  IP: 0  PC: 8  DPL: 0  DPH: 0  SCON: 0
695   SBUF: 0  TMOD: 0  TCON: 0
[511]696   Registers:                                   
[560]697    R0: 0  R1: 0  R2: 0  R3: 0  R4: 0  R5: 0  R6: 0  R7: 0
702Here, the traces indicates that the instruction \texttt{mov 81 \#07} has just been executed by the processor, which is now in the state indicated.
703These traces were useful in spotting anything that was `obviously' wrong with the execution of the program.
[549]705Further, we used MCU 8051 IDE as a reference.
706Using our execution traces, we were able to step through a compiled program, one instruction at a time, in MCU 8051 IDE, and compare the resulting execution trace with the trace produced by our emulator.
708Our Matita formalisation was largely copied from the O'Caml source code, apart from changes related to addressing modes already mentioned.
709However, as the Matita emulator is executable, we could perform further validation by comparing the trace of a program's execution in the Matita emulator with the trace of the same program in the O'Caml emulator.
712% SECTION                                                                      %
[493]714\section{Related work}
[546]716There exists a large body of literature on the formalisation of microprocessors.
717The majority of it aims to prove correctness of the implementation of the microprocessor at the microcode or gate level.
[562]718 We are interested in providing a precise specification of the behaviour of the microprocessor in order to prove the correctness of a compiler which will target the processor.
[546]719In particular, we are interested in intensional properties of the processor; precise timings of instruction execution in clock cycles.
720Moreover, in addition to formalising the interface of an MCS-51 processor, we have also built a complete MCS-51 ecosystem: the UART, the I/O lines, and hardware timers, along with an assembler.
[549]722Similar work to ours can be found in~\cite{fox:trustworthy:2010}.
[546]723Here, the authors describe the formalisation, in HOL4, of the ARMv7 instruction set architecture, and point to a good list of references to related work in the literature.
724This formalisation also considers the machine code level, as opposed to only considering an abstract assembly language.
725In particular, instruction decoding is explicitly modelled inside HOL4's logic.
[562]726We go further in also providing an assembly language, complete with assembler, to translate instructions and pseudoinstruction to machine code.
[549]728Further, in~\cite{fox:trustworthy:2010} the authors validated their formalisation by using development boards and random testing.
[562]729We currently rely on non-exhaustive testing against a third party emulator.
730We leave exhaustive testing for future work.
[549]732Executability is another key difference between our work and~\cite{fox:trustworthy:2010}.
[555]733Our formalisation is executable: applying the emulation function to an input state eventually reduces to an output state that already satisfies the appropriate conditions.
734This is because Matita is based on a logic that internalizes conversion.
[549]735In~\cite{fox:trustworthy:2010} the authors provide an automation layer to derive single step theorems: if the processor is in a particular state that satisfies some preconditions, then after execution of an instruction it will reside in another state satisfying some postconditions.
[546]736We do not need single step theorems of this form.
[546]738Our main difficulties resided in the non-uniformity of an old 8-bit architecture, in terms of the instruction set, addressing modes and memory models.
739In contrast, the ARM instruction set and memory model is relatively uniform, simplifying any formalisation considerably.
[563]741Perhaps the closest project to CerCo is CompCert~\cite{leroy:formally:2009}.
742CompCert concerns the certification of a C compiler and includes a formalisation in Coq of a subset of PowerPC.
[546]743Coq and Matita essentially share the same logic.
[546]745Despite this similarity, the two formalisations do not have much in common.
[564]746First, CompCert provides a formalisation at the assembly level (no instruction decoding), and this impels them to trust an unformalised assembler and linker, whereas we provide our own. Our formalization is directly executable, while the
747one in CompCert only provides a relation that describes execution.
[546]748I/O is also not considered at all in CompCert.
749Moreover an idealized abstract and uniform memory model is assumed, while we take into account the complicated overlapping memory model of the MCS-51 architecture.
[564]750Finally, 82 instructions of the 200+ offered by the processor are formalised in CompCert, and the assembly language is augmented with macro instructions that are turned into `real' instructions only during communication with the external assembler.
[546]751Even from a technical level the two formalisations differ: while we tried to exploit dependent types as often as possible, CompCert largely sticks to the non-dependent fragment of Coq.
[549]753In~\cite{atkey:coqjvm:2007} Atkey presents an executable specification of the Java virtual machine which uses dependent types.
[546]754As we do, dependent types are used to remove spurious partiality from the model, and to lower the need for over-specifying the behaviour of the processor in impossible cases.
755Our use of dependent types will also help to maintain invariants when we prove the correctness of the CerCo prototype compiler.
[565]757Finally, Sarkar et al~\cite{sarkar:semantics:2009} provide an executable semantics for x86-CC multiprocessor machine code.
[548]758This machine code exhibits a high degree of non-uniformity similar to the MCS-51.
[565]759However, only a small subset of the instruction set is considered, and they over-approximate the possibilities of unorthogonality of the instruction set, largely dodging the problems we had to face.
[548]761Further, it seems that the definition of the decode function is potentially error prone.
762A small domain specific language of patterns is formalised in HOL4.
763This is similar to the specification language of the x86 instruction set found in manufacturer's data sheets.
764A decode function is implemented by copying lines from data sheets into the proof script.
[548]766We are currently considering implementing a similar domain specific language in Matita.
767However, we would prefer to certify in Matita the compiler for this language.
768Data sheets could then be compiled down to the efficient code that we currently provide, instead of inefficiently interpreting the data sheets every time an instruction is executed.
771% SECTION                                                                      %
[565]776The CerCo project is interested in the certification of a compiler for C that induces a precise cost model on the source code.
777Our cost model assigns costs to blocks of instructions by tracing the way that blocks are compiled, and by computing exact costs on generated assembly code.
778To perform this accurately, we have provided an executable semantics for the MCS-51 family of processors, better known as 8051/8052.
779The formalisation was done twice, first in O'Caml and then in Matita, and captures the exact timings of the processor.
780Moreover, the O'Caml formalisation also considers timers and I/O.
781Adding support for I/O and timers in Matita is an on-going work that will not present any major problem, and was delayed only because the addition is not immediately useful for the formalisation of the CerCo compiler.
[565]783The formalisation is done at machine level and not at assembly level; we also formalise fetching and decoding.
784We separately provide an assembly language, enhanched with labels and pseudo-instructions, and an assembler from this language to machine code.
785We introduce cost labels in the machine language to relate the data flow of the assembly program to that of the C source language, in order to associate costs to the C program.
786For the O'Caml version, we provide a parser and pretty printer from code memory to Intel HEX format.
787Hence we can perform testing on programs compiled using any free or commercial compiler.
[565]789Our main difficulty in formalising the MCS-51 was the unorthogonality of its memory model and instruction set.
790These problems are easily handled in O'Caml by using advanced language features like polymorphic variants and phantom types, simulating Generalized Abstract Data Types.
791In Matita, we use dependent types to recover the same flexibility, to reduce spurious partiality, and to grant invariants that will be useful in the formalization of the CerCo compiler.
[565]793The formalisation has been partially verified by computing execution traces on selected programs and comparing them with an existing emulator.
794All instructions have been tested at least once, but we have not yet pushed testing further, for example with random testing or by using development boards.
795I/O in particular has not been tested yet, and it is currently unclear how to provide exhaustive testing in the presence of I/O.
796Finally, we are aware of having over-specified the processor in several places, by fixing a behaviour hopefully consistent with the real machine, where manufacturer data sheets are ambiguous or under specified.
806\section{Listing of main O'Caml functions}
809\subsubsection{From \texttt{}}
813Name & Description \\
815\texttt{assembly} & Assembles an abstract syntax tree representing an 8051 assembly program into a list of bytes, its compiled form. \\
816\texttt{initialize} & Initializes the emulator status. \\
817\texttt{load} & Loads an assembled program into the emulator's code memory. \\
818\texttt{fetch} & Fetches the next instruction, and automatically increments the program counter. \\
819\texttt{execute} & Emulates the processor.  Accepts as input a function that pretty prints the emulator status after every emulation loop. \\
[541]823\subsubsection{From \texttt{}}
827Name & Description \\
829\texttt{compute} & Computes a map associating costings to basic blocks in the program.
[540]833\subsubsection{From \texttt{}}
837Name & Description \\
839\texttt{intel\_hex\_of\_file} & Reads in a file and parses it if in Intel IHX format, otherwise raises an exception. \\
840\texttt{process\_intel\_hex} & Accepts a parsed Intel IHX file and populates a hashmap (of the same type as code memory) with the contents.
844\subsubsection{From \texttt{}}
848Name & Description \\
850\texttt{subb8\_with\_c} & Performs an eight bit subtraction on bitvectors.  The function also returns the most important PSW flags for the 8051: carry, auxiliary carry and overflow. \\
851\texttt{add8\_with\_c} & Performs an eight bit addition on bitvectors.  The function also returns the most important PSW flags for the 8051: carry, auxiliary carry and overflow. \\
852\texttt{dec} & Decrements an eight bit bitvector with underflow, if necessary. \\
853\texttt{inc} & Increments an eight bit bitvector with overflow, if necessary.
859\section{Listing of main Matita functions}
862\subsubsection{From \texttt{}}
866Title & Description \\
868\texttt{add\_n\_with\_carry} & Performs an $n$ bit addition on bitvectors.  The function also returns the most important PSW flags for the 8051: carry, auxiliary carry and overflow. \\
869\texttt{sub\_8\_with\_carry} & Performs an eight bit subtraction on bitvectors. The function also returns the most important PSW flags for the 8051: carry, auxiliary carry and overflow. \\
870\texttt{half\_add} & Performs a standard half addition on bitvectors, returning the result and carry bit. \\
871\texttt{full\_add} & Performs a standard full addition on bitvectors and a carry bit, returning the result and a carry bit.
875\subsubsection{From \texttt{}}
879Title & Description \\
881\texttt{assemble1} & Assembles a single 8051 assembly instruction into its memory representation. \\
882\texttt{assemble} & Assembles an 8051 assembly program into its memory representation.\\
883\texttt{assemble\_unlabelled\_program} &\\& Assembles a list of (unlabelled) 8051 assembly instructions into its memory representation.
887\subsubsection{From \texttt{}}
891Title & Description \\
893\texttt{lookup} & Returns the data stored at the end of a particular path (a bitvector) from the trie.  If no data exists, returns a default value. \\
894\texttt{insert} & Inserts data into a tree at the end of the path (a bitvector) indicated.  Automatically expands the tree (by filling in stubs) if necessary.
898\subsubsection{From \texttt{}}
902Title & Description \\
904\texttt{execute\_trace} & Executes an assembly program for a fixed number of steps, recording in a trace which instructions were executed.
908\subsubsection{From \texttt{}}
912Title & Description \\
914\texttt{fetch} & Decodes and returns the instruction currently pointed to by the program counter and automatically increments the program counter the required amount to point to the next instruction. \\
918\subsubsection{From \texttt{}}
922Title & Description \\
924\texttt{execute\_1} & Executes a single step of an 8051 assembly program. \\
925\texttt{execute} & Executes a fixed number of steps of an 8051 assembly program.
929\subsubsection{From \texttt{}}
933Title & Description \\
935\texttt{load} & Loads an assembled 8051 assembly program into code memory.
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