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[493]51\author{Claudio Sacerdoti Coen \and Dominic P. Mulligan}
[492]52\authorrunning{C. Sacerdoti Coen and D. P. Mulligan}
[501]53\title{An executable formalisation of the MCS-51 microprocessor in Matita}
54\titlerunning{An executable formalisation of the MCS-51}
[492]55\institute{Dipartimento di Scienze dell'Informazione, University of Bologna}
[495]62We summarise our formalisation of an emulator for the MCS-51 microprocessor in the Matita proof assistant.
63The MCS-51 is a widely used 8-bit microprocessor, especially popular in embedded devices.
65We proceeded in two stages, first implementing in O'Caml a prototype emulator, where bugs could be `ironed out' quickly.
66We then ported our O'Caml emulator to Matita's internal language.
67Though mostly straight-forward, this porting presented multiple problems.
68Of particular interest is how we handle the extreme non-orthoganality of the MSC-51's instruction set.
69In O'Caml, this was handled through heavy use of polymorphic variants.
[501]70In Matita, we achieve the same effect through a non-standard use of dependent types.
72Both the O'Caml and Matita emulators are `executable'.
73Assembly programs may be animated within Matita, producing a trace of instructions executed.
75Our formalisation is a major component of the ongoing EU-funded CerCo project.
79% SECTION                                                                      %
[512]84Formal methods are designed to increase our confidence in the design and implementation of software (and hardware).
85Ideally, we would like all software to come equipped with a formal specification, along with a proof of correctness for the implementation.
86Today practically all programs are written in high level languages and then compiled into low level ones.
87Specifications are therefore also given at a high level and correctness can be proved by reasoning automatically or interactively on the program's source code.
88The code that is actually run, however, is not the high level source code that we reason on, but the object code that is generated by the compiler.
[512]90A few simple questions now arise:
[509]93What properties are preserved during compilation?
[509]95What properties are affected by the compilation strategy?
[509]97To what extent can you trust your compiler in preserving those properties?
99These questions, and others like them, motivate a current `hot topic' in computer science research: \emph{compiler verification}.
100So far, the field has been focused on the first and last questions only.
101In particular, much attention has been placed on verifying compiler correctness with respect to extensional properties of programs, which are easily preserved during compilation; it is sufficient to completely preserve the denotational semantics of the input program.
[513]103However, if we consider intensional properties of programs---such as space, time or energy spent into computation and transmission of data---the situation is more complex.
104To express even be able to express these properties, and to be able to reason about them, we are forced to adopt a cost model that assigns a cost to single, or blocks, of instructions.
105Ideally, we would like to have a compositional cost model that assigns the same cost to all occurrences of one instruction.
[515]106However, compiler optimisations are inherently non-compositional: each occurrence of a high level instruction is usually compiled in a different way according to the context it finds itself in.
[513]107Therefore both the cost model and intensional specifications are affected by the compilation process.
[514]109In the current EU Project CerCo (`Certified Complexity') we approach the problem of reasoning about intensional properties of programs as follows.
110We are currently developing a compiler that induces a cost model on the high level source code.
111Costs are assigned to each block of high level instructions by considering the costs of the corresponding blocks of compiled object code.
112The cost model is therefore inherently non compositional.
113However, the model has the potential to be extremely \emph{precise}, capturing a program's \emph{realistic} cost, by taking into account, not ignoring, the compilation process.
114A prototype compiler, where no approximation of the cost is provided, has been developed.
[514]116We believe that our approach is especially applicable to certifying real time programs.
117Here, a user can certify that all `deadlines' are met whilst wringing as many clock cycles from the processor---using a cost model that does not over-estimate---as possible.
[515]119Further, we see our approach as being relevant to the field of compiler verification (and construction) itself.
120For instance, an optimisation specified only extensionally is only half specified; though the optimisation may preserve the denotational semantics of a program, there is no guarantee that any intensional properties of the program, such as space or time usage, will be improved.
121Another potential application is toward completeness and correctness of the compilation process in the presence of space constraints.
122Here, a compiler could potentially reject a source program targetting an embedded system when the size of the compiled code exceeds the available ROM size.
123Moreover, preservation of a program's semantics may only be required for those programs that do not exhaust the stack or heap.
124Hence the statement of completeness of the compiler must take in to account a realistic cost model.
[515]126In the methodology proposed in CerCo we assume we are able to compute on the object code exact and realistic costs for sequential blocks of instructions.
127With modern processors, though possible~\cite{??,??,??}, it is difficult to compute exact costs or to reasonably approximate them.
128This is because the execution of a program itself has an influence on the speed of processing.
129For instance, caching and memory effects in the processor are used in advanced features such as branch prediction.
130For this reason CerCo decided to focus on 8-bit microprocessors.
131These are still widely used in embedded systems, and have the advantage of an easily predictable cost model due to the relative sparcity of features that they possess.
[515]133In particular, we have fully formalised an executable formal semantics of a family of 8 bit Freescale Microprocessors~\cite{oliboni}, and provided a similar executable formal semantics for the MCS-51 microprocessor.
134The latter work is what we describe in this paper.
135The main focus of the formalisation has been on capturing the intensional behaviour of the processor.
136However, the design of the MCS-51 itself has caused problems in our formalisation.
137For example, the MCS-51 has a highly unorthogonal instruction set.
138To cope with this unorthogonality, and to produce an executable specification, we have exploited the dependent type system of Matita, an interactive proof assistant.
[493]140\subsection{The 8051/8052}
143The MCS-51 is an eight bit microprocessor introduced by Intel in the late 1970s.
144Commonly called the 8051, in the three decades since its introduction the processor has become a highly popular target for embedded systems engineers.
[515]145Further, the processor, its immediate successor the 8052, and many derivatives are still manufactured \emph{en masse} by a host of semiconductor suppliers.
147The 8051 is a well documented processor, and has the additional support of numerous open source and commercial tools, such as compilers for high-level languages and emulators.
148For instance, the open source Small Device C Compiler (SDCC) recognises a dialect of C, and other compilers targeting the 8051 for BASIC, Forth and Modula-2 are also extant.
[515]149An open source emulator for the processor, MCU-8051 IDE, is also available.
150Both MCU-8051 IDE and SDCC were used profitably in the implementation of our formalisation.
156\caption{High level overview of the 8051 memory layout}
160The 8051 has a relatively straightforward architecture, unencumbered by advanced features of modern processors, making it an ideal target for formalisation.
161A high-level overview of the processor's memory layout is provided in Figure~\ref{fig.memory.layout}.
163Processor RAM is divided into numerous segments, with the most prominent division being between internal and (optional) external memory.
164Internal memory, commonly provided on the die itself with fast access, is further divided into 128 bytes of internal RAM and numerous Special Function Registers (SFRs) which control the operation of the processor.
165Internal RAM (IRAM) is further divided into a eight general purpose bit-addressable registers (R0--R7).
166These sit in the first eight bytes of IRAM, though can be programmatically `shifted up' as needed.
167Bit memory, followed by a small amount of stack space resides in the memory space immediately after the register banks.
168What remains of the IRAM may be treated as general purpose memory.
169A schematic view of IRAM layout is provided in Figure~\ref{fig.iram.layout}.
171External RAM (XRAM), limited to 64 kilobytes, is optional, and may be provided on or off chip, depending on the manufacturer.
172XRAM is accessed using a dedicated instruction.
173External code memory (XCODE) is often stored in the form of an EPROM, and limited to 64 kilobytes in size.
174However, depending on the particular manufacturer and processor model, a dedicated on-die read-only memory area for program code (ICODE) may also be supplied.
176Memory may be addressed in numerous ways: immediate, direct, indirect, external direct and code indirect.
177As the latter two addressing modes hint, there are some restrictions enforced by the 8051 and its derivatives on which addressing modes may be used with specific types of memory.
178For instance, the 128 bytes of extra internal RAM that the 8052 features cannot be addressed using indirect addressing; rather, external (in)direct addressing must be used.
180The 8051 series possesses an eight bit Arithmetic and Logic Unit (ALU), with a wide variety of instructions for performing arithmetic and logical operations on bits and integers.
181Further, the processor possesses two eight bit general purpose accumulators, A and B.
183Communication with the device is facilitated by an onboard UART serial port, and associated serial controller, which can operate in numerous modes.
184Serial baud rate is determined by one of two sixteen bit timers included with the 8051, which can be set to multiple modes of operation.
185(The 8052 provides an additional sixteen bit timer.)
186As an additional method of communication, the 8051 also provides a four byte bit-addressable input-output port.
188The programmer may take advantage of the interrupt mechanism that the processor provides.
189This is especially useful when dealing with input or output involving the serial device, as an interrupt can be set when a whole character is sent or received via the serial port.
191Interrupts immediately halt the flow of execution of the processor, and cause the program counter to jump to a fixed address, where the requisite interrupt handler is stored.
192However, interrupts may be set to one of two priorities: low and high.
193The interrupt handler of an interrupt with high priority is executed ahead of the interrupt handler of an interrupt of lower priority, interrupting a currently executing handler of lower priority, if necessary.
195The 8051 has interrupts disabled by default.
196The programmer is free to handle serial input and output manually, by poking serial flags in the SFRs.
197Similarly, `exceptional circumstances' that would otherwise trigger an interrupt on more modern processors, for example, division by zero, are also signalled by setting flags.
203\caption{Schematic view of 8051 IRAM layout}
208% SECTION                                                                      %
210\subsection{Overview of paper}
[494]213In Section~\ref{sect.development.strategy} we provide a brief overview of how we designed and implemented the formalised microprocessor emulator.
214In Section~\ref{} we describe how we made use of dependent types to handle some of the idiosyncracies of the microprocessor.
215In Section~\ref{} we describe the relation our work has to
218% SECTION                                                                      %
[495]220\section{From O'Caml prototype to Matita formalisation}
[506]223Our implementation progressed in two stages:
225\paragraph{O'Caml prototype}
[506]226We began with an emulator written in O'Caml.
227We used this to `iron out' any bugs in our design and implementation within O'Caml's more permissive type system.
228O'Caml's ability to perform file input-output also eased debugging and validation.
229Once we were happy with the performance and design of the O'Caml emulator, we moved to the Matita formalisation.
231\paragraph{Matita formalisation}
[506]232Matita's syntax is lexically similar to O'Caml's.
233This eased the translation, as large swathes of code were merely copy-pasted with minor modifications.
234However, several major issues had to be addresses when moving from O'Caml to Matita.
235These are now discussed.
238% SECTION                                                                      %
[494]240\section{Design issues in the formalisation}
244% SECTION                                                                      %
[494]246\subsection{Labels and pseudoinstructions}
[508]249As part of the CerCo project, a prototype compiler was being developed in parallel with the emulator.
250Easing the design of the compiler was a key objective in implementing the emulator.
251For this reason, we introduced notion of \emph{pseudoinstruction} and \emph{label}.
[508]253The MCS-51's instruction set has numerous instructions for unconditional and conditional jumps to memory locations, calling procedures and moving data between memory spaces.
254For instance, the instructions \texttt{AJMP}, \texttt{JMP} and \texttt{LJMP} all perform unconditional jumps.
255However, these instructions differ in how large the maximum size of the offset of the jump to be performed can be.
256Further, all jump instructions require a concrete memory address, to jump to, to be specified.
257Requiring the compiler to compute these offsets, and select appropriate jump instructions, was seen as needleslly burdensome.
[508]259Instead, we introduced generic \texttt{Jump}, \texttt{Call} and \texttt{Move} instructions.
260These are expanded into MCS-51 assembly instructions with an assembly phase, prior to program execution.
261Further, we introduced a notion of label (represented by strings), and introduced pseudoinstructions that allow conditional jumps to jump to labels.
262These are also removed during the assembly phase, and replaced by concrete memory addresses and offsets.
265% SECTION                                                                      %
[511]267\subsection{Representing memory}
271% SECTION                                                                      %
[494]273\subsection{Putting dependent types to work}
[510]276We typeset O'Caml source with blue, and Matita source with red.
[508]278A peculiarity of the MCS-51 is the non-orthogonality of its instruction set.
279For instance, the \texttt{MOV} instruction, can be invoked using one of sixteen combinations of addressing modes.
281Such non-orthogonality in the instruction set was handled with the use of polymorphic variants in the O'Caml emulator.
282For instance, we introduced types corresponding to each addressing mode:
285type direct = [ `DIRECT of byte ]
286type indirect = [ `INDIRECT of bit ]
290Which were then used in our inductive datatype for assembly instructions, as follows:
293type 'addr preinstruction =
294 [ `ADD of acc * [ reg | direct | indirect | data ]
296 | `MOV of
297    (acc * [ reg | direct | indirect | data ],
298     [ reg | indirect ] * [ acc | direct | data ],
299     direct * [ acc | reg | direct | indirect | data ],
300     dptr * data16,
301     carry * bit,
302     bit * carry
303     ) union6
307Here, \texttt{union6} is a disjoint union type, defined as follows:
310type ('a,'b,'c,'d,'e,'f) union6 = [ `U1 of 'a | ... | `U6 of 'f ]
[510]313For our purposes, the types \texttt{union2}, \texttt{union3} and \texttt{union6} sufficed.
[510]315This polymorphic variant machinery worked well: it introduced a certain level of type safety (for instance, the type of our \texttt{MOV} instruction above guarantees it cannot be invoked with arguments in the \texttt{carry} and \texttt{data16} addressing modes, respectively), and also allowed us to pattern match against instructions, when necessary.
316However, this polymorphic variant machinery is \emph{not} present in Matita.
317We needed some way to produce the same effect, which Matita supported.
318For this task, we used dependent types.
[510]320We first provided an inductive data type representing all possible addressing modes, a type that functions will pattern match against:
[510]323inductive addressing_mode: Type[0] ≝
[495]324  DIRECT: Byte $\rightarrow$ addressing_mode
325| INDIRECT: Bit $\rightarrow$ addressing_mode
[510]329We also wished to express in the type of functions the \emph{impossibility} of pattern matching against certain constructors.
330In order to do this, we introduced an inductive type of addressing mode `tags'.
331The constructors of \texttt{addressing\_mode\_tag} are in one-to-one correspondence with the constructors of \texttt{addressing\_mode}:
[510]334inductive addressing_mode_tag : Type[0] ≝
[495]335  direct: addressing_mode_tag
336| indirect: addressing_mode_tag
[510]340A function that checks whether an \texttt{addressing\_mode} is `morally' an \texttt{addressing\_mode\_tag} is provided, as follows:
[510]343let rec is_a (d: addressing_mode_tag) (A: addressing_mode) on d ≝
[495]344  match d with
345   [ direct $\Rightarrow$ match A with [ DIRECT _ $\Rightarrow$ true | _ $\Rightarrow$ false ]
346   | indirect $\Rightarrow$ match A with [ INDIRECT _ $\Rightarrow$ true | _ $\Rightarrow$ false ]
350We also extend this check to vectors of \texttt{addressing\_mode\_tag}'s in the obvious manner:
[510]353let rec is_in (n) (l: Vector addressing_mode_tag n) (A: addressing_mode) on l ≝
354 match l return $\lambda$m.$\lambda$_: Vector addressing_mode_tag m. bool with
[495]355  [ VEmpty $\Rightarrow$ false
356  | VCons m he (tl: Vector addressing_mode_tag m) $\Rightarrow$
357     is_a he A $\vee$ is_in ? tl A ].
360Here \texttt{VEmpty} and \texttt{VCons} are the two constructors of the \texttt{Vector} data type, and $\mathtt{\vee}$ is inclusive disjunction on Booleans.
[510]363record subaddressing_mode (n: Nat) (l: Vector addressing_mode_tag (S n)) : Type[0] ≝
365  subaddressing_modeel :> addressing_mode;
366  subaddressing_modein: bool_to_Prop (is_in ? l subaddressing_modeel)
370We can now provide an inductive type of preinstructions with precise typings:
[510]373inductive preinstruction (A: Type[0]): Type[0] ≝
[495]374   ADD: $\llbracket$ acc_a $\rrbracket$ $\rightarrow$ $\llbracket$ register; direct; indirect; data $\rrbracket$ $\rightarrow$ preinstruction A
375 | ADDC: $\llbracket$ acc_a $\rrbracket$ $\rightarrow$ $\llbracket$ register; direct; indirect; data $\rrbracket$ $\rightarrow$ preinstruction A
379Here $\llbracket - \rrbracket$ is syntax denoting a vector.
380We see that the constructor \texttt{ADD} expects two parameters, the first being the accumulator A (\texttt{acc\_a}), and the second being one of a register, direct, indirect or data addressing mode.
382The final, missing component is a pair of type coercions from \texttt{addressing\_mode} to \texttt{subaddressing\_mode} and from \texttt{subaddressing\_mode} to \texttt{Type$\lbrack0\rbrack$}, respectively.
383The previous machinery allows us to state in the type of a function what addressing modes that function expects.
384For instance, consider \texttt{set\_arg\_16}, which expects only a \texttt{DPTR}:
[510]387definition set_arg_16: Status $\rightarrow$ Word $\rightarrow$ $\llbracket$ dptr $\rrbracket$ $\rightarrow$ Status ≝
[495]388  $\lambda$s, v, a.
389   match a return $\lambda$x. bool_to_Prop (is_in ? $\llbracket$ dptr $\rrbracket$ x) $\rightarrow$ ? with
390     [ DPTR $\Rightarrow$ $\lambda$_: True.
391       let 〈 bu, bl 〉 := split $\ldots$ eight eight v in
392       let status := set_8051_sfr s SFR_DPH bu in
393       let status := set_8051_sfr status SFR_DPL bl in
394         status
395     | _ $\Rightarrow$ $\lambda$_: False.
396       match K in False with
397       [
398       ]
399     ] (subaddressing_modein $\ldots$ a).
402All other cases are discharged by the catch-all at the bottom of the match expression.
403Attempting to match against another addressing mode not indicated in the type (for example, \texttt{REGISTER}) will produce a type-error.
406% SECTION                                                                      %
[511]411We spent considerable effort attempting to ensure that our formalisation is correct, that is, what we have formalised really is an accurate model of the MCS-51 microprocessor.
413First, we made use of multiple data sheets, each from a different semiconductor manufacturer.
414This helped us spot errors in the specification of the processor's instruction set, and its behaviour.
416The O'Caml prototype was especially useful for validation purposes.
417This is because we wrote a module for parsing and loading the Intel HEX file format.
418HEX is a standard format that all compilers targetting the MCS-51, and similar processors, produce.
419It is essentially a snapshot of the processor's code memory in compressed form.
420Using this, we were able to compile C programs with SDCC, an open source compiler, and load the resulting program directly into our emulator's code memory, ready for execution.
421Further, we are able to produce a HEX file from our emulator's code memory, for loading into third party tools.
422After each step of execution, we can print out both the instruction that had been executed, along with its arguments, and a snapshot of the processor's state, including all flags and register contents.
423For example:
42808: mov 81 #07
430 Processor status:                               
432   ACC : 0 (00000000) B   : 0 (00000000)
433   PSW : 0 (00000000) with flags set as:
434     CY  : false   AC  : false
435     FO  : false   RS1 : false
436     RS0 : false   OV  : false
437     UD  : false   P   : false
438   SP  : 7 (00000111) IP  : 0 (00000000)
439   PC  : 8 (0000000000001000)
440   DPL : 0 (00000000) DPH : 0 (00000000)
441   SCON: 0 (00000000) SBUF: 0 (00000000)
442   TMOD: 0 (00000000) TCON: 0 (00000000)
443   Registers:                                   
444    R0 : 0 (00000000) R1 : 0 (00000000)
445    R2 : 0 (00000000) R3 : 0 (00000000)
446    R4 : 0 (00000000) R5 : 0 (00000000)
447    R6 : 0 (00000000) R7 : 0 (00000000)
452Here, the traces indicates that the instruction \texttt{mov 81 \#07} has just been executed by the processor, which is now in the state indicated.
453These traces were useful in spotting anything that was `obviously' wrong with the execution of the program.
455Further, we made use of an open source emulator for the MCS-51, \texttt{mcu8051ide}.
456Using our execution traces, we were able to step through a compiled program, one instruction at a time, in \texttt{mcu8051ide}, and compare the resulting execution trace with the trace produced by our emulator.
458Our Matita formalisation was largely copied from the O'Caml source code, apart from changes related to addressing modes already mentioned.
459However, as the Matita emulator is executable, we could perform further validation by comparing the trace of a program's execution in the Matita emulator with the trace of the same program in the O'Caml emulator.
462% SECTION                                                                      %
[493]464\section{Related work}
468% SECTION                                                                      %
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