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[493]51\author{Claudio Sacerdoti Coen \and Dominic P. Mulligan}
[492]52\authorrunning{C. Sacerdoti Coen and D. P. Mulligan}
[501]53\title{An executable formalisation of the MCS-51 microprocessor in Matita}
54\titlerunning{An executable formalisation of the MCS-51}
[492]55\institute{Dipartimento di Scienze dell'Informazione, University of Bologna}
[495]62We summarise our formalisation of an emulator for the MCS-51 microprocessor in the Matita proof assistant.
63The MCS-51 is a widely used 8-bit microprocessor, especially popular in embedded devices.
65We proceeded in two stages, first implementing in O'Caml a prototype emulator, where bugs could be `ironed out' quickly.
66We then ported our O'Caml emulator to Matita's internal language.
67Though mostly straight-forward, this porting presented multiple problems.
68Of particular interest is how we handle the extreme non-orthoganality of the MSC-51's instruction set.
69In O'Caml, this was handled through heavy use of polymorphic variants.
[501]70In Matita, we achieve the same effect through a non-standard use of dependent types.
72Both the O'Caml and Matita emulators are `executable'.
73Assembly programs may be animated within Matita, producing a trace of instructions executed.
75Our formalisation is a major component of the ongoing EU-funded CerCo project.
79% SECTION                                                                      %
[512]84Formal methods are designed to increase our confidence in the design and implementation of software (and hardware).
85Ideally, we would like all software to come equipped with a formal specification, along with a proof of correctness for the implementation.
86Today practically all programs are written in high level languages and then compiled into low level ones.
87Specifications are therefore also given at a high level and correctness can be proved by reasoning automatically or interactively on the program's source code.
88The code that is actually run, however, is not the high level source code that we reason on, but the object code that is generated by the compiler.
[512]90A few simple questions now arise:
[509]93What properties are preserved during compilation?
[509]95What properties are affected by the compilation strategy?
[509]97To what extent can you trust your compiler in preserving those properties?
[512]100These questions, and others like them, motivate a current `hot topic' in computer science research: \emph{compiler verification}.
101So far, the field has been focused on the first and last questions only.
102In particular, much attention has been placed on verifying compiler correctness with respect to extensional properties of programs, which are easily preserved during compilation; it is sufficient to completely preserve the denotational semantics of the input program.
104The situation is definitely more complex when we also take in account
105intesional properties of programs, like space, time or energy spent into
106computation and transmission of data. To express this properties and to
107reason on them we are forced to adopt a cost model that assigns a cost to
108single instructions or to blocks of instructions. Morally, we would like to
109have a compositional cost model that assigns the same cost to all occurrences
110of one instruction. However, compiler optimizations are inherently non
111compositional: each occurrence of an high level instruction is usually compiled
112in a different way according to the surrounding instructions. Hence the cost
113model is affected by compilation and thus all intensional specifications are as
116In the EU Project CerCo (Certified Complexity) we will approach the problem
117by developing a compiler that induces the cost model on the source code by
118assigning to each block of high level instructions the cost associated to the
119obtained object code. The cost model will thus be inherently non compositional,
120but it can be extremely \emph{precise}, capturing the realistic cost. In
121particular, we already have a prototype where no approximation of the cost
122is provided at all. The natural applications of our approach are then in the
123domain of hard real time programs, where the user can certify the meeting of
124all dealines while fully exploiting the computational time, that would be
125wasted in case of over-estimation of the costs.
127Other applications of our approach are in the domain of compiler verification
128itself. For instance, an extensional specification of an optimization is useless
129since it grants preservation of the semantics without stating that the cost
130(in space or time) of the optimized code should be lower. Another example is
131completeness and correctness of the compilation process in presence of
132space constraints: the compiler could refuse a source
133program for an embedded system when the size of the compiled code exceeds the
134available ROM size. Moreover, preservation of the semantics must be required
135only for those programs that do not exhausts their stack/heap space. Hence the
136statement of completeness of the compiler must take in account the realistic
137cost model.
139In the methodology proposed in CerCo we assume to be able to compute on the
140object code exact and realistic costs for sequential blocks of instructions.
141With modern processors, it is possible~\cite{??,??,??}, but difficult,
142to compute exact costs or to reasonably approximate them, since the execution
143of the program itself has an influence on the speed of processing. This is due
144mainly to caching effects and memory effects in the processor, used, for
145instance, to perform branch prediction. For this reason, at the current stage
146of CerCo we decided to focus on 8-bits microprocessors that are still widely
147used in embedded systems and whose cost model is easily predictable.
149In particular, we have fully formalized an executable formal semantics of
150the Family of 8 bits Freescale Microprocessors~\cite{oliboni} and a similar
151one for the MCS-51 microprocessors. The latter is the one described in this
152paper. The main focus of the formalization has been on capturing the
153intensional behaviour of the processor. The main problems we have faced,
154however, are mainly due to the extreme unorthogonality of the memory model
155and instruction sets of the MCS-51 microprocessors. To cope with this
156unorthogonality and to have executability, we have exploited the dependent
157type system of the interactive theorem prover Matita.
159%Compiler verification, as of late, is a `hot topic' in computer science research.
160%This rapidly growing field is motivated by one simple question: `to what extent can you trust your compiler?'
161%Existing verification efforts have broadly focussed on \emph{semantic correctness}, that is, creating a compiler that is guaranteed to preserve the semantics of a program during the compilation process.
162%However, there is another important facet of correctness that has not garnered much attention, that is, correctness with respect to some intensional properties of the program to be compiled.
[493]164\subsection{The 8051/8052}
167The MCS-51 is an eight bit microprocessor introduced by Intel in the late 1970s.
168Commonly called the 8051, in the three decades since its introduction the processor has become a highly popular target for embedded systems engineers.
169Further, the processor and its immediate successor, the 8052, is still manufactured by a host of semiconductor suppliers---many of them European---including Atmel, Siemens Semiconductor, NXP (formerly Phillips Semiconductor), Texas Instruments, and Maxim (formerly Dallas Semiconductor).
171The 8051 is a well documented processor, and has the additional support of numerous open source and commercial tools, such as compilers for high-level languages and emulators.
172For instance, the open source Small Device C Compiler (SDCC) recognises a dialect of C, and other compilers targeting the 8051 for BASIC, Forth and Modula-2 are also extant.
173An open source emulator for the processor, MCU8051 IDE, is also available.
179\caption{High level overview of the 8051 memory layout}
183The 8051 has a relatively straightforward architecture, unencumbered by advanced features of modern processors, making it an ideal target for formalisation.
184A high-level overview of the processor's memory layout is provided in Figure~\ref{fig.memory.layout}.
186Processor RAM is divided into numerous segments, with the most prominent division being between internal and (optional) external memory.
187Internal memory, commonly provided on the die itself with fast access, is further divided into 128 bytes of internal RAM and numerous Special Function Registers (SFRs) which control the operation of the processor.
188Internal RAM (IRAM) is further divided into a eight general purpose bit-addressable registers (R0--R7).
189These sit in the first eight bytes of IRAM, though can be programmatically `shifted up' as needed.
190Bit memory, followed by a small amount of stack space resides in the memory space immediately after the register banks.
191What remains of the IRAM may be treated as general purpose memory.
192A schematic view of IRAM layout is provided in Figure~\ref{fig.iram.layout}.
194External RAM (XRAM), limited to 64 kilobytes, is optional, and may be provided on or off chip, depending on the manufacturer.
195XRAM is accessed using a dedicated instruction.
196External code memory (XCODE) is often stored in the form of an EPROM, and limited to 64 kilobytes in size.
197However, depending on the particular manufacturer and processor model, a dedicated on-die read-only memory area for program code (ICODE) may also be supplied.
199Memory may be addressed in numerous ways: immediate, direct, indirect, external direct and code indirect.
200As the latter two addressing modes hint, there are some restrictions enforced by the 8051 and its derivatives on which addressing modes may be used with specific types of memory.
201For instance, the 128 bytes of extra internal RAM that the 8052 features cannot be addressed using indirect addressing; rather, external (in)direct addressing must be used.
203The 8051 series possesses an eight bit Arithmetic and Logic Unit (ALU), with a wide variety of instructions for performing arithmetic and logical operations on bits and integers.
204Further, the processor possesses two eight bit general purpose accumulators, A and B.
206Communication with the device is facilitated by an onboard UART serial port, and associated serial controller, which can operate in numerous modes.
207Serial baud rate is determined by one of two sixteen bit timers included with the 8051, which can be set to multiple modes of operation.
208(The 8052 provides an additional sixteen bit timer.)
209As an additional method of communication, the 8051 also provides a four byte bit-addressable input-output port.
211The programmer may take advantage of the interrupt mechanism that the processor provides.
212This is especially useful when dealing with input or output involving the serial device, as an interrupt can be set when a whole character is sent or received via the serial port.
214Interrupts immediately halt the flow of execution of the processor, and cause the program counter to jump to a fixed address, where the requisite interrupt handler is stored.
215However, interrupts may be set to one of two priorities: low and high.
216The interrupt handler of an interrupt with high priority is executed ahead of the interrupt handler of an interrupt of lower priority, interrupting a currently executing handler of lower priority, if necessary.
218The 8051 has interrupts disabled by default.
219The programmer is free to handle serial input and output manually, by poking serial flags in the SFRs.
220Similarly, `exceptional circumstances' that would otherwise trigger an interrupt on more modern processors, for example, division by zero, are also signalled by setting flags.
226\caption{Schematic view of 8051 IRAM layout}
231% SECTION                                                                      %
233\subsection{Overview of paper}
[494]236In Section~\ref{sect.development.strategy} we provide a brief overview of how we designed and implemented the formalised microprocessor emulator.
237In Section~\ref{} we describe how we made use of dependent types to handle some of the idiosyncracies of the microprocessor.
238In Section~\ref{} we describe the relation our work has to
241% SECTION                                                                      %
[495]243\section{From O'Caml prototype to Matita formalisation}
[506]246Our implementation progressed in two stages:
248\paragraph{O'Caml prototype}
[506]249We began with an emulator written in O'Caml.
250We used this to `iron out' any bugs in our design and implementation within O'Caml's more permissive type system.
251O'Caml's ability to perform file input-output also eased debugging and validation.
252Once we were happy with the performance and design of the O'Caml emulator, we moved to the Matita formalisation.
254\paragraph{Matita formalisation}
[506]255Matita's syntax is lexically similar to O'Caml's.
256This eased the translation, as large swathes of code were merely copy-pasted with minor modifications.
257However, several major issues had to be addresses when moving from O'Caml to Matita.
258These are now discussed.
261% SECTION                                                                      %
[494]263\section{Design issues in the formalisation}
267% SECTION                                                                      %
[494]269\subsection{Labels and pseudoinstructions}
[508]272As part of the CerCo project, a prototype compiler was being developed in parallel with the emulator.
273Easing the design of the compiler was a key objective in implementing the emulator.
274For this reason, we introduced notion of \emph{pseudoinstruction} and \emph{label}.
[508]276The MCS-51's instruction set has numerous instructions for unconditional and conditional jumps to memory locations, calling procedures and moving data between memory spaces.
277For instance, the instructions \texttt{AJMP}, \texttt{JMP} and \texttt{LJMP} all perform unconditional jumps.
278However, these instructions differ in how large the maximum size of the offset of the jump to be performed can be.
279Further, all jump instructions require a concrete memory address, to jump to, to be specified.
280Requiring the compiler to compute these offsets, and select appropriate jump instructions, was seen as needleslly burdensome.
[508]282Instead, we introduced generic \texttt{Jump}, \texttt{Call} and \texttt{Move} instructions.
283These are expanded into MCS-51 assembly instructions with an assembly phase, prior to program execution.
284Further, we introduced a notion of label (represented by strings), and introduced pseudoinstructions that allow conditional jumps to jump to labels.
285These are also removed during the assembly phase, and replaced by concrete memory addresses and offsets.
288% SECTION                                                                      %
[511]290\subsection{Representing memory}
294% SECTION                                                                      %
[494]296\subsection{Putting dependent types to work}
[510]299We typeset O'Caml source with blue, and Matita source with red.
[508]301A peculiarity of the MCS-51 is the non-orthogonality of its instruction set.
302For instance, the \texttt{MOV} instruction, can be invoked using one of sixteen combinations of addressing modes.
304Such non-orthogonality in the instruction set was handled with the use of polymorphic variants in the O'Caml emulator.
305For instance, we introduced types corresponding to each addressing mode:
308type direct = [ `DIRECT of byte ]
309type indirect = [ `INDIRECT of bit ]
313Which were then used in our inductive datatype for assembly instructions, as follows:
316type 'addr preinstruction =
317 [ `ADD of acc * [ reg | direct | indirect | data ]
319 | `MOV of
320    (acc * [ reg | direct | indirect | data ],
321     [ reg | indirect ] * [ acc | direct | data ],
322     direct * [ acc | reg | direct | indirect | data ],
323     dptr * data16,
324     carry * bit,
325     bit * carry
326     ) union6
330Here, \texttt{union6} is a disjoint union type, defined as follows:
333type ('a,'b,'c,'d,'e,'f) union6 = [ `U1 of 'a | ... | `U6 of 'f ]
[510]336For our purposes, the types \texttt{union2}, \texttt{union3} and \texttt{union6} sufficed.
[510]338This polymorphic variant machinery worked well: it introduced a certain level of type safety (for instance, the type of our \texttt{MOV} instruction above guarantees it cannot be invoked with arguments in the \texttt{carry} and \texttt{data16} addressing modes, respectively), and also allowed us to pattern match against instructions, when necessary.
339However, this polymorphic variant machinery is \emph{not} present in Matita.
340We needed some way to produce the same effect, which Matita supported.
341For this task, we used dependent types.
[510]343We first provided an inductive data type representing all possible addressing modes, a type that functions will pattern match against:
[510]346inductive addressing_mode: Type[0] ≝
[495]347  DIRECT: Byte $\rightarrow$ addressing_mode
348| INDIRECT: Bit $\rightarrow$ addressing_mode
[510]352We also wished to express in the type of functions the \emph{impossibility} of pattern matching against certain constructors.
353In order to do this, we introduced an inductive type of addressing mode `tags'.
354The constructors of \texttt{addressing\_mode\_tag} are in one-to-one correspondence with the constructors of \texttt{addressing\_mode}:
[510]357inductive addressing_mode_tag : Type[0] ≝
[495]358  direct: addressing_mode_tag
359| indirect: addressing_mode_tag
[510]363A function that checks whether an \texttt{addressing\_mode} is `morally' an \texttt{addressing\_mode\_tag} is provided, as follows:
[510]366let rec is_a (d: addressing_mode_tag) (A: addressing_mode) on d ≝
[495]367  match d with
368   [ direct $\Rightarrow$ match A with [ DIRECT _ $\Rightarrow$ true | _ $\Rightarrow$ false ]
369   | indirect $\Rightarrow$ match A with [ INDIRECT _ $\Rightarrow$ true | _ $\Rightarrow$ false ]
373We also extend this check to vectors of \texttt{addressing\_mode\_tag}'s in the obvious manner:
[510]376let rec is_in (n) (l: Vector addressing_mode_tag n) (A: addressing_mode) on l ≝
377 match l return $\lambda$m.$\lambda$_: Vector addressing_mode_tag m. bool with
[495]378  [ VEmpty $\Rightarrow$ false
379  | VCons m he (tl: Vector addressing_mode_tag m) $\Rightarrow$
380     is_a he A $\vee$ is_in ? tl A ].
383Here \texttt{VEmpty} and \texttt{VCons} are the two constructors of the \texttt{Vector} data type, and $\mathtt{\vee}$ is inclusive disjunction on Booleans.
[510]386record subaddressing_mode (n: Nat) (l: Vector addressing_mode_tag (S n)) : Type[0] ≝
388  subaddressing_modeel :> addressing_mode;
389  subaddressing_modein: bool_to_Prop (is_in ? l subaddressing_modeel)
393We can now provide an inductive type of preinstructions with precise typings:
[510]396inductive preinstruction (A: Type[0]): Type[0] ≝
[495]397   ADD: $\llbracket$ acc_a $\rrbracket$ $\rightarrow$ $\llbracket$ register; direct; indirect; data $\rrbracket$ $\rightarrow$ preinstruction A
398 | ADDC: $\llbracket$ acc_a $\rrbracket$ $\rightarrow$ $\llbracket$ register; direct; indirect; data $\rrbracket$ $\rightarrow$ preinstruction A
402Here $\llbracket - \rrbracket$ is syntax denoting a vector.
403We see that the constructor \texttt{ADD} expects two parameters, the first being the accumulator A (\texttt{acc\_a}), and the second being one of a register, direct, indirect or data addressing mode.
405The final, missing component is a pair of type coercions from \texttt{addressing\_mode} to \texttt{subaddressing\_mode} and from \texttt{subaddressing\_mode} to \texttt{Type$\lbrack0\rbrack$}, respectively.
406The previous machinery allows us to state in the type of a function what addressing modes that function expects.
407For instance, consider \texttt{set\_arg\_16}, which expects only a \texttt{DPTR}:
[510]410definition set_arg_16: Status $\rightarrow$ Word $\rightarrow$ $\llbracket$ dptr $\rrbracket$ $\rightarrow$ Status ≝
[495]411  $\lambda$s, v, a.
412   match a return $\lambda$x. bool_to_Prop (is_in ? $\llbracket$ dptr $\rrbracket$ x) $\rightarrow$ ? with
413     [ DPTR $\Rightarrow$ $\lambda$_: True.
414       let 〈 bu, bl 〉 := split $\ldots$ eight eight v in
415       let status := set_8051_sfr s SFR_DPH bu in
416       let status := set_8051_sfr status SFR_DPL bl in
417         status
418     | _ $\Rightarrow$ $\lambda$_: False.
419       match K in False with
420       [
421       ]
422     ] (subaddressing_modein $\ldots$ a).
425All other cases are discharged by the catch-all at the bottom of the match expression.
426Attempting to match against another addressing mode not indicated in the type (for example, \texttt{REGISTER}) will produce a type-error.
429% SECTION                                                                      %
[511]434We spent considerable effort attempting to ensure that our formalisation is correct, that is, what we have formalised really is an accurate model of the MCS-51 microprocessor.
436First, we made use of multiple data sheets, each from a different semiconductor manufacturer.
437This helped us spot errors in the specification of the processor's instruction set, and its behaviour.
439The O'Caml prototype was especially useful for validation purposes.
440This is because we wrote a module for parsing and loading the Intel HEX file format.
441HEX is a standard format that all compilers targetting the MCS-51, and similar processors, produce.
442It is essentially a snapshot of the processor's code memory in compressed form.
443Using this, we were able to compile C programs with SDCC, an open source compiler, and load the resulting program directly into our emulator's code memory, ready for execution.
444Further, we are able to produce a HEX file from our emulator's code memory, for loading into third party tools.
445After each step of execution, we can print out both the instruction that had been executed, along with its arguments, and a snapshot of the processor's state, including all flags and register contents.
446For example:
45108: mov 81 #07
453 Processor status:                               
455   ACC : 0 (00000000) B   : 0 (00000000)
456   PSW : 0 (00000000) with flags set as:
457     CY  : false   AC  : false
458     FO  : false   RS1 : false
459     RS0 : false   OV  : false
460     UD  : false   P   : false
461   SP  : 7 (00000111) IP  : 0 (00000000)
462   PC  : 8 (0000000000001000)
463   DPL : 0 (00000000) DPH : 0 (00000000)
464   SCON: 0 (00000000) SBUF: 0 (00000000)
465   TMOD: 0 (00000000) TCON: 0 (00000000)
466   Registers:                                   
467    R0 : 0 (00000000) R1 : 0 (00000000)
468    R2 : 0 (00000000) R3 : 0 (00000000)
469    R4 : 0 (00000000) R5 : 0 (00000000)
470    R6 : 0 (00000000) R7 : 0 (00000000)
475Here, the traces indicates that the instruction \texttt{mov 81 \#07} has just been executed by the processor, which is now in the state indicated.
476These traces were useful in spotting anything that was `obviously' wrong with the execution of the program.
478Further, we made use of an open source emulator for the MCS-51, \texttt{mcu8051ide}.
479Using our execution traces, we were able to step through a compiled program, one instruction at a time, in \texttt{mcu8051ide}, and compare the resulting execution trace with the trace produced by our emulator.
481Our Matita formalisation was largely copied from the O'Caml source code, apart from changes related to addressing modes already mentioned.
482However, as the Matita emulator is executable, we could perform further validation by comparing the trace of a program's execution in the Matita emulator with the trace of the same program in the O'Caml emulator.
485% SECTION                                                                      %
[493]487\section{Related work}
491% SECTION                                                                      %
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