source: Deliverables/D4.1/ASMInterpret.mli @ 215

Last change on this file since 215 was 215, checked in by mulligan, 9 years ago

More on implementation of interrupts. Need to add a queue for
interrupts that occur `at the same time' to be executed once interrupts
with higher priority have finished.

File size: 2.9 KB
Line 
1open BitVectors;;
2open Physical;;
3
4exception CodeTooLarge
5
6type time = int;;
7type line = [ `P1 of byte
8            | `P3 of byte
9            | `SerialBuff of [ `Eight of byte
10                             | `Nine of BitVectors.bit * byte
11                             ]
12            ];;
13
14type interrupt =
15  Timer0
16| Timer1
17| External0
18| External1
19;;
20
21val string_of_line: line -> string;;
22
23type epsilon = int;;
24
25(* In:  reception time, line of input, new continuation,
26   Out: transmission time, output line, expected duration until reply,
27        new continuation.
28*)
29type continuation =
30  [`In of time * line * epsilon * continuation] option *
31  [`Out of (time -> line -> time * continuation) ];;
32
33type status =
34{
35  (* Memory *)
36  code_memory: WordMap.map;        (* can be reduced *)
37  low_internal_ram: Byte7Map.map;
38  high_internal_ram: Byte7Map.map;
39  external_ram: WordMap.map;
40
41  (* Program counter *)
42  pc: word;
43
44  (* SFRs *)
45  sp: byte;
46  dpl: byte;
47  dph: byte;
48  pcon: byte;
49  tcon: byte;
50  tmod: byte;
51  tl0: byte;
52  tl1: byte;
53  th0: byte;
54  th1: byte;
55  p1: byte;
56  scon: byte;
57  sbuf: byte;
58  ie: byte;
59  p3: byte;
60  ip: byte;
61  psw: byte;
62  acc: byte;
63  b: byte;
64  t2con: byte;   (* 8052 only *)
65  rcap2l: byte;  (* 8052 only *)
66  rcap2h: byte;  (* 8052 only *)
67  tl2: byte;     (* 8052 only *)
68  th2: byte;     (* 8052 only *)
69
70  (* Latches for the output lines *)
71  p1_latch: byte;
72  p3_latch: byte;
73
74  (* Fields for tracking the state of the processor. *)
75 
76  (* IO specific *)
77  previous_p1_val: bool;
78  previous_p3_val: bool;
79
80  serial_epsilon_out: epsilon option;
81  serial_epsilon_in: epsilon option;
82
83  io_epsilon: epsilon;
84
85  serial_v_in: [`Eight of byte | `Nine of (BitVectors.bit * byte) ] option;
86  serial_v_out: [`Eight of byte | `Nine of (BitVectors.bit * byte) ] option;
87
88  serial_k_out: continuation option;
89
90  io: continuation;
91  expected_out_time: [ `None | `Now | `At of time ];
92
93  (* Timer and clock specific *)
94  clock: time;
95  timer0: word;
96  timer1: word;
97  timer2: word;  (* can be missing *)
98
99  esi_running: bool;
100  t0i_running: bool;
101  t1i_running: bool;
102  e0i_running: bool;
103  e1i_running: bool;
104
105  interrupt_queue: interrupt list;
106}
107
108val string_of_status: status -> string
109
110module IntMap: Map.S with type key = int
111
112val assembly: ASM.assembly_program -> BitVectors.byte list (*ASM.instruction list * symbol_table *) * string IntMap.t
113
114(*
115val link:
116 (ASM.instruction list * symbol_table * cost_map) list -> BitVectors.byte list
117*)
118
119val initialize: status
120
121val load_mem: Physical.WordMap.map -> status -> status
122val load: BitVectors.byte list -> status -> status
123
124exception Halt  (* to be raised to stop execution *)
125
126(* the callback function is used to observe the execution
127   trace; it can raise Hold to stop execution. Otherwise
128   the processor never halts. *)
129val execute: (status -> unit) -> status -> status
130
131val fetch: Physical.WordMap.map -> word -> ASM.instruction * word * int
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