source: Deliverables/D2.2/8051/src/ASM/I8051.mli

Last change on this file was 1568, checked in by tranquil, 8 years ago
  • Immediates introduced (but not fully used yet in RTLabs to RTL pass)
  • translation streamlined
  • BUGGY: interpretation fails in LTL, trying to fetch a function with incorrect address
File size: 1.6 KB
Line 
1
2include Arch.S
3
4type opaccs =
5  | Mul
6  | DivuModu
7
8type op1 =
9  | Cmpl
10  | Inc
11  (* | Dec *)
12  | Rl
13
14type op2 =
15  | Add
16  | Addc
17  | Sub
18  | And
19  | Or
20  | Xor
21
22val print_opaccs : opaccs -> string
23val print_op1 : op1 -> string
24val print_op2 : op2 -> string
25
26module Eval (Val : Value.S) : sig
27  val opaccs : opaccs -> Val.t -> Val.t ->
28               (Val.t (* first result (ACC) *) *
29                Val.t (* second result (BACC) *))
30  val op1    : op1 -> Val.t -> Val.t
31  val op2    : Val.t (* carry *) -> op2 -> Val.t -> Val.t ->
32               (Val.t (* returned value *) * Val.t (* new carry value *))
33end
34
35(* Not supported: signed division, signed modulo, shift operations. *)
36
37type register
38val compare_reg : register -> register -> int
39val eq_reg      : register -> register -> bool
40
41module RegisterSet : Set.S with type elt = register
42module RegisterMap : Map.S with type key = register
43
44val a : register
45val b : register
46val dpl : register
47val dph : register
48val spl : register
49val sph : register
50val st0 : register
51val st1 : register
52val st2 : register
53val st3 : register
54val sts : register list
55val rets : register list
56val sst : register
57val carry : register (* only used for the liveness analysis *)
58
59val spl_addr : int
60val spl_init : int
61val sph_addr : int
62val sph_init : int
63val isp_addr : int
64val isp_init : int
65
66val registers : RegisterSet.t
67val parameters : register list
68val callee_saved : RegisterSet.t
69val caller_saved : RegisterSet.t
70val allocatable : RegisterSet.t
71val forbidden : RegisterSet.t
72
73val print_register : register -> string
74
75val reg_addr : register -> [> ASM.direct]
76
77val ext_ram_size : int
78val int_ram_size : int
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